Support REG_SEQUENCE in tablegen.
[oota-llvm.git] / lib / Target / R600 / SIInstructions.td
2014-11-02 Matt ArsenaultSupport REG_SEQUENCE in tablegen.
2014-10-21 Matt ArsenaultAdd minnum / maxnum codegen
2014-10-21 Matt ArsenaultR600/SI: Add pattern for bswap
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw xchg
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw xor
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw or
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw min/umin
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw max/umax
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw and
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw sub
2014-10-17 Matt ArsenaultR600/SI: Remove redundant setting of instruction bits
2014-10-17 Matt ArsenaultR600/SI: Use complex pattern for MUBUF load patterns.
2014-10-17 Matt ArsenaultR600/SI: Remove SI_BUFFER_RSRC pseudo
2014-10-16 Matt ArsenaultR600/SI: Remove another VALU pattern
2014-10-16 Matt ArsenaultR600/SI: Remove unnecessary VALU patterns
2014-10-07 Tom StellardR600/SI: Refactor VOP3 instruction defs
2014-10-07 Tom StellardR600/SI: Refactor VOPC instruction defs
2014-10-07 Tom StellardR600/SI: Refactor VOP2 instruction defs
2014-10-07 Tom StellardR600/SI: Refactor VOP1 instruction defs
2014-10-01 Tom StellardR600/SI: Add a generic pseudo EXP instruction
2014-10-01 Tom StellardR600/SI: Add generic pseudo MTBUF instructions
2014-09-25 Tom StellardR600/SI: Add support for global atomic add
2014-09-24 Tom StellardR600/SI: Enable selecting SALU inside branches
2014-09-24 Tom StellardR600/SI: Fix the FixSGPRLiveRanges pass
2014-09-24 Tom StellardR600/SI: Implement VGPR register spilling for compute...
2014-09-22 Tom StellardRevert "R600/SI: Add support for global atomic add"
2014-09-22 Tom StellardR600/SI: Add support for global atomic add
2014-09-22 Tom StellardR600/SI: Remove modifier operands from V_CNDMASK_B32_e64
2014-09-15 Matt ArsenaultR600/SI: Prefer selecting more e64 instruction forms.
2014-09-15 Matt ArsenaultR600/SI: Add preliminary support for flat address space
2014-09-08 Matt ArsenaultR600/SI: Replace LDS atomics with no return versions
2014-09-08 Matt ArsenaultR600/SI: Add InstrMapping for noret atomics.
2014-09-07 Matt ArsenaultR600/SI: Fix register class for some 64-bit atomics
2014-09-05 Matt ArsenaultR600/SI: Use same complex patterns for DS atomics
2014-09-05 Tom StellardR600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of...
2014-09-03 Matt ArsenaultR600/SI: Un-move pattern I forgot to remove in last...
2014-09-03 Matt ArsenaultR600/SI: Try to keep i32 mul on SALU
2014-09-03 Tom StellardR600/SI: Add a pattern for i64 and in a branch
2014-08-29 Matt ArsenaultR600/SI: Use mad for fsub + fmul
2014-08-22 Tom StellardR600/SI: Use READ2/WRITE2 instructions for 64-bit mem...
2014-08-22 Tom StellardR600/SI: Use a ComplexPattern for DS loads and stores
2014-08-21 Tom StellardR600/SI: Use eliminateFrameIndex() to expand SGPR spill...
2014-08-15 Matt ArsenaultR600/SI: Move all fabs / fneg handling to patterns
2014-08-15 Matt ArsenaultR600/SI: Use source modifiers for f64 fneg
2014-08-15 Matt ArsenaultR600/SI: Refactor fneg / fabs patterns
2014-08-15 Matt ArsenaultR600/SI: Add intrinsic for ldexp
2014-08-11 Tom StellardR600/SI: Add an _OFFEN variant MUBUF_STORE_* and use...
2014-08-05 Matt ArsenaultR600/SI: Add definitions for ds_read2st64_ / ds_write2st64_
2014-08-04 Matt ArsenaultR600/SI: Fix definitions for ds_read2 / ds_write2 instr...
2014-08-01 Tom StellardR600/SI: Do abs/neg folding with ComplexPatterns
2014-07-30 Matt ArsenaultR600/SI: Remove redundant setting of bits on instructions.
2014-07-21 Tom StellardR600/SI: Use scratch memory for large private arrays
2014-07-21 Tom StellardR600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET...
2014-07-21 Tom StellardR600/SI: Store constant initializer data in constant...
2014-07-21 Tom StellardR600/SI: Add isCFDepth0 Predicate to SALU addc pattern
2014-07-21 Tom StellardR600/SI: Use VALU for i1 XOR
2014-07-21 Tom StellardR600/SI: Use a custom encoding method for simm16 in...
2014-07-21 Tom StellardR600/SI: Rename SOPP operands to match the encoding...
2014-07-19 Matt ArsenaultR600/SI: implement range reduction for sin/cos
2014-07-17 Tim NorthoverCodeGen: extend f16 conversions to permit types > float.
2014-07-15 Matt ArsenaultR600/SI: Allow using f32 rcp / rsq when denormals not...
2014-07-15 Matt ArsenaultR600/SI: Implement less wrong f32 fdiv
2014-07-11 Marek OlsakR600/SI: Use i32 vectors for resources and samplers
2014-07-11 Marek OlsakR600/SI: add sample and image intrinsics exposing all...
2014-07-10 Matt ArsenaultR600/SI: Add support for llvm.convert.{to|from}.fp16
2014-07-02 Tom StellardR600/SI: Use a ComplexPattern for ADDR64 addressing...
2014-07-02 Tom StellardR600: Promote i64 loads to v2i32
2014-07-02 Tom StellardR600/SI: Add verifier check for immediates in register...
2014-06-24 Tom StellardR600/SI: Use a ComplexPattern for MUBUF stores
2014-06-24 Tom StellardR600: Promote i64 stores to v2i32
2014-06-24 Matt ArsenaultR600: Fix inconsistency in rsq instructions.
2014-06-24 Matt ArsenaultR600/SI: Move pattern to instruction definition
2014-06-23 Matt ArsenaultR600/SI: Fix div_scale intrinsic.
2014-06-20 Tom StellardR600/SI: Add patterns for ctpop inside a branch
2014-06-20 Tom StellardR600/SI: Add a pattern for f32 ftrunc
2014-06-20 Tom StellardR600/SI: Add a VALU pattern for i64 xor
2014-06-19 Matt ArsenaultR600/SI: Add intrinsics for various math instructions.
2014-06-18 Marek OlsakR600/SI: add gather4 and getlod intrinsics (v3)
2014-06-18 Matt ArsenaultR600/SI: Add intrinsics for brev instructions
2014-06-18 Matt ArsenaultR600/SI: Comparisons set vcc.
2014-06-17 Matt ArsenaultR600/SI: Match cttz_zero_undef
2014-06-17 Matt ArsenaultR600/SI: Match ctlz_zero_undef
2014-06-17 Tom StellardR600: Use LDS and vectors for private memory
2014-06-17 Tom StellardR600/SI: Add a pattern for llvm.AMDGPU.barrier.global
2014-06-13 Tom StellardR600: Remove AMDIL instruction and register definitions
2014-06-12 Matt ArsenaultR600: Mostly remove remaining AMDIL intrinsics.
2014-06-12 Matt ArsenaultR600/SI: Use a register set to -1 for data0 on ds_inc...
2014-06-11 Matt ArsenaultR600/SI: Fix bitcast between v2i32 and f64
2014-06-11 Matt ArsenaultR600/SI: Update place using old subtarget predicate
2014-06-11 Matt ArsenaultR600/SI: Add common 64-bit LDS atomics
2014-06-11 Matt ArsenaultR600/SI: Add instruction definitions for 64-bit LDS...
2014-06-11 Matt ArsenaultR600/SI: Add 32-bit LDS atomic cmpxchg
2014-06-11 Matt ArsenaultR600/SI: Use LDS atomic inc / dec
2014-06-11 Matt ArsenaultR600/SI: Add other LDS atomic operations
2014-06-11 Matt ArsenaultR600/SI: Add instruction definitions for more LDS ops
2014-06-11 Matt ArsenaultR600/SI: Fix backwards names for local atomic instructions.
2014-06-11 Matt ArsenaultR600/SI: Refactor local atomics.
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 Matt ArsenaultR600/SI: Fix selection failure on scalar_to_vector
2014-06-10 Tom StellardR600/SI: Fix a crash when spilling SGPRs
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