1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
35 def isCFDepth0 : Predicate<"isCFDepth0()">;
37 def WAIT_FLAG : InstFlag<"printWaitFlag">;
39 let SubtargetPredicate = isSI in {
40 let OtherPredicates = [isCFDepth0] in {
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
48 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
49 // SMRD instructions, because the SGPR_32 register class does not include M0
50 // and writing to M0 from an SMRD instruction will hang the GPU.
51 defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
52 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
53 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
54 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
55 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
57 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
58 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
61 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
62 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
65 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
66 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
69 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
70 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
73 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
74 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
79 //def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
80 //def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
86 let neverHasSideEffects = 1 in {
88 let isMoveImm = 1 in {
89 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
90 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
91 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
92 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
93 } // End isMoveImm = 1
95 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32",
96 [(set i32:$dst, (not i32:$src0))]
99 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64",
100 [(set i64:$dst, (not i64:$src0))]
102 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
103 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
104 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
105 def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
106 } // End neverHasSideEffects = 1
108 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>;
109 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>;
110 def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32",
111 [(set i32:$dst, (ctpop i32:$src0))]
113 def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>;
115 ////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "S_FF0_I32_B32", []>;
116 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>;
117 ////def S_FF1_I32_B32 : SOP1_32 <0x00000013, "S_FF1_I32_B32", []>;
118 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>;
119 def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32",
120 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
122 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
123 def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
124 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
125 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
126 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
128 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
129 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
132 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
133 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
134 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
135 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>;
136 def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>;
137 def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>;
138 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>;
139 def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>;
141 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
143 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>;
144 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>;
145 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>;
146 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>;
147 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>;
148 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>;
149 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>;
150 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>;
152 } // End hasSideEffects = 1
154 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>;
155 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>;
156 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>;
157 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>;
158 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>;
159 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
160 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>;
161 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
162 def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
163 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
165 //===----------------------------------------------------------------------===//
167 //===----------------------------------------------------------------------===//
169 let Defs = [SCC] in { // Carry out goes to SCC
170 let isCommutable = 1 in {
171 def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
172 def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
173 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
175 } // End isCommutable = 1
177 def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
178 def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
179 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
182 let Uses = [SCC] in { // Carry in comes from SCC
183 let isCommutable = 1 in {
184 def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
185 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
186 } // End isCommutable = 1
188 def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
189 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
190 } // End Uses = [SCC]
191 } // End Defs = [SCC]
193 def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
194 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
196 def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
197 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
199 def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
200 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
202 def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
203 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
206 def S_CSELECT_B32 : SOP2 <
207 0x0000000a, (outs SReg_32:$dst),
208 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
212 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
214 def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
215 [(set i32:$dst, (and i32:$src0, i32:$src1))]
218 def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
219 [(set i64:$dst, (and i64:$src0, i64:$src1))]
222 def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
223 [(set i32:$dst, (or i32:$src0, i32:$src1))]
226 def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
227 [(set i64:$dst, (or i64:$src0, i64:$src1))]
230 def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
231 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
234 def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
235 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
237 def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
238 def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
239 def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
240 def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
241 def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
242 def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
243 def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
244 def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
245 def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
246 def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
248 // Use added complexity so these patterns are preferred to the VALU patterns.
249 let AddedComplexity = 1 in {
251 def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
252 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
254 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
255 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
257 def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
258 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
260 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
261 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
263 def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
264 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
266 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
267 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
270 } // End AddedComplexity = 1
272 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
273 def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
274 def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
275 def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
276 def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
277 def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
278 def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
279 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
280 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
282 //===----------------------------------------------------------------------===//
284 //===----------------------------------------------------------------------===//
286 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
287 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
288 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
289 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
290 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
291 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
292 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
293 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
294 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
295 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
296 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
297 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
298 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
299 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
300 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
301 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
302 //def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
304 //===----------------------------------------------------------------------===//
306 //===----------------------------------------------------------------------===//
308 def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
309 def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
312 This instruction is disabled for now until we can figure out how to teach
313 the instruction selector to correctly use the S_CMP* vs V_CMP*
316 When this instruction is enabled the code generator sometimes produces this
319 SCC = S_CMPK_EQ_I32 SGPR0, imm
321 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
323 def S_CMPK_EQ_I32 : SOPK <
324 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
326 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
330 let isCompare = 1 in {
331 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
332 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
333 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>;
334 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>;
335 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>;
336 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>;
337 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>;
338 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>;
339 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>;
340 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>;
341 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>;
342 } // End isCompare = 1
344 let Defs = [SCC], isCommutable = 1 in {
345 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>;
346 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>;
349 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>;
350 def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>;
351 def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>;
352 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
353 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
354 //def EXP : EXP_ <0x00000000, "EXP", []>;
356 } // End let OtherPredicates = [isCFDepth0]
358 //===----------------------------------------------------------------------===//
360 //===----------------------------------------------------------------------===//
362 def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>;
364 let isTerminator = 1 in {
366 def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
373 let isBranch = 1 in {
374 def S_BRANCH : SOPP <
375 0x00000002, (ins brtarget:$target), "S_BRANCH $target",
380 let DisableEncoding = "$scc" in {
381 def S_CBRANCH_SCC0 : SOPP <
382 0x00000004, (ins brtarget:$target, SCCReg:$scc),
383 "S_CBRANCH_SCC0 $target", []
385 def S_CBRANCH_SCC1 : SOPP <
386 0x00000005, (ins brtarget:$target, SCCReg:$scc),
387 "S_CBRANCH_SCC1 $target",
390 } // End DisableEncoding = "$scc"
392 def S_CBRANCH_VCCZ : SOPP <
393 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
394 "S_CBRANCH_VCCZ $target",
397 def S_CBRANCH_VCCNZ : SOPP <
398 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
399 "S_CBRANCH_VCCNZ $target",
403 let DisableEncoding = "$exec" in {
404 def S_CBRANCH_EXECZ : SOPP <
405 0x00000008, (ins brtarget:$target, EXECReg:$exec),
406 "S_CBRANCH_EXECZ $target",
409 def S_CBRANCH_EXECNZ : SOPP <
410 0x00000009, (ins brtarget:$target, EXECReg:$exec),
411 "S_CBRANCH_EXECNZ $target",
414 } // End DisableEncoding = "$exec"
417 } // End isBranch = 1
418 } // End isTerminator = 1
420 let hasSideEffects = 1 in {
421 def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
422 [(int_AMDGPU_barrier_local)]
431 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
434 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
435 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
436 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
438 let Uses = [EXEC] in {
439 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
440 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
442 let DisableEncoding = "$m0";
444 } // End Uses = [EXEC]
446 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
447 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
448 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
449 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
450 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
451 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
452 } // End hasSideEffects
454 //===----------------------------------------------------------------------===//
456 //===----------------------------------------------------------------------===//
458 let isCompare = 1 in {
460 defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
461 defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>;
462 defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>;
463 defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>;
464 defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>;
465 defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">;
466 defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>;
467 defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>;
468 defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>;
469 defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">;
470 defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">;
471 defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">;
472 defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">;
473 defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>;
474 defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">;
475 defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">;
477 let hasSideEffects = 1, Defs = [EXEC] in {
479 defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">;
480 defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">;
481 defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">;
482 defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">;
483 defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">;
484 defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">;
485 defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">;
486 defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">;
487 defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">;
488 defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">;
489 defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">;
490 defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">;
491 defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">;
492 defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">;
493 defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">;
494 defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">;
496 } // End hasSideEffects = 1, Defs = [EXEC]
498 defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">;
499 defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>;
500 defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>;
501 defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>;
502 defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>;
503 defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">;
504 defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>;
505 defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>;
506 defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>;
507 defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">;
508 defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">;
509 defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">;
510 defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">;
511 defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>;
512 defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">;
513 defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">;
515 let hasSideEffects = 1, Defs = [EXEC] in {
517 defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">;
518 defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">;
519 defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">;
520 defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">;
521 defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">;
522 defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">;
523 defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">;
524 defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">;
525 defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">;
526 defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">;
527 defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">;
528 defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">;
529 defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">;
530 defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">;
531 defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">;
532 defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">;
534 } // End hasSideEffects = 1, Defs = [EXEC]
536 defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">;
537 defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">;
538 defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">;
539 defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">;
540 defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">;
541 defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">;
542 defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">;
543 defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">;
544 defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">;
545 defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">;
546 defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">;
547 defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">;
548 defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">;
549 defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">;
550 defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">;
551 defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">;
553 let hasSideEffects = 1, Defs = [EXEC] in {
555 defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">;
556 defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">;
557 defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">;
558 defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">;
559 defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">;
560 defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">;
561 defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">;
562 defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">;
563 defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">;
564 defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">;
565 defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">;
566 defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">;
567 defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">;
568 defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">;
569 defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">;
570 defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">;
572 } // End hasSideEffects = 1, Defs = [EXEC]
574 defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">;
575 defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">;
576 defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">;
577 defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">;
578 defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">;
579 defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">;
580 defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">;
581 defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">;
582 defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">;
583 defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">;
584 defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">;
585 defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">;
586 defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">;
587 defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">;
588 defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">;
589 defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">;
591 let hasSideEffects = 1, Defs = [EXEC] in {
593 defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">;
594 defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">;
595 defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">;
596 defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">;
597 defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">;
598 defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">;
599 defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">;
600 defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">;
601 defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">;
602 defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">;
603 defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">;
604 defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">;
605 defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">;
606 defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">;
607 defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">;
608 defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">;
610 } // End hasSideEffects = 1, Defs = [EXEC]
612 defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">;
613 defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>;
614 defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>;
615 defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>;
616 defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>;
617 defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>;
618 defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>;
619 defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">;
621 let hasSideEffects = 1, Defs = [EXEC] in {
623 defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">;
624 defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">;
625 defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">;
626 defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">;
627 defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">;
628 defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">;
629 defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">;
630 defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">;
632 } // End hasSideEffects = 1, Defs = [EXEC]
634 defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">;
635 defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>;
636 defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>;
637 defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>;
638 defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>;
639 defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>;
640 defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>;
641 defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">;
643 let hasSideEffects = 1, Defs = [EXEC] in {
645 defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">;
646 defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">;
647 defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">;
648 defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">;
649 defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">;
650 defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">;
651 defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">;
652 defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">;
654 } // End hasSideEffects = 1, Defs = [EXEC]
656 defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">;
657 defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>;
658 defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>;
659 defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>;
660 defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>;
661 defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>;
662 defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>;
663 defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">;
665 let hasSideEffects = 1, Defs = [EXEC] in {
667 defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">;
668 defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">;
669 defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">;
670 defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">;
671 defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">;
672 defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">;
673 defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">;
674 defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">;
676 } // End hasSideEffects = 1, Defs = [EXEC]
678 defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">;
679 defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>;
680 defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>;
681 defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>;
682 defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>;
683 defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>;
684 defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>;
685 defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">;
687 let hasSideEffects = 1, Defs = [EXEC] in {
689 defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">;
690 defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">;
691 defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">;
692 defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">;
693 defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">;
694 defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">;
695 defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">;
696 defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">;
698 } // End hasSideEffects = 1, Defs = [EXEC]
700 defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">;
702 let hasSideEffects = 1, Defs = [EXEC] in {
703 defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
704 } // End hasSideEffects = 1, Defs = [EXEC]
706 defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
708 let hasSideEffects = 1, Defs = [EXEC] in {
709 defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
710 } // End hasSideEffects = 1, Defs = [EXEC]
712 } // End isCompare = 1
714 //===----------------------------------------------------------------------===//
716 //===----------------------------------------------------------------------===//
719 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "DS_ADD_U32", VReg_32>;
720 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "DS_SUB_U32", VReg_32>;
721 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "DS_RSUB_U32", VReg_32>;
722 def DS_INC_U32 : DS_1A1D_NORET <0x3, "DS_INC_U32", VReg_32>;
723 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "DS_DEC_U32", VReg_32>;
724 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "DS_MIN_I32", VReg_32>;
725 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "DS_MAX_I32", VReg_32>;
726 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "DS_MIN_U32", VReg_32>;
727 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "DS_MAX_U32", VReg_32>;
728 def DS_AND_B32 : DS_1A1D_NORET <0x9, "DS_AND_B32", VReg_32>;
729 def DS_OR_B32 : DS_1A1D_NORET <0xa, "DS_OR_B32", VReg_32>;
730 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "DS_XOR_B32", VReg_32>;
731 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "DS_MSKOR_B32", VReg_32>;
732 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "DS_CMPST_B32", VReg_32>;
733 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "DS_CMPST_F32", VReg_32>;
734 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "DS_MIN_F32", VReg_32>;
735 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "DS_MAX_F32", VReg_32>;
737 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "DS_ADD_RTN_U32", VReg_32>;
738 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "DS_SUB_RTN_U32", VReg_32>;
739 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "DS_RSUB_RTN_U32", VReg_32>;
740 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "DS_INC_RTN_U32", VReg_32>;
741 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "DS_DEC_RTN_U32", VReg_32>;
742 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "DS_MIN_RTN_I32", VReg_32>;
743 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "DS_MAX_RTN_I32", VReg_32>;
744 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "DS_MIN_RTN_U32", VReg_32>;
745 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "DS_MAX_RTN_U32", VReg_32>;
746 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "DS_AND_RTN_B32", VReg_32>;
747 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "DS_OR_RTN_B32", VReg_32>;
748 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "DS_XOR_RTN_B32", VReg_32>;
749 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "DS_MSKOR_RTN_B32", VReg_32>;
750 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "DS_WRXCHG_RTN_B32", VReg_32>;
751 //def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "DS_WRXCHG2_RTN_B32", VReg_32>;
752 //def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "DS_WRXCHG2_RTN_B32", VReg_32>;
753 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "DS_CMPST_RTN_B32", VReg_32>;
754 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "DS_CMPST_RTN_F32", VReg_32>;
755 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "DS_MIN_RTN_F32", VReg_32>;
756 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "DS_MAX_RTN_F32", VReg_32>;
758 let SubtargetPredicate = isCI in {
759 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "DS_WRAP_RTN_F32", VReg_32>;
763 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "DS_ADD_U64", VReg_32>;
764 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "DS_SUB_U64", VReg_32>;
765 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "DS_RSUB_U64", VReg_32>;
766 def DS_INC_U64 : DS_1A1D_NORET <0x43, "DS_INC_U64", VReg_32>;
767 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "DS_DEC_U64", VReg_32>;
768 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "DS_MIN_I64", VReg_64>;
769 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "DS_MAX_I64", VReg_64>;
770 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "DS_MIN_U64", VReg_64>;
771 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "DS_MAX_U64", VReg_64>;
772 def DS_AND_B64 : DS_1A1D_NORET <0x49, "DS_AND_B64", VReg_64>;
773 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "DS_OR_B64", VReg_64>;
774 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "DS_XOR_B64", VReg_64>;
775 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "DS_MSKOR_B64", VReg_64>;
776 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "DS_CMPST_B64", VReg_64>;
777 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "DS_CMPST_F64", VReg_64>;
778 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "DS_MIN_F64", VReg_64>;
779 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "DS_MAX_F64", VReg_64>;
781 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "DS_ADD_RTN_U64", VReg_64>;
782 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "DS_SUB_RTN_U64", VReg_64>;
783 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "DS_RSUB_RTN_U64", VReg_64>;
784 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "DS_INC_RTN_U64", VReg_64>;
785 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "DS_DEC_RTN_U64", VReg_64>;
786 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "DS_MIN_RTN_I64", VReg_64>;
787 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "DS_MAX_RTN_I64", VReg_64>;
788 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "DS_MIN_RTN_U64", VReg_64>;
789 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "DS_MAX_RTN_U64", VReg_64>;
790 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "DS_AND_RTN_B64", VReg_64>;
791 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "DS_OR_RTN_B64", VReg_64>;
792 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "DS_XOR_RTN_B64", VReg_64>;
793 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "DS_MSKOR_RTN_B64", VReg_64>;
794 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "DS_WRXCHG_RTN_B64", VReg_64>;
795 //def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "DS_WRXCHG2_RTN_B64", VReg_64>;
796 //def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "DS_WRXCHG2_RTN_B64", VReg_64>;
797 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "DS_CMPST_RTN_B64", VReg_64>;
798 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "DS_CMPST_RTN_F64", VReg_64>;
799 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "DS_MIN_F64", VReg_64>;
800 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64>;
802 //let SubtargetPredicate = isCI in {
803 // DS_CONDXCHG32_RTN_B64
804 // DS_CONDXCHG32_RTN_B128
807 // TODO: _SRC2_* forms
809 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
810 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
811 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
812 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "DS_WRITE_B64", VReg_64>;
814 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
815 def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>;
816 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>;
817 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>;
818 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>;
819 def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>;
822 def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>;
823 def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>;
825 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>;
826 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
828 // TODO: DS_READ2ST64_B32, DS_READ2ST64_B64,
829 // DS_WRITE2ST64_B32, DS_WRITE2ST64_B64
831 //===----------------------------------------------------------------------===//
832 // MUBUF Instructions
833 //===----------------------------------------------------------------------===//
835 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
836 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
837 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>;
838 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>;
839 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>;
840 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>;
841 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>;
842 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>;
843 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>;
844 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>;
845 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>;
846 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>;
847 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>;
848 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>;
849 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>;
851 def BUFFER_STORE_BYTE : MUBUF_Store_Helper <
852 0x00000018, "BUFFER_STORE_BYTE", VReg_32
855 def BUFFER_STORE_SHORT : MUBUF_Store_Helper <
856 0x0000001a, "BUFFER_STORE_SHORT", VReg_32
859 def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
860 0x0000001c, "BUFFER_STORE_DWORD", VReg_32
863 def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
864 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64
867 def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
868 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128
870 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
871 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
872 //def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
873 //def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>;
874 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>;
875 //def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>;
876 //def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>;
877 //def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>;
878 //def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>;
879 //def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>;
880 //def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>;
881 //def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>;
882 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>;
883 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>;
884 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>;
885 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>;
886 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>;
887 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>;
888 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>;
889 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>;
890 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>;
891 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>;
892 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>;
893 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>;
894 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>;
895 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>;
896 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>;
897 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>;
898 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>;
899 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>;
900 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>;
901 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>;
902 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>;
903 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
904 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
905 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
907 //===----------------------------------------------------------------------===//
908 // MTBUF Instructions
909 //===----------------------------------------------------------------------===//
911 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
912 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
913 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
914 def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
915 def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
916 def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
917 def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
918 def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
920 //===----------------------------------------------------------------------===//
922 //===----------------------------------------------------------------------===//
924 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
925 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
926 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
927 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>;
928 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>;
929 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>;
930 //def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>;
931 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>;
932 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>;
933 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>;
934 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">;
935 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>;
936 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>;
937 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>;
938 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>;
939 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>;
940 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>;
941 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>;
942 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>;
943 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>;
944 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>;
945 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>;
946 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>;
947 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>;
948 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>;
949 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>;
950 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>;
951 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>;
952 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">;
953 //def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>;
954 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">;
955 //def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>;
956 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">;
957 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">;
958 //def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>;
959 //def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>;
960 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">;
961 //def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>;
962 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">;
963 //def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>;
964 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">;
965 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
966 //def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>;
967 //def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>;
968 //def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>;
969 //def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>;
970 //def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>;
971 //def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>;
972 //def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>;
973 //def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>;
974 //def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>;
975 //def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>;
976 //def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>;
977 //def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>;
978 //def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>;
979 //def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>;
980 //def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>;
981 //def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>;
982 //def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>;
983 //def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>;
984 //def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>;
985 //def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>;
986 //def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>;
987 //def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>;
988 //def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>;
989 //def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>;
990 //def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>;
991 //def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>;
992 //def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>;
993 //def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>;
994 //def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>;
995 //def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>;
996 //def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>;
997 //def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>;
998 //def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>;
999 //def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>;
1000 //def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>;
1001 //def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>;
1002 //def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>;
1003 //def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>;
1004 //def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>;
1005 //def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>;
1006 //def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>;
1007 //def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>;
1008 //def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>;
1009 //def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>;
1010 //def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>;
1011 //def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>;
1012 //def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>;
1013 //def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>;
1014 //def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>;
1015 //def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>;
1016 //def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
1017 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
1018 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
1020 //===----------------------------------------------------------------------===//
1021 // VOP1 Instructions
1022 //===----------------------------------------------------------------------===//
1024 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
1026 let neverHasSideEffects = 1, isMoveImm = 1 in {
1027 defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
1028 } // End neverHasSideEffects = 1, isMoveImm = 1
1030 let Uses = [EXEC] in {
1032 def V_READFIRSTLANE_B32 : VOP1 <
1034 (outs SReg_32:$vdst),
1035 (ins VReg_32:$src0),
1036 "V_READFIRSTLANE_B32 $vdst, $src0",
1042 defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
1043 [(set i32:$dst, (fp_to_sint f64:$src0))]
1045 defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
1046 [(set f64:$dst, (sint_to_fp i32:$src0))]
1048 defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
1049 [(set f32:$dst, (sint_to_fp i32:$src0))]
1051 defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32",
1052 [(set f32:$dst, (uint_to_fp i32:$src0))]
1054 defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32",
1055 [(set i32:$dst, (fp_to_uint f32:$src0))]
1057 defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32",
1058 [(set i32:$dst, (fp_to_sint f32:$src0))]
1060 defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
1061 ////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>;
1062 //defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>;
1063 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
1064 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
1065 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
1066 defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
1067 [(set f32:$dst, (fround f64:$src0))]
1069 defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
1070 [(set f64:$dst, (fextend f32:$src0))]
1072 defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0",
1073 [(set f32:$dst, (AMDGPUcvt_f32_ubyte0 i32:$src0))]
1075 defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1",
1076 [(set f32:$dst, (AMDGPUcvt_f32_ubyte1 i32:$src0))]
1078 defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2",
1079 [(set f32:$dst, (AMDGPUcvt_f32_ubyte2 i32:$src0))]
1081 defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3",
1082 [(set f32:$dst, (AMDGPUcvt_f32_ubyte3 i32:$src0))]
1084 defm V_CVT_U32_F64 : VOP1_32_64 <0x00000015, "V_CVT_U32_F64",
1085 [(set i32:$dst, (fp_to_uint f64:$src0))]
1087 defm V_CVT_F64_U32 : VOP1_64_32 <0x00000016, "V_CVT_F64_U32",
1088 [(set f64:$dst, (uint_to_fp i32:$src0))]
1091 defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32",
1092 [(set f32:$dst, (AMDGPUfract f32:$src0))]
1094 defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32",
1095 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))]
1097 defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32",
1098 [(set f32:$dst, (fceil f32:$src0))]
1100 defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32",
1101 [(set f32:$dst, (frint f32:$src0))]
1103 defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32",
1104 [(set f32:$dst, (ffloor f32:$src0))]
1106 defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32",
1107 [(set f32:$dst, (fexp2 f32:$src0))]
1109 defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>;
1110 defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32",
1111 [(set f32:$dst, (flog2 f32:$src0))]
1113 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
1114 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
1115 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
1116 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))]
1118 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
1119 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
1120 defm V_RSQ_LEGACY_F32 : VOP1_32 <
1121 0x0000002d, "V_RSQ_LEGACY_F32",
1122 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))]
1124 defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32",
1125 [(set f32:$dst, (fdiv FP_ONE, (fsqrt f32:$src0)))]
1127 defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64",
1128 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))]
1130 defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>;
1131 defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64",
1132 [(set f64:$dst, (fdiv FP_ONE, (fsqrt f64:$src0)))]
1134 defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>;
1135 defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32",
1136 [(set f32:$dst, (fsqrt f32:$src0))]
1138 defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64",
1139 [(set f64:$dst, (fsqrt f64:$src0))]
1141 defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>;
1142 defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>;
1143 defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>;
1144 defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>;
1145 defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>;
1146 defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>;
1147 defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>;
1148 //defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>;
1149 defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>;
1150 defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>;
1151 //defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>;
1152 defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>;
1153 //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
1154 defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
1155 defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
1156 defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
1159 //===----------------------------------------------------------------------===//
1160 // VINTRP Instructions
1161 //===----------------------------------------------------------------------===//
1163 def V_INTERP_P1_F32 : VINTRP <
1165 (outs VReg_32:$dst),
1166 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1167 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]",
1169 let DisableEncoding = "$m0";
1172 def V_INTERP_P2_F32 : VINTRP <
1174 (outs VReg_32:$dst),
1175 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1176 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1179 let Constraints = "$src0 = $dst";
1180 let DisableEncoding = "$src0,$m0";
1184 def V_INTERP_MOV_F32 : VINTRP <
1186 (outs VReg_32:$dst),
1187 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1188 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
1190 let DisableEncoding = "$m0";
1193 //===----------------------------------------------------------------------===//
1194 // VOP2 Instructions
1195 //===----------------------------------------------------------------------===//
1197 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1198 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1199 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
1202 let DisableEncoding = "$vcc";
1205 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1206 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
1207 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
1208 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
1209 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1211 let src0_modifiers = 0;
1212 let src1_modifiers = 0;
1213 let src2_modifiers = 0;
1216 def V_READLANE_B32 : VOP2 <
1218 (outs SReg_32:$vdst),
1219 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1220 "V_READLANE_B32 $vdst, $src0, $vsrc1",
1224 def V_WRITELANE_B32 : VOP2 <
1226 (outs VReg_32:$vdst),
1227 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1228 "V_WRITELANE_B32 $vdst, $src0, $vsrc1",
1232 let isCommutable = 1 in {
1233 defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32",
1234 [(set f32:$dst, (fadd f32:$src0, f32:$src1))]
1237 defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
1238 [(set f32:$dst, (fsub f32:$src0, f32:$src1))]
1240 defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">;
1241 } // End isCommutable = 1
1243 defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
1245 let isCommutable = 1 in {
1247 defm V_MUL_LEGACY_F32 : VOP2_32 <
1248 0x00000007, "V_MUL_LEGACY_F32",
1249 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))]
1252 defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32",
1253 [(set f32:$dst, (fmul f32:$src0, f32:$src1))]
1257 defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
1258 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))]
1260 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
1261 defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
1262 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))]
1264 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
1267 defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
1268 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]
1271 defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
1272 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))]
1275 defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
1276 defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
1277 defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
1278 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>;
1279 defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
1280 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>;
1281 defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
1282 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>;
1283 defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
1284 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>;
1286 defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
1287 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
1290 defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
1292 defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
1293 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
1295 defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
1297 let hasPostISelHook = 1 in {
1299 defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
1300 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
1304 defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
1306 defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
1307 [(set i32:$dst, (and i32:$src0, i32:$src1))]>;
1308 defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
1309 [(set i32:$dst, (or i32:$src0, i32:$src1))]
1311 defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
1312 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
1315 } // End isCommutable = 1
1317 defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32",
1318 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
1319 defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>;
1320 defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>;
1321 defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
1322 defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>;
1323 defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
1324 defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
1326 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1327 // No patterns so that the scalar instructions are always selected.
1328 // The scalar versions will be replaced with vector when needed later.
1329 defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
1330 [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>;
1331 defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
1332 [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>;
1333 defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
1336 let Uses = [VCC] in { // Carry-in comes from VCC
1337 defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32",
1338 [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>;
1339 defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32",
1340 [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>;
1341 defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
1343 } // End Uses = [VCC]
1344 } // End isCommutable = 1, Defs = [VCC]
1346 defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
1347 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
1348 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
1349 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>;
1350 defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
1351 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))]
1353 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
1354 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
1356 //===----------------------------------------------------------------------===//
1357 // VOP3 Instructions
1358 //===----------------------------------------------------------------------===//
1360 let neverHasSideEffects = 1 in {
1362 defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
1363 defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32",
1364 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
1366 defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
1367 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))]
1369 defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
1370 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))]
1373 } // End neverHasSideEffects
1375 defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
1376 defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
1377 defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
1378 defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
1380 let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
1381 defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
1382 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
1383 defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
1384 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
1387 defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
1388 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>;
1389 defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
1390 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
1392 def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
1393 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
1395 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
1396 defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
1398 defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
1399 defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
1400 ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
1401 ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
1402 ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
1403 ////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>;
1404 ////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>;
1405 ////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>;
1406 ////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>;
1407 ////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>;
1408 ////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>;
1409 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
1410 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
1411 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
1412 defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
1413 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
1414 defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
1415 def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
1417 def V_LSHL_B64 : VOP3_64_32 <0x00000161, "V_LSHL_B64",
1418 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
1420 def V_LSHR_B64 : VOP3_64_32 <0x00000162, "V_LSHR_B64",
1421 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
1423 def V_ASHR_I64 : VOP3_64_32 <0x00000163, "V_ASHR_I64",
1424 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
1427 let isCommutable = 1 in {
1429 def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>;
1430 def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>;
1431 def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>;
1432 def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>;
1434 } // isCommutable = 1
1436 def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
1438 let isCommutable = 1 in {
1440 defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
1441 defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
1442 defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
1443 defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
1445 } // isCommutable = 1
1447 defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
1448 def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
1449 defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
1450 def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
1451 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
1452 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
1453 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
1454 def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
1456 //===----------------------------------------------------------------------===//
1457 // Pseudo Instructions
1458 //===----------------------------------------------------------------------===//
1460 let isCodeGenOnly = 1, isPseudo = 1 in {
1462 def V_MOV_I1 : InstSI <
1465 "", [(set i1:$dst, (imm:$src))]
1468 def V_AND_I1 : InstSI <
1469 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1470 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1473 def V_OR_I1 : InstSI <
1474 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1475 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1478 // SI pseudo instructions. These are used by the CFG structurizer pass
1479 // and should be lowered to ISA instructions prior to codegen.
1481 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1482 Uses = [EXEC], Defs = [EXEC] in {
1484 let isBranch = 1, isTerminator = 1 in {
1487 (outs SReg_64:$dst),
1488 (ins SReg_64:$vcc, brtarget:$target),
1490 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1493 def SI_ELSE : InstSI <
1494 (outs SReg_64:$dst),
1495 (ins SReg_64:$src, brtarget:$target),
1497 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1499 let Constraints = "$src = $dst";
1502 def SI_LOOP : InstSI <
1504 (ins SReg_64:$saved, brtarget:$target),
1505 "SI_LOOP $saved, $target",
1506 [(int_SI_loop i64:$saved, bb:$target)]
1509 } // end isBranch = 1, isTerminator = 1
1511 def SI_BREAK : InstSI <
1512 (outs SReg_64:$dst),
1514 "SI_ELSE $dst, $src",
1515 [(set i64:$dst, (int_SI_break i64:$src))]
1518 def SI_IF_BREAK : InstSI <
1519 (outs SReg_64:$dst),
1520 (ins SReg_64:$vcc, SReg_64:$src),
1521 "SI_IF_BREAK $dst, $vcc, $src",
1522 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1525 def SI_ELSE_BREAK : InstSI <
1526 (outs SReg_64:$dst),
1527 (ins SReg_64:$src0, SReg_64:$src1),
1528 "SI_ELSE_BREAK $dst, $src0, $src1",
1529 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1532 def SI_END_CF : InstSI <
1534 (ins SReg_64:$saved),
1536 [(int_SI_end_cf i64:$saved)]
1539 def SI_KILL : InstSI <
1543 [(int_AMDGPU_kill f32:$src)]
1546 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1547 // Uses = [EXEC], Defs = [EXEC]
1549 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1551 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1553 let UseNamedOperandTable = 1 in {
1555 def SI_RegisterLoad : InstSI <
1556 (outs VReg_32:$dst, SReg_64:$temp),
1557 (ins FRAMEri32:$addr, i32imm:$chan),
1560 let isRegisterLoad = 1;
1564 class SIRegStore<dag outs> : InstSI <
1566 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1569 let isRegisterStore = 1;
1573 let usesCustomInserter = 1 in {
1574 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1575 } // End usesCustomInserter = 1
1576 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1579 } // End UseNamedOperandTable = 1
1581 def SI_INDIRECT_SRC : InstSI <
1582 (outs VReg_32:$dst, SReg_64:$temp),
1583 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1584 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
1588 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1589 (outs rc:$dst, SReg_64:$temp),
1590 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1591 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
1594 let Constraints = "$src = $dst";
1597 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1598 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1599 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1600 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1601 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1603 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1605 let usesCustomInserter = 1 in {
1607 // This pseudo instruction takes a pointer as input and outputs a resource
1608 // constant that can be used with the ADDR64 MUBUF instructions.
1609 def SI_ADDR64_RSRC : InstSI <
1610 (outs SReg_128:$srsrc),
1615 def V_SUB_F64 : InstSI <
1616 (outs VReg_64:$dst),
1617 (ins VReg_64:$src0, VReg_64:$src1),
1618 "V_SUB_F64 $dst, $src0, $src1",
1622 } // end usesCustomInserter
1624 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1626 def _SAVE : InstSI <
1627 (outs VReg_32:$dst),
1628 (ins sgpr_class:$src, i32imm:$frame_idx),
1632 def _RESTORE : InstSI <
1633 (outs sgpr_class:$dst),
1634 (ins VReg_32:$src, i32imm:$frame_idx),
1640 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1641 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1642 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1643 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1644 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1646 } // end IsCodeGenOnly, isPseudo
1648 } // end SubtargetPredicate = SI
1650 let Predicates = [isSI] in {
1653 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1654 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0))
1659 (SI_KILL 0xbf800000)
1662 /* int_SI_vs_load_input */
1664 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
1665 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1670 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1671 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1672 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1673 $src0, $src1, $src2, $src3)
1677 (f64 (fsub f64:$src0, f64:$src1)),
1678 (V_SUB_F64 $src0, $src1)
1681 //===----------------------------------------------------------------------===//
1683 //===----------------------------------------------------------------------===//
1685 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1687 // 1. Offset as 8bit DWORD immediate
1689 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1690 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1693 // 2. Offset loaded in an 32bit SGPR
1695 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1696 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1699 // 3. No offset at all
1701 (constant_load i64:$sbase),
1702 (vt (Instr_IMM $sbase, 0))
1706 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1707 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1708 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
1709 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1710 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1711 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1712 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1713 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1715 // 1. Offset as 8bit DWORD immediate
1717 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1718 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1721 // 2. Offset loaded in an 32bit SGPR
1723 (SIload_constant v4i32:$sbase, imm:$offset),
1724 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1727 //===----------------------------------------------------------------------===//
1729 //===----------------------------------------------------------------------===//
1732 (i1 (xor i1:$src0, i1:$src1)),
1733 (S_XOR_B64 $src0, $src1)
1736 //===----------------------------------------------------------------------===//
1738 //===----------------------------------------------------------------------===//
1741 (int_AMDGPU_barrier_global),
1745 //===----------------------------------------------------------------------===//
1747 //===----------------------------------------------------------------------===//
1750 (or i64:$src0, i64:$src1),
1751 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1752 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
1753 (EXTRACT_SUBREG i64:$src1, sub0)), sub0),
1754 (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
1755 (EXTRACT_SUBREG i64:$src1, sub1)), sub1)
1758 class SextInReg <ValueType vt, int ShiftAmt> : Pat <
1759 (sext_inreg i32:$src0, vt),
1760 (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
1763 def : SextInReg <i8, 24>;
1764 def : SextInReg <i16, 16>;
1766 /********** ======================= **********/
1767 /********** Image sampling patterns **********/
1768 /********** ======================= **********/
1770 /* SIsample for simple 1D texture lookup */
1772 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1773 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1776 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1777 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
1778 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1781 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1782 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
1783 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1786 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
1787 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
1788 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1791 class SampleShadowPattern<SDNode name, MIMG opcode,
1792 ValueType vt> : Pat <
1793 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
1794 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1797 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
1798 ValueType vt> : Pat <
1799 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
1800 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
1803 /* SIsample* for texture lookups consuming more address parameters */
1804 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
1805 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
1806 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
1807 def : SamplePattern <SIsample, sample, addr_type>;
1808 def : SampleRectPattern <SIsample, sample, addr_type>;
1809 def : SampleArrayPattern <SIsample, sample, addr_type>;
1810 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
1811 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
1813 def : SamplePattern <SIsamplel, sample_l, addr_type>;
1814 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
1815 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
1816 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
1818 def : SamplePattern <SIsampleb, sample_b, addr_type>;
1819 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
1820 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
1821 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
1823 def : SamplePattern <SIsampled, sample_d, addr_type>;
1824 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
1825 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
1826 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
1829 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
1830 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
1831 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
1832 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
1834 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
1835 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
1836 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
1837 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
1839 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
1840 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
1841 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
1842 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
1844 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
1845 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
1846 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
1847 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
1850 /* int_SI_imageload for texture fetches consuming varying address parameters */
1851 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1852 (name addr_type:$addr, v32i8:$rsrc, imm),
1853 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1856 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1857 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
1858 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1861 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1862 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
1863 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
1866 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
1867 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
1868 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
1871 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
1872 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
1873 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
1876 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
1877 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
1878 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
1881 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
1882 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
1884 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
1885 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
1887 /* Image resource information */
1889 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
1890 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1894 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
1895 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1899 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
1900 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
1903 /********** ============================================ **********/
1904 /********** Extraction, Insertion, Building and Casting **********/
1905 /********** ============================================ **********/
1907 foreach Index = 0-2 in {
1908 def Extract_Element_v2i32_#Index : Extract_Element <
1909 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1911 def Insert_Element_v2i32_#Index : Insert_Element <
1912 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1915 def Extract_Element_v2f32_#Index : Extract_Element <
1916 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1918 def Insert_Element_v2f32_#Index : Insert_Element <
1919 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1923 foreach Index = 0-3 in {
1924 def Extract_Element_v4i32_#Index : Extract_Element <
1925 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1927 def Insert_Element_v4i32_#Index : Insert_Element <
1928 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1931 def Extract_Element_v4f32_#Index : Extract_Element <
1932 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1934 def Insert_Element_v4f32_#Index : Insert_Element <
1935 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1939 foreach Index = 0-7 in {
1940 def Extract_Element_v8i32_#Index : Extract_Element <
1941 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1943 def Insert_Element_v8i32_#Index : Insert_Element <
1944 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1947 def Extract_Element_v8f32_#Index : Extract_Element <
1948 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1950 def Insert_Element_v8f32_#Index : Insert_Element <
1951 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1955 foreach Index = 0-15 in {
1956 def Extract_Element_v16i32_#Index : Extract_Element <
1957 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1959 def Insert_Element_v16i32_#Index : Insert_Element <
1960 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1963 def Extract_Element_v16f32_#Index : Extract_Element <
1964 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1966 def Insert_Element_v16f32_#Index : Insert_Element <
1967 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1971 def : BitConvert <i32, f32, SReg_32>;
1972 def : BitConvert <i32, f32, VReg_32>;
1974 def : BitConvert <f32, i32, SReg_32>;
1975 def : BitConvert <f32, i32, VReg_32>;
1977 def : BitConvert <i64, f64, VReg_64>;
1979 def : BitConvert <f64, i64, VReg_64>;
1981 def : BitConvert <v2f32, v2i32, VReg_64>;
1982 def : BitConvert <v2i32, v2f32, VReg_64>;
1983 def : BitConvert <v2i32, i64, VReg_64>;
1984 def : BitConvert <i64, v2i32, VReg_64>;
1985 def : BitConvert <v2f32, i64, VReg_64>;
1986 def : BitConvert <i64, v2f32, VReg_64>;
1987 def : BitConvert <v2i32, f64, VReg_64>;
1988 def : BitConvert <f64, v2i32, VReg_64>;
1989 def : BitConvert <v4f32, v4i32, VReg_128>;
1990 def : BitConvert <v4i32, v4f32, VReg_128>;
1992 def : BitConvert <v8f32, v8i32, SReg_256>;
1993 def : BitConvert <v8i32, v8f32, SReg_256>;
1994 def : BitConvert <v8i32, v32i8, SReg_256>;
1995 def : BitConvert <v32i8, v8i32, SReg_256>;
1996 def : BitConvert <v8i32, v32i8, VReg_256>;
1997 def : BitConvert <v8i32, v8f32, VReg_256>;
1998 def : BitConvert <v8f32, v8i32, VReg_256>;
1999 def : BitConvert <v32i8, v8i32, VReg_256>;
2001 def : BitConvert <v16i32, v16f32, VReg_512>;
2002 def : BitConvert <v16f32, v16i32, VReg_512>;
2004 /********** =================== **********/
2005 /********** Src & Dst modifiers **********/
2006 /********** =================== **********/
2008 def FCLAMP_SI : AMDGPUShaderInst <
2009 (outs VReg_32:$dst),
2010 (ins VSrc_32:$src0),
2011 "FCLAMP_SI $dst, $src0",
2014 let usesCustomInserter = 1;
2018 (AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
2019 (FCLAMP_SI f32:$src)
2022 /********** ================================ **********/
2023 /********** Floating point absolute/negative **********/
2024 /********** ================================ **********/
2026 // Manipulate the sign bit directly, as e.g. using the source negation modifier
2027 // in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
2028 // breaking the piglit *s-floatBitsToInt-neg* tests
2030 // TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
2031 // removing these patterns
2034 (fneg (fabs f32:$src)),
2035 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2038 def FABS_SI : AMDGPUShaderInst <
2039 (outs VReg_32:$dst),
2040 (ins VSrc_32:$src0),
2041 "FABS_SI $dst, $src0",
2044 let usesCustomInserter = 1;
2052 def FNEG_SI : AMDGPUShaderInst <
2053 (outs VReg_32:$dst),
2054 (ins VSrc_32:$src0),
2055 "FNEG_SI $dst, $src0",
2058 let usesCustomInserter = 1;
2066 /********** ================== **********/
2067 /********** Immediate Patterns **********/
2068 /********** ================== **********/
2071 (SGPRImm<(i32 imm)>:$imm),
2072 (S_MOV_B32 imm:$imm)
2076 (SGPRImm<(f32 fpimm)>:$imm),
2077 (S_MOV_B32 fpimm:$imm)
2082 (V_MOV_B32_e32 imm:$imm)
2087 (V_MOV_B32_e32 fpimm:$imm)
2091 (i64 InlineImm<i64>:$imm),
2092 (S_MOV_B64 InlineImm<i64>:$imm)
2095 /********** ===================== **********/
2096 /********** Interpolation Paterns **********/
2097 /********** ===================== **********/
2100 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2101 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2105 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2106 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2107 imm:$attr_chan, imm:$attr, i32:$params),
2108 (EXTRACT_SUBREG $ij, sub1),
2109 imm:$attr_chan, imm:$attr, $params)
2112 /********** ================== **********/
2113 /********** Intrinsic Patterns **********/
2114 /********** ================== **********/
2116 /* llvm.AMDGPU.pow */
2117 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2120 (int_AMDGPU_div f32:$src0, f32:$src1),
2121 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2125 (fdiv f32:$src0, f32:$src1),
2126 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1))
2130 (fdiv f64:$src0, f64:$src1),
2131 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0))
2136 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2141 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
2145 (int_AMDGPU_cube v4f32:$src),
2146 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2147 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
2148 (EXTRACT_SUBREG $src, sub1),
2149 (EXTRACT_SUBREG $src, sub2)),
2151 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
2152 (EXTRACT_SUBREG $src, sub1),
2153 (EXTRACT_SUBREG $src, sub2)),
2155 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
2156 (EXTRACT_SUBREG $src, sub1),
2157 (EXTRACT_SUBREG $src, sub2)),
2159 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
2160 (EXTRACT_SUBREG $src, sub1),
2161 (EXTRACT_SUBREG $src, sub2)),
2166 (i32 (sext i1:$src0)),
2167 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2170 class Ext32Pat <SDNode ext> : Pat <
2171 (i32 (ext i1:$src0)),
2172 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2175 def : Ext32Pat <zext>;
2176 def : Ext32Pat <anyext>;
2178 // Offset in an 32Bit VGPR
2180 (SIload_constant v4i32:$sbase, i32:$voff),
2181 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
2184 // The multiplication scales from [0,1] to the unsigned integer range
2186 (AMDGPUurecip i32:$src0),
2188 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2189 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2194 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2195 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0))
2198 //===----------------------------------------------------------------------===//
2200 //===----------------------------------------------------------------------===//
2202 def : IMad24Pat<V_MAD_I32_I24>;
2203 def : UMad24Pat<V_MAD_U32_U24>;
2206 (fadd f64:$src0, f64:$src1),
2207 (V_ADD_F64 $src0, $src1, (i64 0))
2211 (fmul f64:$src0, f64:$src1),
2212 (V_MUL_F64 $src0, $src1, (i64 0))
2216 (mul i32:$src0, i32:$src1),
2217 (V_MUL_LO_I32 $src0, $src1, (i32 0))
2221 (mulhu i32:$src0, i32:$src1),
2222 (V_MUL_HI_U32 $src0, $src1, (i32 0))
2226 (mulhs i32:$src0, i32:$src1),
2227 (V_MUL_HI_I32 $src0, $src1, (i32 0))
2230 defm : BFIPatterns <V_BFI_B32, S_MOV_B32>;
2231 def : ROTRPattern <V_ALIGNBIT_B32>;
2233 /********** ======================= **********/
2234 /********** Load/Store Patterns **********/
2235 /********** ======================= **********/
2237 multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
2239 (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
2240 (inst (i1 0), $ptr, (as_i16imm $offset))
2245 (vt (inst 0, $src0, 0))
2249 defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2250 defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2251 defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2252 defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2253 defm : DSReadPat <DS_READ_B32, i32, local_load>;
2254 defm : DSReadPat <DS_READ_B64, i64, local_load>;
2256 multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
2258 (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
2259 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2263 (frag vt:$val, i32:$ptr),
2264 (inst 0, $ptr, $val, 0)
2268 defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2269 defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2270 defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
2271 defm : DSWritePat <DS_WRITE_B64, i64, local_store>;
2273 multiclass DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> {
2275 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), vt:$value),
2276 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2280 (frag i32:$ptr, vt:$val),
2281 (inst 0, $ptr, $val, 0)
2285 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2287 // We need to use something for the data0, so we set a register to
2288 // -1. For the non-rtn variants, the manual says it does
2289 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2290 // will always do the increment so I'm assuming it's the same.
2292 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
2293 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
2294 // easier since there is no v_mov_b64.
2295 multiclass DSAtomicIncRetPat<DS inst, ValueType vt,
2296 Instruction LoadImm, PatFrag frag> {
2298 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), (vt 1)),
2299 (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset))
2303 (frag i32:$ptr, (vt 1)),
2304 (inst 0, $ptr, (LoadImm (vt -1)), 0)
2308 multiclass DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> {
2310 (frag (add i32:$ptr, (i32 IMM16bit:$offset)), vt:$cmp, vt:$swap),
2311 (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset))
2315 (frag i32:$ptr, vt:$cmp, vt:$swap),
2316 (inst 0, $ptr, $cmp, $swap, 0)
2322 defm : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2323 S_MOV_B32, atomic_load_add_local>;
2324 defm : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2325 S_MOV_B32, atomic_load_sub_local>;
2327 defm : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, atomic_swap_local>;
2328 defm : DSAtomicRetPat<DS_ADD_RTN_U32, i32, atomic_load_add_local>;
2329 defm : DSAtomicRetPat<DS_SUB_RTN_U32, i32, atomic_load_sub_local>;
2330 defm : DSAtomicRetPat<DS_AND_RTN_B32, i32, atomic_load_and_local>;
2331 defm : DSAtomicRetPat<DS_OR_RTN_B32, i32, atomic_load_or_local>;
2332 defm : DSAtomicRetPat<DS_XOR_RTN_B32, i32, atomic_load_xor_local>;
2333 defm : DSAtomicRetPat<DS_MIN_RTN_I32, i32, atomic_load_min_local>;
2334 defm : DSAtomicRetPat<DS_MAX_RTN_I32, i32, atomic_load_max_local>;
2335 defm : DSAtomicRetPat<DS_MIN_RTN_U32, i32, atomic_load_umin_local>;
2336 defm : DSAtomicRetPat<DS_MAX_RTN_U32, i32, atomic_load_umax_local>;
2338 defm : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, atomic_cmp_swap_32_local>;
2341 defm : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2342 S_MOV_B64, atomic_load_add_local>;
2343 defm : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2344 S_MOV_B64, atomic_load_sub_local>;
2346 defm : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, atomic_swap_local>;
2347 defm : DSAtomicRetPat<DS_ADD_RTN_U64, i64, atomic_load_add_local>;
2348 defm : DSAtomicRetPat<DS_SUB_RTN_U64, i64, atomic_load_sub_local>;
2349 defm : DSAtomicRetPat<DS_AND_RTN_B64, i64, atomic_load_and_local>;
2350 defm : DSAtomicRetPat<DS_OR_RTN_B64, i64, atomic_load_or_local>;
2351 defm : DSAtomicRetPat<DS_XOR_RTN_B64, i64, atomic_load_xor_local>;
2352 defm : DSAtomicRetPat<DS_MIN_RTN_I64, i64, atomic_load_min_local>;
2353 defm : DSAtomicRetPat<DS_MAX_RTN_I64, i64, atomic_load_max_local>;
2354 defm : DSAtomicRetPat<DS_MIN_RTN_U64, i64, atomic_load_umin_local>;
2355 defm : DSAtomicRetPat<DS_MAX_RTN_U64, i64, atomic_load_umax_local>;
2357 defm : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
2360 //===----------------------------------------------------------------------===//
2362 //===----------------------------------------------------------------------===//
2364 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2365 PatFrag global_ld, PatFrag constant_ld> {
2367 (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))),
2368 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2372 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))),
2373 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2377 (vt (global_ld i64:$ptr)),
2378 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2382 (vt (global_ld (add i64:$ptr, i64:$offset))),
2383 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2387 (vt (constant_ld (add i64:$ptr, i64:$offset))),
2388 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0)
2392 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32,
2393 sextloadi8_global, sextloadi8_constant>;
2394 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32,
2395 az_extloadi8_global, az_extloadi8_constant>;
2396 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32,
2397 sextloadi16_global, sextloadi16_constant>;
2398 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32,
2399 az_extloadi16_global, az_extloadi16_constant>;
2400 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32,
2401 global_load, constant_load>;
2402 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2403 global_load, constant_load>;
2404 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64,
2405 az_extloadi32_global, az_extloadi32_constant>;
2406 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32,
2407 global_load, constant_load>;
2408 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32,
2409 global_load, constant_load>;
2411 multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> {
2414 (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)),
2415 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset))
2419 (st vt:$value, (add i64:$ptr, IMM12bit:$offset)),
2420 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset))
2424 (st vt:$value, i64:$ptr),
2425 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
2429 (st vt:$value, (add i64:$ptr, i64:$offset)),
2430 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
2434 defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>;
2435 defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>;
2436 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>;
2437 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
2438 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
2439 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
2441 // BUFFER_LOAD_DWORD*, addr64=0
2442 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2446 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2447 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2449 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2450 (as_i1imm $slc), (as_i1imm $tfe))
2454 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2455 imm, 1, 0, imm:$glc, imm:$slc,
2457 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2462 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2463 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2465 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2466 (as_i1imm $slc), (as_i1imm $tfe))
2470 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2471 imm, 1, 1, imm:$glc, imm:$slc,
2473 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2478 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2479 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2480 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2481 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2482 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2483 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2485 //===----------------------------------------------------------------------===//
2487 //===----------------------------------------------------------------------===//
2489 // TBUFFER_STORE_FORMAT_*, addr64=0
2490 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2491 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2492 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2493 imm:$nfmt, imm:$offen, imm:$idxen,
2494 imm:$glc, imm:$slc, imm:$tfe),
2496 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2497 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2498 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2501 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2502 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2503 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2504 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2506 let SubtargetPredicate = isCI in {
2508 // Sea island new arithmetic instructinos
2509 let neverHasSideEffects = 1 in {
2510 defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64",
2511 [(set f64:$dst, (ftrunc f64:$src0))]
2513 defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64",
2514 [(set f64:$dst, (fceil f64:$src0))]
2516 defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64",
2517 [(set f64:$dst, (ffloor f64:$src0))]
2519 defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64",
2520 [(set f64:$dst, (frint f64:$src0))]
2523 defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
2524 defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
2525 defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
2526 def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>;
2528 // XXX - Does this set VCC?
2529 def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>;
2530 } // End neverHasSideEffects = 1
2532 // Remaining instructions:
2534 // S_CBRANCH_CDBGUSER
2535 // S_CBRANCH_CDBGSYS
2536 // S_CBRANCH_CDBGSYS_OR_USER
2537 // S_CBRANCH_CDBGSYS_AND_USER
2542 // DS_GWS_SEMA_RELEASE_ALL
2544 // DS_CNDXCHG32_RTN_B64
2547 // DS_CONDXCHG32_RTN_B128
2550 // BUFFER_LOAD_DWORDX3
2551 // BUFFER_STORE_DWORDX3
2556 /********** ====================== **********/
2557 /********** Indirect adressing **********/
2558 /********** ====================== **********/
2560 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2562 // 1. Extract with offset
2564 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2565 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2568 // 2. Extract without offset
2570 (vector_extract vt:$vec, i32:$idx),
2571 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2574 // 3. Insert with offset
2576 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2577 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2580 // 4. Insert without offset
2582 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2583 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2587 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2588 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2589 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2590 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2592 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2593 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2594 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2595 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2597 //===----------------------------------------------------------------------===//
2598 // Conversion Patterns
2599 //===----------------------------------------------------------------------===//
2601 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2602 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2604 // TODO: Match 64-bit BFE. SI has a 64-bit BFE, but it's scalar only so it
2605 // might not be worth the effort, and will need to expand to shifts when
2606 // fixing SGPR copies.
2608 // Handle sext_inreg in i64
2610 (i64 (sext_inreg i64:$src, i1)),
2611 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2612 (S_BFE_I32 (EXTRACT_SUBREG i64:$src, sub0), 65536), sub0), // 0 | 1 << 16
2613 (S_MOV_B32 -1), sub1)
2617 (i64 (sext_inreg i64:$src, i8)),
2618 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2619 (S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2620 (S_MOV_B32 -1), sub1)
2624 (i64 (sext_inreg i64:$src, i16)),
2625 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2626 (S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
2627 (S_MOV_B32 -1), sub1)
2630 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
2631 (i64 (ext i32:$src)),
2632 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2633 (S_MOV_B32 0), sub1)
2636 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
2637 (i64 (ext i1:$src)),
2639 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2640 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0),
2641 (S_MOV_B32 0), sub1)
2645 def : ZExt_i64_i32_Pat<zext>;
2646 def : ZExt_i64_i32_Pat<anyext>;
2647 def : ZExt_i64_i1_Pat<zext>;
2648 def : ZExt_i64_i1_Pat<anyext>;
2651 (i64 (sext i32:$src)),
2653 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2654 (S_ASHR_I32 $src, 31), sub1)
2658 (i64 (sext i1:$src)),
2661 (i64 (IMPLICIT_DEF)),
2662 (V_CNDMASK_B32_e64 0, -1, $src), sub0),
2663 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
2667 (f32 (sint_to_fp i1:$src)),
2668 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
2672 (f32 (uint_to_fp i1:$src)),
2673 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
2677 (f64 (sint_to_fp i1:$src)),
2678 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
2682 (f64 (uint_to_fp i1:$src)),
2683 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
2686 //===----------------------------------------------------------------------===//
2687 // Miscellaneous Patterns
2688 //===----------------------------------------------------------------------===//
2691 (i32 (trunc i64:$a)),
2692 (EXTRACT_SUBREG $a, sub0)
2696 (i1 (trunc i32:$a)),
2697 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1)
2700 // V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector
2701 // case, the sgpr-copies pass will fix this to use the vector version.
2703 (i32 (addc i32:$src0, i32:$src1)),
2704 (S_ADD_I32 $src0, $src1)
2708 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
2709 (V_BCNT_U32_B32_e32 $popcnt, $val)
2713 (i64 (ctpop i64:$src)),
2714 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2715 (S_BCNT1_I32_B64 $src), sub0),
2716 (S_MOV_B32 0), sub1)
2719 //============================================================================//
2720 // Miscellaneous Optimization Patterns
2721 //============================================================================//
2723 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
2725 } // End isSI predicate