Add target hook for whether it is profitable to reduce load widths
[oota-llvm.git] / lib / Target / R600 / AMDGPUISelLowering.cpp
2014-12-12 Matt ArsenaultAdd target hook for whether it is profitable to reduce...
2014-12-07 Marek OlsakR600/SI: Update instruction conversions for VI
2014-11-26 Matt ArsenaultR600/SI: Use ZeroOrNegativeOneBooleanContent
2014-11-23 Matt ArsenaultR600: Fix assert on copy of an i1 on pre-SI
2014-11-15 Matt ArsenaultR600: Permute operands when selecting legacy min/max
2014-11-15 Tom StellardR600: Fix 64-bit integer division
2014-11-15 Tom StellardR600: Factor i64 UDIVREM lowering into its own fuction
2014-11-14 Matt ArsenaultR600/SI: Combine min3/max3 instructions
2014-11-14 Matt ArsenaultR600/SI: Match integer min / max instructions
2014-11-13 Matt ArsenaultR600/SI: Fix fmin_legacy / fmax_legacy matching for SI
2014-11-13 Aditya NandakumarWe can get the TLOF from the TargetMachine - so constru...
2014-11-13 Matt ArsenaultR600: Error on initializer for LDS.
2014-11-13 Aditya NandakumarThis patch changes the ownership of TLOF from TargetLow...
2014-10-21 Matt ArsenaultAdd minnum / maxnum codegen
2014-10-21 Matt ArsenaultR600/SI: Add missing parameter to div_fmas intrinsic
2014-10-16 Matt ArsenaultR600: Fix nonsensical implementation of computeKnownBit...
2014-10-16 Matt ArsenaultR600: Remove dead function
2014-10-15 Matt ArsenaultR600: Remove unnecessary part of computeKnownBitsForTar...
2014-10-15 Matt ArsenaultMove variable down to use
2014-10-15 Matt ArsenaultR600: Fix miscompiles when BFE has multiple uses
2014-10-15 Matt ArsenaultR600: Use existing variable
2014-10-15 Matt ArsenaultR600: Remove outdated comment
2014-10-03 Matt ArsenaultR600/SI: Custom lower f64 -> i64 conversions
2014-10-03 Matt ArsenaultR600: Custom lower [s|u]int_to_fp for i64 -> f64
2014-10-03 Matt ArsenaultR600/SI: Fix ftrunc f64 conformance failures.
2014-09-26 Matt ArsenaultR600/SI: Add a note about the order of the operands...
2014-09-22 Tom StellardR600: Don't set BypassSlowDiv for 64-bit division
2014-09-22 Tom StellardR600/SI: Use ISD::MUL instead of ISD::UMULO when loweri...
2014-09-19 Matt ArsenaultR600: Better fix for bug 20982
2014-09-18 Matt ArsenaultR600: Bug 20982 - Avoid undefined left shift of negativ...
2014-09-10 Matt ArsenaultR600: Custom lower frem
2014-08-29 Matt ArsenaultR600/SI: Use mad for fsub + fmul
2014-08-21 Sanjay Patelname change: isPow2DivCheap -> isPow2SDivCheap
2014-08-15 Matt ArsenaultR600/SI: Use source modifiers for f64 fneg
2014-08-15 Matt ArsenaultR600/SI: Use source modifier for f64 fabs
2014-08-15 Matt ArsenaultR600/SI: Add intrinsic for ldexp
2014-08-12 Jan VeselyR600: Use optimized 24bit path in udivrem
2014-08-12 Jan VeselyR600: Remove unused code.
2014-08-12 Jan VeselyR600: Use i24 optimized path for SREM
2014-08-09 Matt ArsenaultR600: Disable FP exceptions.
2014-08-05 Tom StellardR600/SI: Avoid generating REGISTER_LOAD instructions.
2014-08-04 Eric ChristopherRemove the TargetMachine forwards for TargetSubtargetIn...
2014-08-04 Matt ArsenaultUse the known address space constant rather than checki...
2014-08-01 Tom StellardRevert "R600: Move code for generating REGISTER_LOAD...
2014-08-01 Tom StellardR600: Move code for generating REGISTER_LOAD into R600I...
2014-07-31 Louis GerbargMake sure no loads resulting from load->switch DAGCombi...
2014-07-25 Chandler Carruth[SDAG] Enable the new assert for out-of-range result...
2014-07-24 Matt ArsenaultR600: Add new functions for splitting vector loads...
2014-07-24 Matt ArsenaultR600: Fix LowerSDIV24
2014-07-21 Tom StellardR600/SI: Store constant initializer data in constant...
2014-07-18 Tim NorthoverR600: support fpext/fptrunc operations to and from...
2014-07-18 Tim NorthoverR600: support f16 -> f64 conversion intrinsic.
2014-07-15 Jan VeselyR600: Implement zero undef variants of ctlz/cttz
2014-07-15 Matt ArsenaultR600: Add dag combine for copy of an illegal type.
2014-07-10 Jan VeselyR600: Implement float to long/ulong
2014-07-07 Matt ArsenaultR600: Fix mishandling of load / store chains.
2014-07-02 Tom StellardR600: Add a comment that llvm.AMDGPU.trunc is a legacy...
2014-07-02 Tom StellardR600: Promote i64 loads to v2i32
2014-07-02 Matt ArsenaultR600: Fix crashes when an illegal type load or store...
2014-06-30 Matt ArsenaultR600: Move mul combine to separate function
2014-06-27 Matt ArsenaultR600: Move load/store ReplaceNodeResults to common...
2014-06-26 Aaron BallmanSilencing a warning about isZExtFree hiding an inherite...
2014-06-26 Matt ArsenaultR600: Fix vector FMA
2014-06-24 Tom StellardR600: Promote i64 stores to v2i32
2014-06-24 Matt ArsenaultR600: Fix inconsistency in rsq instructions.
2014-06-24 Matt ArsenaultR600: Remove DIV_INF
2014-06-23 Matt ArsenaultR600/SI: Fix div_scale intrinsic.
2014-06-23 Matt ArsenaultR600: Remove AMDILISelLowering
2014-06-23 Matt ArsenaultR600: Select is not expensive.
2014-06-23 Matt ArsenaultR600: Move add/sub with overflow out of AMDILISelLowering
2014-06-23 Matt ArsenaultR600: Move more out of AMDILISelLowering
2014-06-23 Matt ArsenaultR600/SI: Handle i64 sub.
2014-06-23 Matt ArsenaultR600: Rename AMDIL file
2014-06-22 Jan VeselyR600: Use LowerSDIVREM for i64 node replace
2014-06-22 Jan VeselyR600: Implement custom SDIVREM.
2014-06-20 Tom StellardR600/SI: Add a pattern for f32 ftrunc
2014-06-20 Tom StellardR600: Expand vector flog2
2014-06-20 Tom StellardR600: Expand vector fexp2
2014-06-19 Matt ArsenaultR600/SI: Add intrinsics for various math instructions.
2014-06-18 Matt ArsenaultUse stdint macros for specifying size of constants
2014-06-18 Matt ArsenaultR600: Handle fnearbyint
2014-06-18 Matt ArsenaultUse LL suffix for literal that should be 64-bits.
2014-06-18 Jan VeselyR600: Expand vector fceil
2014-06-18 Matt ArsenaultWork around ridiculous warning.
2014-06-18 Matt ArsenaultR600/SI: Add intrinsics for brev instructions
2014-06-18 Matt ArsenaultR600: Implement f64 ftrunc, ffloor and fceil.
2014-06-18 Matt ArsenaultR600: Custom lower f64 frint for pre-CI
2014-06-17 Matt ArsenaultR600/SI: Match ctlz_zero_undef
2014-06-17 Tom StellardR600: Use LDS and vectors for private memory
2014-06-17 Tom StellardSelectionDAG: Expand i64 = FP_TO_SINT i32
2014-06-15 Matt ArsenaultFix copy paste error
2014-06-15 Matt ArsenaultR600: Remove a few more things from AMDILISelLowering
2014-06-15 Matt ArsenaultR600: Fix assert on vector sdiv
2014-06-15 Matt ArsenaultR600: Move / cleanup more leftover AMDIL stuff.
2014-06-15 Matt ArsenaultR600: Move division custom lowering out of AMDILISelLow...
2014-06-15 Matt ArsenaultR600: Report that integer division is expensive.
2014-06-14 Matt ArsenaultR600: Fix asserts related to constant initializers
2014-06-14 Matt ArsenaultR600: Use address space enum instead of value
2014-06-13 Matt ArsenaultR600: Cleanup some old AMDIL stuff.
2014-06-13 Matt ArsenaultR600/SI: Fix selection error on i64 rotl / rotr.
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