1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDILIntrinsicInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 // Find a larger type to do a load / store of a vector with.
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
91 return EVT::getIntegerVT(Ctx, StoreSize);
93 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
97 // Type for a vector that will be loaded to.
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
101 return EVT::getIntegerVT(Ctx, 32);
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
107 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
109 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
111 // Initialize target lowering borrowed from AMDIL
114 // We need to custom lower some of the intrinsics
115 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
117 // Library functions. These default to Expand, but we have instructions
119 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
120 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
121 setOperationAction(ISD::FPOW, MVT::f32, Legal);
122 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
123 setOperationAction(ISD::FABS, MVT::f32, Legal);
124 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
125 setOperationAction(ISD::FRINT, MVT::f32, Legal);
126 setOperationAction(ISD::FROUND, MVT::f32, Legal);
127 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
129 // The hardware supports 32-bit ROTR, but not ROTL.
130 setOperationAction(ISD::ROTL, MVT::i32, Expand);
131 setOperationAction(ISD::ROTL, MVT::i64, Expand);
132 setOperationAction(ISD::ROTR, MVT::i64, Expand);
134 // Lower floating point store/load to integer store/load to reduce the number
135 // of patterns in tablegen.
136 setOperationAction(ISD::STORE, MVT::f32, Promote);
137 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
139 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
140 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
142 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
143 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
145 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
146 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
148 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
149 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
151 setOperationAction(ISD::STORE, MVT::f64, Promote);
152 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
154 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
155 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
157 // Custom lowering of vector stores is required for local address space
159 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
160 // XXX: Native v2i32 local address space stores are possible, but not
161 // currently implemented.
162 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
164 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
165 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
166 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
168 // XXX: This can be change to Custom, once ExpandVectorStores can
169 // handle 64-bit stores.
170 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
172 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
173 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
174 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
175 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
176 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
179 setOperationAction(ISD::LOAD, MVT::f32, Promote);
180 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
182 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
183 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
185 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
186 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
188 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
189 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
191 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
192 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
194 setOperationAction(ISD::LOAD, MVT::f64, Promote);
195 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
197 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
198 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
200 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
201 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
202 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
203 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
204 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
205 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
206 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
207 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
208 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
209 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
211 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
212 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
213 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
214 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
215 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
216 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
217 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
218 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
220 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
221 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
224 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
226 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
228 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
230 setOperationAction(ISD::MUL, MVT::i64, Expand);
231 setOperationAction(ISD::SUB, MVT::i64, Expand);
233 setOperationAction(ISD::UDIV, MVT::i32, Expand);
234 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
235 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
236 setOperationAction(ISD::UREM, MVT::i32, Expand);
238 if (!Subtarget->hasBFI()) {
239 // fcopysign can be done in a single instruction with BFI.
240 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
241 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
244 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
245 for (MVT VT : ScalarIntVTs) {
246 // GPU does not have divrem function for signed or unsigned.
247 setOperationAction(ISD::SDIVREM, VT, Expand);
249 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
250 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
251 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
253 setOperationAction(ISD::BSWAP, VT, Expand);
254 setOperationAction(ISD::CTTZ, VT, Expand);
255 setOperationAction(ISD::CTLZ, VT, Expand);
258 if (!Subtarget->hasBCNT(32))
259 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
261 if (!Subtarget->hasBCNT(64))
262 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
265 static const MVT::SimpleValueType VectorIntTypes[] = {
266 MVT::v2i32, MVT::v4i32
269 for (MVT VT : VectorIntTypes) {
270 // Expand the following operations for the current type by default.
271 setOperationAction(ISD::ADD, VT, Expand);
272 setOperationAction(ISD::AND, VT, Expand);
273 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
274 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
275 setOperationAction(ISD::MUL, VT, Expand);
276 setOperationAction(ISD::OR, VT, Expand);
277 setOperationAction(ISD::SHL, VT, Expand);
278 setOperationAction(ISD::SRA, VT, Expand);
279 setOperationAction(ISD::SRL, VT, Expand);
280 setOperationAction(ISD::ROTL, VT, Expand);
281 setOperationAction(ISD::ROTR, VT, Expand);
282 setOperationAction(ISD::SUB, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
285 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
286 // TODO: Implement custom UREM / SREM routines.
287 setOperationAction(ISD::SREM, VT, Expand);
288 setOperationAction(ISD::UREM, VT, Expand);
289 setOperationAction(ISD::SDIVREM, VT, Expand);
290 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
291 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
292 setOperationAction(ISD::SELECT, VT, Expand);
293 setOperationAction(ISD::VSELECT, VT, Expand);
294 setOperationAction(ISD::XOR, VT, Expand);
295 setOperationAction(ISD::BSWAP, VT, Expand);
296 setOperationAction(ISD::CTPOP, VT, Expand);
297 setOperationAction(ISD::CTTZ, VT, Expand);
298 setOperationAction(ISD::CTLZ, VT, Expand);
301 static const MVT::SimpleValueType FloatVectorTypes[] = {
302 MVT::v2f32, MVT::v4f32
305 for (MVT VT : FloatVectorTypes) {
306 setOperationAction(ISD::FABS, VT, Expand);
307 setOperationAction(ISD::FADD, VT, Expand);
308 setOperationAction(ISD::FCOS, VT, Expand);
309 setOperationAction(ISD::FDIV, VT, Expand);
310 setOperationAction(ISD::FPOW, VT, Expand);
311 setOperationAction(ISD::FFLOOR, VT, Expand);
312 setOperationAction(ISD::FTRUNC, VT, Expand);
313 setOperationAction(ISD::FMUL, VT, Expand);
314 setOperationAction(ISD::FRINT, VT, Expand);
315 setOperationAction(ISD::FSQRT, VT, Expand);
316 setOperationAction(ISD::FSIN, VT, Expand);
317 setOperationAction(ISD::FSUB, VT, Expand);
318 setOperationAction(ISD::FNEG, VT, Expand);
319 setOperationAction(ISD::SELECT, VT, Expand);
320 setOperationAction(ISD::VSELECT, VT, Expand);
321 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
324 setTargetDAGCombine(ISD::MUL);
325 setTargetDAGCombine(ISD::SELECT_CC);
327 setSchedulingPreference(Sched::RegPressure);
328 setJumpIsExpensive(true);
330 // FIXME: Need to really handle these.
331 MaxStoresPerMemcpy = 4096;
332 MaxStoresPerMemmove = 4096;
333 MaxStoresPerMemset = 4096;
336 //===----------------------------------------------------------------------===//
337 // Target Information
338 //===----------------------------------------------------------------------===//
340 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
344 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
346 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
349 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
350 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
352 return ((LScalarSize <= CastScalarSize) ||
353 (CastScalarSize >= 32) ||
357 //===---------------------------------------------------------------------===//
359 //===---------------------------------------------------------------------===//
361 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
362 assert(VT.isFloatingPoint());
363 return VT == MVT::f32;
366 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
367 assert(VT.isFloatingPoint());
368 return VT == MVT::f32;
371 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
372 // Truncate is just accessing a subregister.
373 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
376 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
377 // Truncate is just accessing a subregister.
378 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
379 (Dest->getPrimitiveSizeInBits() % 32 == 0);
382 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
383 const DataLayout *DL = getDataLayout();
384 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
385 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
387 return SrcSize == 32 && DestSize == 64;
390 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
391 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
392 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
393 // this will enable reducing 64-bit operations the 32-bit, which is always
395 return Src == MVT::i32 && Dest == MVT::i64;
398 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
399 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
400 // limited number of native 64-bit operations. Shrinking an operation to fit
401 // in a single 32-bit register should always be helpful. As currently used,
402 // this is much less general than the name suggests, and is only used in
403 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
404 // not profitable, and may actually be harmful.
405 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
408 //===---------------------------------------------------------------------===//
409 // TargetLowering Callbacks
410 //===---------------------------------------------------------------------===//
412 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
413 const SmallVectorImpl<ISD::InputArg> &Ins) const {
415 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
418 SDValue AMDGPUTargetLowering::LowerReturn(
420 CallingConv::ID CallConv,
422 const SmallVectorImpl<ISD::OutputArg> &Outs,
423 const SmallVectorImpl<SDValue> &OutVals,
424 SDLoc DL, SelectionDAG &DAG) const {
425 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
428 //===---------------------------------------------------------------------===//
429 // Target specific lowering
430 //===---------------------------------------------------------------------===//
432 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
433 SmallVectorImpl<SDValue> &InVals) const {
434 SDValue Callee = CLI.Callee;
435 SelectionDAG &DAG = CLI.DAG;
437 const Function &Fn = *DAG.getMachineFunction().getFunction();
439 StringRef FuncName("<unknown>");
441 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
442 FuncName = G->getSymbol();
443 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
444 FuncName = G->getGlobal()->getName();
446 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
447 DAG.getContext()->diagnose(NoCalls);
451 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
453 switch (Op.getOpcode()) {
455 Op.getNode()->dump();
456 llvm_unreachable("Custom lowering code for this"
457 "instruction is not implemented yet!");
459 // AMDIL DAG lowering
460 case ISD::SDIV: return LowerSDIV(Op, DAG);
461 case ISD::SREM: return LowerSREM(Op, DAG);
462 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
463 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
464 // AMDGPU DAG lowering
465 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
466 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
467 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
468 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
469 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
470 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
475 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
476 SmallVectorImpl<SDValue> &Results,
477 SelectionDAG &DAG) const {
478 switch (N->getOpcode()) {
479 case ISD::SIGN_EXTEND_INREG:
480 // Different parts of legalization seem to interpret which type of
481 // sign_extend_inreg is the one to check for custom lowering. The extended
482 // from type is what really matters, but some places check for custom
483 // lowering of the result type. This results in trying to use
484 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
485 // nothing here and let the illegal result integer be handled normally.
488 SDValue Op = SDValue(N, 0);
490 EVT VT = Op.getValueType();
491 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
492 N->getOperand(0), N->getOperand(1));
493 Results.push_back(UDIVREM);
497 SDValue Op = SDValue(N, 0);
499 EVT VT = Op.getValueType();
500 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
501 N->getOperand(0), N->getOperand(1));
502 Results.push_back(UDIVREM.getValue(1));
506 SDValue Op = SDValue(N, 0);
508 EVT VT = Op.getValueType();
509 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
511 SDValue one = DAG.getConstant(1, HalfVT);
512 SDValue zero = DAG.getConstant(0, HalfVT);
515 SDValue LHS = N->getOperand(0);
516 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
517 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
519 SDValue RHS = N->getOperand(1);
520 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
521 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
523 // Get Speculative values
524 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
525 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
527 SDValue REM_Hi = zero;
528 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
530 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
531 SDValue DIV_Lo = zero;
533 const unsigned halfBitWidth = HalfVT.getSizeInBits();
535 for (unsigned i = 0; i < halfBitWidth; ++i) {
536 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
537 // Get Value of high bit
539 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
540 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
542 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
543 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
546 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
547 DAG.getConstant(halfBitWidth - 1, HalfVT));
548 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
549 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
551 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
552 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
555 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
557 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
558 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
560 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
564 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
566 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
567 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
568 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
571 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
572 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
573 Results.push_back(DIV);
574 Results.push_back(REM);
582 // FIXME: This implements accesses to initialized globals in the constant
583 // address space by copying them to private and accessing that. It does not
584 // properly handle illegal types or vectors. The private vector loads are not
585 // scalarized, and the illegal scalars hit an assertion. This technique will not
586 // work well with large initializers, and this should eventually be
587 // removed. Initialized globals should be placed into a data section that the
588 // runtime will load into a buffer before the kernel is executed. Uses of the
589 // global need to be replaced with a pointer loaded from an implicit kernel
590 // argument into this buffer holding the copy of the data, which will remove the
591 // need for any of this.
592 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
593 const GlobalValue *GV,
594 const SDValue &InitPtr,
596 SelectionDAG &DAG) const {
597 const DataLayout *TD = getTargetMachine().getDataLayout();
599 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
600 EVT VT = EVT::getEVT(CI->getType());
601 PointerType *PtrTy = PointerType::get(CI->getType(), 0);
602 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
603 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
604 TD->getPrefTypeAlignment(CI->getType()));
607 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
608 EVT VT = EVT::getEVT(CFP->getType());
609 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
610 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
611 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
612 TD->getPrefTypeAlignment(CFP->getType()));
615 Type *InitTy = Init->getType();
616 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
617 const StructLayout *SL = TD->getStructLayout(ST);
619 EVT PtrVT = InitPtr.getValueType();
620 SmallVector<SDValue, 8> Chains;
622 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
623 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
624 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
626 Constant *Elt = Init->getAggregateElement(I);
627 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
630 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
633 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
634 EVT PtrVT = InitPtr.getValueType();
636 unsigned NumElements;
637 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
638 NumElements = AT->getNumElements();
639 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
640 NumElements = VT->getNumElements();
642 llvm_unreachable("Unexpected type");
644 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
645 SmallVector<SDValue, 8> Chains;
646 for (unsigned i = 0; i < NumElements; ++i) {
647 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
648 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
650 Constant *Elt = Init->getAggregateElement(i);
651 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
654 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
658 llvm_unreachable("Unhandled constant initializer");
661 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
663 SelectionDAG &DAG) const {
665 const DataLayout *TD = getTargetMachine().getDataLayout();
666 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
667 const GlobalValue *GV = G->getGlobal();
669 switch (G->getAddressSpace()) {
670 default: llvm_unreachable("Global Address lowering not implemented for this "
672 case AMDGPUAS::LOCAL_ADDRESS: {
673 // XXX: What does the value of G->getOffset() mean?
674 assert(G->getOffset() == 0 &&
675 "Do not know what to do with an non-zero offset");
678 if (MFI->LocalMemoryObjects.count(GV) == 0) {
679 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
680 Offset = MFI->LDSSize;
681 MFI->LocalMemoryObjects[GV] = Offset;
682 // XXX: Account for alignment?
683 MFI->LDSSize += Size;
685 Offset = MFI->LocalMemoryObjects[GV];
688 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
690 case AMDGPUAS::CONSTANT_ADDRESS: {
691 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
692 Type *EltType = GV->getType()->getElementType();
693 unsigned Size = TD->getTypeAllocSize(EltType);
694 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
696 const GlobalVariable *Var = cast<GlobalVariable>(GV);
697 const Constant *Init = Var->getInitializer();
698 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
699 SDValue InitPtr = DAG.getFrameIndex(FI,
700 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
701 SmallVector<SDNode*, 8> WorkList;
703 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
704 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
705 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
707 WorkList.push_back(*I);
709 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
710 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
711 E = WorkList.end(); I != E; ++I) {
712 SmallVector<SDValue, 8> Ops;
713 Ops.push_back(Chain);
714 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
715 Ops.push_back((*I)->getOperand(i));
717 DAG.UpdateNodeOperands(*I, Ops);
719 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op),
720 getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
725 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
726 SelectionDAG &DAG) const {
727 SmallVector<SDValue, 8> Args;
728 SDValue A = Op.getOperand(0);
729 SDValue B = Op.getOperand(1);
731 DAG.ExtractVectorElements(A, Args);
732 DAG.ExtractVectorElements(B, Args);
734 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
737 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
738 SelectionDAG &DAG) const {
740 SmallVector<SDValue, 8> Args;
741 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
742 EVT VT = Op.getValueType();
743 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
744 VT.getVectorNumElements());
746 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
749 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
750 SelectionDAG &DAG) const {
752 MachineFunction &MF = DAG.getMachineFunction();
753 const AMDGPUFrameLowering *TFL =
754 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
756 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
758 unsigned FrameIndex = FIN->getIndex();
759 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
760 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
764 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
765 SelectionDAG &DAG) const {
766 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
768 EVT VT = Op.getValueType();
770 switch (IntrinsicID) {
772 case AMDGPUIntrinsic::AMDGPU_abs:
773 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
774 return LowerIntrinsicIABS(Op, DAG);
775 case AMDGPUIntrinsic::AMDGPU_lrp:
776 return LowerIntrinsicLRP(Op, DAG);
777 case AMDGPUIntrinsic::AMDGPU_fract:
778 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
779 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
781 case AMDGPUIntrinsic::AMDGPU_clamp:
782 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
783 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
784 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
786 case AMDGPUIntrinsic::AMDGPU_imax:
787 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
789 case AMDGPUIntrinsic::AMDGPU_umax:
790 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
792 case AMDGPUIntrinsic::AMDGPU_imin:
793 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
795 case AMDGPUIntrinsic::AMDGPU_umin:
796 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
799 case AMDGPUIntrinsic::AMDGPU_umul24:
800 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
801 Op.getOperand(1), Op.getOperand(2));
803 case AMDGPUIntrinsic::AMDGPU_imul24:
804 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
805 Op.getOperand(1), Op.getOperand(2));
807 case AMDGPUIntrinsic::AMDGPU_umad24:
808 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
809 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
811 case AMDGPUIntrinsic::AMDGPU_imad24:
812 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
813 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
815 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
816 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
818 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
819 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
821 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
822 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
824 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
825 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
827 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
828 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
833 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
834 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
839 case AMDGPUIntrinsic::AMDGPU_bfi:
840 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
845 case AMDGPUIntrinsic::AMDGPU_bfm:
846 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
850 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
851 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
853 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
854 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
858 ///IABS(a) = SMAX(sub(0, a), a)
859 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
860 SelectionDAG &DAG) const {
862 EVT VT = Op.getValueType();
863 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
866 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
869 /// Linear Interpolation
870 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
871 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
872 SelectionDAG &DAG) const {
874 EVT VT = Op.getValueType();
875 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
876 DAG.getConstantFP(1.0f, MVT::f32),
878 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
880 return DAG.getNode(ISD::FADD, DL, VT,
881 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
885 /// \brief Generate Min/Max node
886 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
887 SelectionDAG &DAG) const {
889 EVT VT = N->getValueType(0);
891 SDValue LHS = N->getOperand(0);
892 SDValue RHS = N->getOperand(1);
893 SDValue True = N->getOperand(2);
894 SDValue False = N->getOperand(3);
895 SDValue CC = N->getOperand(4);
897 if (VT != MVT::f32 ||
898 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
902 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
916 llvm_unreachable("Operation should already be optimised!");
923 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
924 return DAG.getNode(Opc, DL, VT, LHS, RHS);
932 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
933 return DAG.getNode(Opc, DL, VT, LHS, RHS);
935 case ISD::SETCC_INVALID:
936 llvm_unreachable("Invalid setcc condcode!");
941 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
942 SelectionDAG &DAG) const {
943 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
944 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
945 EVT EltVT = Op.getValueType().getVectorElementType();
946 EVT PtrVT = Load->getBasePtr().getValueType();
947 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
948 SmallVector<SDValue, 8> Loads;
951 for (unsigned i = 0, e = NumElts; i != e; ++i) {
952 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
953 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
954 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
955 Load->getChain(), Ptr,
956 MachinePointerInfo(Load->getMemOperand()->getValue()),
957 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
958 Load->getAlignment()));
960 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
963 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
964 SelectionDAG &DAG) const {
965 StoreSDNode *Store = cast<StoreSDNode>(Op);
966 EVT MemVT = Store->getMemoryVT();
967 unsigned MemBits = MemVT.getSizeInBits();
969 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
970 // truncating store into an i32 store.
971 // XXX: We could also handle optimize other vector bitwidths.
972 if (!MemVT.isVector() || MemBits > 32) {
977 SDValue Value = Store->getValue();
978 EVT VT = Value.getValueType();
979 EVT ElemVT = VT.getVectorElementType();
980 SDValue Ptr = Store->getBasePtr();
981 EVT MemEltVT = MemVT.getVectorElementType();
982 unsigned MemEltBits = MemEltVT.getSizeInBits();
983 unsigned MemNumElements = MemVT.getVectorNumElements();
984 unsigned PackedSize = MemVT.getStoreSizeInBits();
985 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
987 assert(Value.getValueType().getScalarSizeInBits() >= 32);
990 for (unsigned i = 0; i < MemNumElements; ++i) {
991 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
992 DAG.getConstant(i, MVT::i32));
993 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
994 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
996 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
997 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1002 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1006 if (PackedSize < 32) {
1007 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1008 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1009 Store->getMemOperand()->getPointerInfo(),
1011 Store->isNonTemporal(), Store->isVolatile(),
1012 Store->getAlignment());
1015 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1016 Store->getMemOperand()->getPointerInfo(),
1017 Store->isVolatile(), Store->isNonTemporal(),
1018 Store->getAlignment());
1021 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1022 SelectionDAG &DAG) const {
1023 StoreSDNode *Store = cast<StoreSDNode>(Op);
1024 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1025 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1026 EVT PtrVT = Store->getBasePtr().getValueType();
1027 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1030 SmallVector<SDValue, 8> Chains;
1032 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1033 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1034 Store->getValue(), DAG.getConstant(i, MVT::i32));
1035 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
1036 Store->getBasePtr(),
1037 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
1039 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1040 MachinePointerInfo(Store->getMemOperand()->getValue()),
1041 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
1042 Store->getAlignment()));
1044 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1047 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1049 LoadSDNode *Load = cast<LoadSDNode>(Op);
1050 ISD::LoadExtType ExtType = Load->getExtensionType();
1051 EVT VT = Op.getValueType();
1052 EVT MemVT = Load->getMemoryVT();
1054 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1055 // We can do the extload to 32-bits, and then need to separately extend to
1058 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1062 Load->getMemOperand());
1063 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
1066 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1067 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1068 // FIXME: Copied from PPC
1069 // First, load into 32 bits, then truncate to 1 bit.
1071 SDValue Chain = Load->getChain();
1072 SDValue BasePtr = Load->getBasePtr();
1073 MachineMemOperand *MMO = Load->getMemOperand();
1075 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1076 BasePtr, MVT::i8, MMO);
1077 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1080 // Lower loads constant address space global variable loads
1081 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1082 isa<GlobalVariable>(
1083 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
1085 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
1086 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1087 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1088 DAG.getConstant(2, MVT::i32));
1089 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1090 Load->getChain(), Ptr,
1091 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1094 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1095 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1099 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1100 DAG.getConstant(2, MVT::i32));
1101 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1102 Load->getChain(), Ptr,
1103 DAG.getTargetConstant(0, MVT::i32),
1105 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1107 DAG.getConstant(0x3, MVT::i32));
1108 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1109 DAG.getConstant(3, MVT::i32));
1111 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1113 EVT MemEltVT = MemVT.getScalarType();
1114 if (ExtType == ISD::SEXTLOAD) {
1115 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1116 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1119 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1122 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1124 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1125 if (Result.getNode()) {
1129 StoreSDNode *Store = cast<StoreSDNode>(Op);
1130 SDValue Chain = Store->getChain();
1131 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1132 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1133 Store->getValue().getValueType().isVector()) {
1134 return SplitVectorStore(Op, DAG);
1137 EVT MemVT = Store->getMemoryVT();
1138 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1139 MemVT.bitsLT(MVT::i32)) {
1141 if (Store->getMemoryVT() == MVT::i8) {
1143 } else if (Store->getMemoryVT() == MVT::i16) {
1146 SDValue BasePtr = Store->getBasePtr();
1147 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1148 DAG.getConstant(2, MVT::i32));
1149 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1150 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1152 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1153 DAG.getConstant(0x3, MVT::i32));
1155 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1156 DAG.getConstant(3, MVT::i32));
1158 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1161 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1163 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1164 MaskedValue, ShiftAmt);
1166 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1168 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1169 DAG.getConstant(0xffffffff, MVT::i32));
1170 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1172 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1173 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1174 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1179 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1180 SelectionDAG &DAG) const {
1182 EVT VT = Op.getValueType();
1184 SDValue Num = Op.getOperand(0);
1185 SDValue Den = Op.getOperand(1);
1187 // RCP = URECIP(Den) = 2^32 / Den + e
1188 // e is rounding error.
1189 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1191 // RCP_LO = umulo(RCP, Den) */
1192 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1194 // RCP_HI = mulhu (RCP, Den) */
1195 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1197 // NEG_RCP_LO = -RCP_LO
1198 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1201 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1202 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1205 // Calculate the rounding error from the URECIP instruction
1206 // E = mulhu(ABS_RCP_LO, RCP)
1207 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1209 // RCP_A_E = RCP + E
1210 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1212 // RCP_S_E = RCP - E
1213 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1215 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1216 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1219 // Quotient = mulhu(Tmp0, Num)
1220 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1222 // Num_S_Remainder = Quotient * Den
1223 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1225 // Remainder = Num - Num_S_Remainder
1226 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1228 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1229 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1230 DAG.getConstant(-1, VT),
1231 DAG.getConstant(0, VT),
1233 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1234 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1236 DAG.getConstant(-1, VT),
1237 DAG.getConstant(0, VT),
1239 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1240 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1243 // Calculate Division result:
1245 // Quotient_A_One = Quotient + 1
1246 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1247 DAG.getConstant(1, VT));
1249 // Quotient_S_One = Quotient - 1
1250 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1251 DAG.getConstant(1, VT));
1253 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1254 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1255 Quotient, Quotient_A_One, ISD::SETEQ);
1257 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1258 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1259 Quotient_S_One, Div, ISD::SETEQ);
1261 // Calculate Rem result:
1263 // Remainder_S_Den = Remainder - Den
1264 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1266 // Remainder_A_Den = Remainder + Den
1267 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1269 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1270 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1271 Remainder, Remainder_S_Den, ISD::SETEQ);
1273 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1274 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1275 Remainder_A_Den, Rem, ISD::SETEQ);
1280 return DAG.getMergeValues(Ops, DL);
1283 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1284 SelectionDAG &DAG) const {
1285 SDValue S0 = Op.getOperand(0);
1287 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1290 // f32 uint_to_fp i64
1291 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1292 DAG.getConstant(0, MVT::i32));
1293 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1294 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1295 DAG.getConstant(1, MVT::i32));
1296 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1297 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1298 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1299 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1302 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1304 SelectionDAG &DAG) const {
1305 MVT VT = Op.getSimpleValueType();
1307 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1308 // Shift left by 'Shift' bits.
1309 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1310 // Signed shift Right by 'Shift' bits.
1311 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1314 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1315 SelectionDAG &DAG) const {
1316 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1317 MVT VT = Op.getSimpleValueType();
1318 MVT ScalarVT = VT.getScalarType();
1323 SDValue Src = Op.getOperand(0);
1326 // TODO: Don't scalarize on Evergreen?
1327 unsigned NElts = VT.getVectorNumElements();
1328 SmallVector<SDValue, 8> Args;
1329 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1331 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1332 for (unsigned I = 0; I < NElts; ++I)
1333 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1335 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1338 //===----------------------------------------------------------------------===//
1339 // Custom DAG optimizations
1340 //===----------------------------------------------------------------------===//
1342 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1343 APInt KnownZero, KnownOne;
1344 EVT VT = Op.getValueType();
1345 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1347 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1350 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1351 EVT VT = Op.getValueType();
1353 // In order for this to be a signed 24-bit value, bit 23, must
1355 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1356 // as unsigned 24-bit values.
1357 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1360 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1362 SelectionDAG &DAG = DCI.DAG;
1363 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1364 EVT VT = Op.getValueType();
1366 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1367 APInt KnownZero, KnownOne;
1368 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1369 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1370 DCI.CommitTargetLoweringOpt(TLO);
1373 template <typename IntTy>
1374 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1375 uint32_t Offset, uint32_t Width) {
1376 if (Width + Offset < 32) {
1377 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1378 return DAG.getConstant(Result, MVT::i32);
1381 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1384 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1385 DAGCombinerInfo &DCI) const {
1386 SelectionDAG &DAG = DCI.DAG;
1389 switch(N->getOpcode()) {
1392 EVT VT = N->getValueType(0);
1393 SDValue N0 = N->getOperand(0);
1394 SDValue N1 = N->getOperand(1);
1397 // FIXME: Add support for 24-bit multiply with 64-bit output on SI.
1398 if (VT.isVector() || VT.getSizeInBits() > 32)
1401 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1402 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1403 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1404 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1405 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1406 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1407 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1408 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1413 // We need to use sext even for MUL_U24, because MUL_U24 is used
1414 // for signed multiply of 8 and 16-bit types.
1415 SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
1419 case AMDGPUISD::MUL_I24:
1420 case AMDGPUISD::MUL_U24: {
1421 SDValue N0 = N->getOperand(0);
1422 SDValue N1 = N->getOperand(1);
1423 simplifyI24(N0, DCI);
1424 simplifyI24(N1, DCI);
1427 case ISD::SELECT_CC: {
1428 return CombineMinMax(N, DAG);
1430 case AMDGPUISD::BFE_I32:
1431 case AMDGPUISD::BFE_U32: {
1432 assert(!N->getValueType(0).isVector() &&
1433 "Vector handling of BFE not implemented");
1434 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
1438 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
1440 return DAG.getConstant(0, MVT::i32);
1442 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
1446 SDValue BitsFrom = N->getOperand(0);
1447 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
1449 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
1451 if (OffsetVal == 0) {
1452 // This is already sign / zero extended, so try to fold away extra BFEs.
1453 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
1455 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
1456 if (OpSignBits >= SignBits)
1459 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
1461 // This is a sign_extend_inreg. Replace it to take advantage of existing
1462 // DAG Combines. If not eliminated, we will match back to BFE during
1465 // TODO: The sext_inreg of extended types ends, although we can could
1466 // handle them in a single BFE.
1467 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
1468 DAG.getValueType(SmallVT));
1471 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
1474 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1476 return constantFoldBFE<int32_t>(DAG,
1477 Val->getSExtValue(),
1482 return constantFoldBFE<uint32_t>(DAG,
1483 Val->getZExtValue(),
1488 APInt Demanded = APInt::getBitsSet(32,
1490 OffsetVal + WidthVal);
1492 if ((OffsetVal + WidthVal) >= 32) {
1493 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
1494 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1495 BitsFrom, ShiftVal);
1498 APInt KnownZero, KnownOne;
1499 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1500 !DCI.isBeforeLegalizeOps());
1501 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1502 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
1503 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
1504 DCI.CommitTargetLoweringOpt(TLO);
1513 //===----------------------------------------------------------------------===//
1515 //===----------------------------------------------------------------------===//
1517 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1520 const SmallVectorImpl<ISD::InputArg> &Ins,
1521 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1523 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1524 if (Ins[i].ArgVT == Ins[i].VT) {
1525 OrigIns.push_back(Ins[i]);
1530 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
1531 // Vector has been split into scalars.
1532 VT = Ins[i].ArgVT.getVectorElementType();
1533 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
1534 Ins[i].ArgVT.getVectorElementType() !=
1535 Ins[i].VT.getVectorElementType()) {
1536 // Vector elements have been promoted
1539 // Vector has been spilt into smaller vectors.
1543 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
1544 Ins[i].OrigArgIndex, Ins[i].PartOffset);
1545 OrigIns.push_back(Arg);
1549 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
1550 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1551 return CFP->isExactlyValue(1.0);
1553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1554 return C->isAllOnesValue();
1559 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
1560 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1561 return CFP->getValueAPF().isZero();
1563 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1564 return C->isNullValue();
1569 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1570 const TargetRegisterClass *RC,
1571 unsigned Reg, EVT VT) const {
1572 MachineFunction &MF = DAG.getMachineFunction();
1573 MachineRegisterInfo &MRI = MF.getRegInfo();
1574 unsigned VirtualRegister;
1575 if (!MRI.isLiveIn(Reg)) {
1576 VirtualRegister = MRI.createVirtualRegister(RC);
1577 MRI.addLiveIn(Reg, VirtualRegister);
1579 VirtualRegister = MRI.getLiveInVirtReg(Reg);
1581 return DAG.getRegister(VirtualRegister, VT);
1584 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
1586 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
1588 default: return nullptr;
1590 NODE_NAME_CASE(CALL);
1591 NODE_NAME_CASE(UMUL);
1592 NODE_NAME_CASE(DIV_INF);
1593 NODE_NAME_CASE(RET_FLAG);
1594 NODE_NAME_CASE(BRANCH_COND);
1597 NODE_NAME_CASE(DWORDADDR)
1598 NODE_NAME_CASE(FRACT)
1599 NODE_NAME_CASE(CLAMP)
1600 NODE_NAME_CASE(FMAX)
1601 NODE_NAME_CASE(SMAX)
1602 NODE_NAME_CASE(UMAX)
1603 NODE_NAME_CASE(FMIN)
1604 NODE_NAME_CASE(SMIN)
1605 NODE_NAME_CASE(UMIN)
1606 NODE_NAME_CASE(BFE_U32)
1607 NODE_NAME_CASE(BFE_I32)
1610 NODE_NAME_CASE(MUL_U24)
1611 NODE_NAME_CASE(MUL_I24)
1612 NODE_NAME_CASE(MAD_U24)
1613 NODE_NAME_CASE(MAD_I24)
1614 NODE_NAME_CASE(URECIP)
1615 NODE_NAME_CASE(DOT4)
1616 NODE_NAME_CASE(EXPORT)
1617 NODE_NAME_CASE(CONST_ADDRESS)
1618 NODE_NAME_CASE(REGISTER_LOAD)
1619 NODE_NAME_CASE(REGISTER_STORE)
1620 NODE_NAME_CASE(LOAD_CONSTANT)
1621 NODE_NAME_CASE(LOAD_INPUT)
1622 NODE_NAME_CASE(SAMPLE)
1623 NODE_NAME_CASE(SAMPLEB)
1624 NODE_NAME_CASE(SAMPLED)
1625 NODE_NAME_CASE(SAMPLEL)
1626 NODE_NAME_CASE(CVT_F32_UBYTE0)
1627 NODE_NAME_CASE(CVT_F32_UBYTE1)
1628 NODE_NAME_CASE(CVT_F32_UBYTE2)
1629 NODE_NAME_CASE(CVT_F32_UBYTE3)
1630 NODE_NAME_CASE(STORE_MSKOR)
1631 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
1635 static void computeKnownBitsForMinMax(const SDValue Op0,
1639 const SelectionDAG &DAG,
1641 APInt Op0Zero, Op0One;
1642 APInt Op1Zero, Op1One;
1643 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
1644 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
1646 KnownZero = Op0Zero & Op1Zero;
1647 KnownOne = Op0One & Op1One;
1650 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
1654 const SelectionDAG &DAG,
1655 unsigned Depth) const {
1657 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
1661 unsigned Opc = Op.getOpcode();
1666 case ISD::INTRINSIC_WO_CHAIN: {
1667 // FIXME: The intrinsic should just use the node.
1668 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
1669 case AMDGPUIntrinsic::AMDGPU_imax:
1670 case AMDGPUIntrinsic::AMDGPU_umax:
1671 case AMDGPUIntrinsic::AMDGPU_imin:
1672 case AMDGPUIntrinsic::AMDGPU_umin:
1673 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
1674 KnownZero, KnownOne, DAG, Depth);
1682 case AMDGPUISD::SMAX:
1683 case AMDGPUISD::UMAX:
1684 case AMDGPUISD::SMIN:
1685 case AMDGPUISD::UMIN:
1686 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
1687 KnownZero, KnownOne, DAG, Depth);
1690 case AMDGPUISD::BFE_I32:
1691 case AMDGPUISD::BFE_U32: {
1692 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
1696 unsigned BitWidth = 32;
1697 uint32_t Width = CWidth->getZExtValue() & 0x1f;
1699 KnownZero = APInt::getAllOnesValue(BitWidth);
1700 KnownOne = APInt::getNullValue(BitWidth);
1704 // FIXME: This could do a lot more. If offset is 0, should be the same as
1705 // sign_extend_inreg implementation, but that involves duplicating it.
1706 if (Opc == AMDGPUISD::BFE_I32)
1707 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
1709 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
1716 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
1718 const SelectionDAG &DAG,
1719 unsigned Depth) const {
1720 switch (Op.getOpcode()) {
1721 case AMDGPUISD::BFE_I32: {
1722 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
1726 unsigned SignBits = 32 - Width->getZExtValue() + 1;
1727 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1728 if (!Offset || !Offset->isNullValue())
1731 // TODO: Could probably figure something out with non-0 offsets.
1732 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
1733 return std::max(SignBits, Op0SignBits);
1736 case AMDGPUISD::BFE_U32: {
1737 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
1738 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;