1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 // Find a larger type to do a load / store of a vector with.
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
91 return EVT::getIntegerVT(Ctx, StoreSize);
93 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
97 // Type for a vector that will be loaded to.
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
101 return EVT::getIntegerVT(Ctx, 32);
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
107 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
109 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
111 setOperationAction(ISD::Constant, MVT::i32, Legal);
112 setOperationAction(ISD::Constant, MVT::i64, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
114 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
116 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
117 setOperationAction(ISD::BRIND, MVT::Other, Expand);
119 // We need to custom lower some of the intrinsics
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
122 // Library functions. These default to Expand, but we have instructions
124 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
125 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
126 setOperationAction(ISD::FPOW, MVT::f32, Legal);
127 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
128 setOperationAction(ISD::FABS, MVT::f32, Legal);
129 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
130 setOperationAction(ISD::FRINT, MVT::f32, Legal);
131 setOperationAction(ISD::FROUND, MVT::f32, Legal);
132 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
134 // Lower floating point store/load to integer store/load to reduce the number
135 // of patterns in tablegen.
136 setOperationAction(ISD::STORE, MVT::f32, Promote);
137 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
139 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
140 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
142 setOperationAction(ISD::STORE, MVT::i64, Promote);
143 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
145 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
146 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
148 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
149 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
151 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
152 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
154 setOperationAction(ISD::STORE, MVT::f64, Promote);
155 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
157 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
158 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
160 // Custom lowering of vector stores is required for local address space
162 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
163 // XXX: Native v2i32 local address space stores are possible, but not
164 // currently implemented.
165 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
167 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
168 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
169 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
171 // XXX: This can be change to Custom, once ExpandVectorStores can
172 // handle 64-bit stores.
173 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
175 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
176 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
178 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
179 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
182 setOperationAction(ISD::LOAD, MVT::f32, Promote);
183 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
185 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
186 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
188 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
189 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
191 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
192 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
194 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
195 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
197 setOperationAction(ISD::LOAD, MVT::f64, Promote);
198 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
200 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
201 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
203 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
204 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
205 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
206 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
207 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
208 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
209 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
210 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
211 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
214 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
215 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
216 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
217 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
218 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
220 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
221 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
223 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
224 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
225 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
227 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
229 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
230 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
231 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
232 setOperationAction(ISD::FRINT, MVT::f64, Custom);
233 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
236 if (!Subtarget->hasBFI()) {
237 // fcopysign can be done in a single instruction with BFI.
238 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
239 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
242 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
243 for (MVT VT : ScalarIntVTs) {
244 setOperationAction(ISD::SREM, VT, Expand);
245 setOperationAction(ISD::SDIV, VT, Expand);
247 // GPU does not have divrem function for signed or unsigned.
248 setOperationAction(ISD::SDIVREM, VT, Custom);
249 setOperationAction(ISD::UDIVREM, VT, Custom);
251 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
252 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
253 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
255 setOperationAction(ISD::BSWAP, VT, Expand);
256 setOperationAction(ISD::CTTZ, VT, Expand);
257 setOperationAction(ISD::CTLZ, VT, Expand);
260 if (!Subtarget->hasBCNT(32))
261 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
263 if (!Subtarget->hasBCNT(64))
264 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
266 // The hardware supports 32-bit ROTR, but not ROTL.
267 setOperationAction(ISD::ROTL, MVT::i32, Expand);
268 setOperationAction(ISD::ROTL, MVT::i64, Expand);
269 setOperationAction(ISD::ROTR, MVT::i64, Expand);
271 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
272 setOperationAction(ISD::MUL, MVT::i64, Expand);
273 setOperationAction(ISD::MULHU, MVT::i64, Expand);
274 setOperationAction(ISD::MULHS, MVT::i64, Expand);
275 setOperationAction(ISD::UDIV, MVT::i32, Expand);
276 setOperationAction(ISD::UREM, MVT::i32, Expand);
277 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
278 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
280 static const MVT::SimpleValueType VectorIntTypes[] = {
281 MVT::v2i32, MVT::v4i32
284 for (MVT VT : VectorIntTypes) {
285 // Expand the following operations for the current type by default.
286 setOperationAction(ISD::ADD, VT, Expand);
287 setOperationAction(ISD::AND, VT, Expand);
288 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
289 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
290 setOperationAction(ISD::MUL, VT, Expand);
291 setOperationAction(ISD::OR, VT, Expand);
292 setOperationAction(ISD::SHL, VT, Expand);
293 setOperationAction(ISD::SRA, VT, Expand);
294 setOperationAction(ISD::SRL, VT, Expand);
295 setOperationAction(ISD::ROTL, VT, Expand);
296 setOperationAction(ISD::ROTR, VT, Expand);
297 setOperationAction(ISD::SUB, VT, Expand);
298 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
299 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
300 // TODO: Implement custom UREM / SREM routines.
301 setOperationAction(ISD::SDIV, VT, Expand);
302 setOperationAction(ISD::UDIV, VT, Expand);
303 setOperationAction(ISD::SREM, VT, Expand);
304 setOperationAction(ISD::UREM, VT, Expand);
305 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
306 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
307 setOperationAction(ISD::SDIVREM, VT, Custom);
308 setOperationAction(ISD::UDIVREM, VT, Custom);
309 setOperationAction(ISD::ADDC, VT, Expand);
310 setOperationAction(ISD::SUBC, VT, Expand);
311 setOperationAction(ISD::ADDE, VT, Expand);
312 setOperationAction(ISD::SUBE, VT, Expand);
313 setOperationAction(ISD::SELECT, VT, Expand);
314 setOperationAction(ISD::VSELECT, VT, Expand);
315 setOperationAction(ISD::SELECT_CC, VT, Expand);
316 setOperationAction(ISD::XOR, VT, Expand);
317 setOperationAction(ISD::BSWAP, VT, Expand);
318 setOperationAction(ISD::CTPOP, VT, Expand);
319 setOperationAction(ISD::CTTZ, VT, Expand);
320 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
321 setOperationAction(ISD::CTLZ, VT, Expand);
322 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
323 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
326 static const MVT::SimpleValueType FloatVectorTypes[] = {
327 MVT::v2f32, MVT::v4f32
330 for (MVT VT : FloatVectorTypes) {
331 setOperationAction(ISD::FABS, VT, Expand);
332 setOperationAction(ISD::FADD, VT, Expand);
333 setOperationAction(ISD::FCEIL, VT, Expand);
334 setOperationAction(ISD::FCOS, VT, Expand);
335 setOperationAction(ISD::FDIV, VT, Expand);
336 setOperationAction(ISD::FEXP2, VT, Expand);
337 setOperationAction(ISD::FLOG2, VT, Expand);
338 setOperationAction(ISD::FPOW, VT, Expand);
339 setOperationAction(ISD::FFLOOR, VT, Expand);
340 setOperationAction(ISD::FTRUNC, VT, Expand);
341 setOperationAction(ISD::FMUL, VT, Expand);
342 setOperationAction(ISD::FMA, VT, Expand);
343 setOperationAction(ISD::FRINT, VT, Expand);
344 setOperationAction(ISD::FNEARBYINT, VT, Expand);
345 setOperationAction(ISD::FSQRT, VT, Expand);
346 setOperationAction(ISD::FSIN, VT, Expand);
347 setOperationAction(ISD::FSUB, VT, Expand);
348 setOperationAction(ISD::FNEG, VT, Expand);
349 setOperationAction(ISD::SELECT, VT, Expand);
350 setOperationAction(ISD::VSELECT, VT, Expand);
351 setOperationAction(ISD::SELECT_CC, VT, Expand);
352 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
353 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
356 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
357 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
359 setTargetDAGCombine(ISD::MUL);
360 setTargetDAGCombine(ISD::SELECT_CC);
362 setSchedulingPreference(Sched::RegPressure);
363 setJumpIsExpensive(true);
365 setSelectIsExpensive(false);
366 PredictableSelectIsExpensive = false;
368 // There are no integer divide instructions, and these expand to a pretty
369 // large sequence of instructions.
370 setIntDivIsCheap(false);
371 setPow2DivIsCheap(false);
373 // TODO: Investigate this when 64-bit divides are implemented.
374 addBypassSlowDiv(64, 32);
376 // FIXME: Need to really handle these.
377 MaxStoresPerMemcpy = 4096;
378 MaxStoresPerMemmove = 4096;
379 MaxStoresPerMemset = 4096;
382 //===----------------------------------------------------------------------===//
383 // Target Information
384 //===----------------------------------------------------------------------===//
386 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
390 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
394 // The backend supports 32 and 64 bit floating point immediates.
395 // FIXME: Why are we reporting vectors of FP immediates as legal?
396 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
397 EVT ScalarVT = VT.getScalarType();
398 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
401 // We don't want to shrink f64 / f32 constants.
402 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
403 EVT ScalarVT = VT.getScalarType();
404 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
407 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
409 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
412 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
413 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
415 return ((LScalarSize <= CastScalarSize) ||
416 (CastScalarSize >= 32) ||
420 //===---------------------------------------------------------------------===//
422 //===---------------------------------------------------------------------===//
424 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
425 assert(VT.isFloatingPoint());
426 return VT == MVT::f32;
429 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
430 assert(VT.isFloatingPoint());
431 return VT == MVT::f32;
434 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
435 // Truncate is just accessing a subregister.
436 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
439 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
440 // Truncate is just accessing a subregister.
441 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
442 (Dest->getPrimitiveSizeInBits() % 32 == 0);
445 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
446 const DataLayout *DL = getDataLayout();
447 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
448 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
450 return SrcSize == 32 && DestSize == 64;
453 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
454 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
455 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
456 // this will enable reducing 64-bit operations the 32-bit, which is always
458 return Src == MVT::i32 && Dest == MVT::i64;
461 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
462 return isZExtFree(Val.getValueType(), VT2);
465 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
466 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
467 // limited number of native 64-bit operations. Shrinking an operation to fit
468 // in a single 32-bit register should always be helpful. As currently used,
469 // this is much less general than the name suggests, and is only used in
470 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
471 // not profitable, and may actually be harmful.
472 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
475 //===---------------------------------------------------------------------===//
476 // TargetLowering Callbacks
477 //===---------------------------------------------------------------------===//
479 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
480 const SmallVectorImpl<ISD::InputArg> &Ins) const {
482 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
485 SDValue AMDGPUTargetLowering::LowerReturn(
487 CallingConv::ID CallConv,
489 const SmallVectorImpl<ISD::OutputArg> &Outs,
490 const SmallVectorImpl<SDValue> &OutVals,
491 SDLoc DL, SelectionDAG &DAG) const {
492 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
495 //===---------------------------------------------------------------------===//
496 // Target specific lowering
497 //===---------------------------------------------------------------------===//
499 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
500 SmallVectorImpl<SDValue> &InVals) const {
501 SDValue Callee = CLI.Callee;
502 SelectionDAG &DAG = CLI.DAG;
504 const Function &Fn = *DAG.getMachineFunction().getFunction();
506 StringRef FuncName("<unknown>");
508 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
509 FuncName = G->getSymbol();
510 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
511 FuncName = G->getGlobal()->getName();
513 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
514 DAG.getContext()->diagnose(NoCalls);
518 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
519 SelectionDAG &DAG) const {
520 switch (Op.getOpcode()) {
522 Op.getNode()->dump();
523 llvm_unreachable("Custom lowering code for this"
524 "instruction is not implemented yet!");
526 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
527 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
528 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
529 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
530 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
531 case ISD::SDIV: return LowerSDIV(Op, DAG);
532 case ISD::SREM: return LowerSREM(Op, DAG);
533 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
534 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
535 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
536 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
537 case ISD::FRINT: return LowerFRINT(Op, DAG);
538 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
539 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
540 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
545 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
546 SmallVectorImpl<SDValue> &Results,
547 SelectionDAG &DAG) const {
548 switch (N->getOpcode()) {
549 case ISD::SIGN_EXTEND_INREG:
550 // Different parts of legalization seem to interpret which type of
551 // sign_extend_inreg is the one to check for custom lowering. The extended
552 // from type is what really matters, but some places check for custom
553 // lowering of the result type. This results in trying to use
554 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
555 // nothing here and let the illegal result integer be handled normally.
558 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
559 Results.push_back(SDValue(Node, 0));
560 Results.push_back(SDValue(Node, 1));
561 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
563 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
567 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
568 Results.push_back(SDValue(Node, 0));
576 // FIXME: This implements accesses to initialized globals in the constant
577 // address space by copying them to private and accessing that. It does not
578 // properly handle illegal types or vectors. The private vector loads are not
579 // scalarized, and the illegal scalars hit an assertion. This technique will not
580 // work well with large initializers, and this should eventually be
581 // removed. Initialized globals should be placed into a data section that the
582 // runtime will load into a buffer before the kernel is executed. Uses of the
583 // global need to be replaced with a pointer loaded from an implicit kernel
584 // argument into this buffer holding the copy of the data, which will remove the
585 // need for any of this.
586 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
587 const GlobalValue *GV,
588 const SDValue &InitPtr,
590 SelectionDAG &DAG) const {
591 const DataLayout *TD = getTargetMachine().getDataLayout();
593 Type *InitTy = Init->getType();
595 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
596 EVT VT = EVT::getEVT(InitTy);
597 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
598 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
599 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
600 TD->getPrefTypeAlignment(InitTy));
603 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
604 EVT VT = EVT::getEVT(CFP->getType());
605 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
606 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
607 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
608 TD->getPrefTypeAlignment(CFP->getType()));
611 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
612 const StructLayout *SL = TD->getStructLayout(ST);
614 EVT PtrVT = InitPtr.getValueType();
615 SmallVector<SDValue, 8> Chains;
617 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
618 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
619 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
621 Constant *Elt = Init->getAggregateElement(I);
622 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
625 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
628 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
629 EVT PtrVT = InitPtr.getValueType();
631 unsigned NumElements;
632 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
633 NumElements = AT->getNumElements();
634 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
635 NumElements = VT->getNumElements();
637 llvm_unreachable("Unexpected type");
639 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
640 SmallVector<SDValue, 8> Chains;
641 for (unsigned i = 0; i < NumElements; ++i) {
642 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
643 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
645 Constant *Elt = Init->getAggregateElement(i);
646 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
649 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
652 if (isa<UndefValue>(Init)) {
653 EVT VT = EVT::getEVT(InitTy);
654 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
655 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
656 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
657 TD->getPrefTypeAlignment(InitTy));
661 llvm_unreachable("Unhandled constant initializer");
664 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
666 SelectionDAG &DAG) const {
668 const DataLayout *TD = getTargetMachine().getDataLayout();
669 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
670 const GlobalValue *GV = G->getGlobal();
672 switch (G->getAddressSpace()) {
673 default: llvm_unreachable("Global Address lowering not implemented for this "
675 case AMDGPUAS::LOCAL_ADDRESS: {
676 // XXX: What does the value of G->getOffset() mean?
677 assert(G->getOffset() == 0 &&
678 "Do not know what to do with an non-zero offset");
681 if (MFI->LocalMemoryObjects.count(GV) == 0) {
682 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
683 Offset = MFI->LDSSize;
684 MFI->LocalMemoryObjects[GV] = Offset;
685 // XXX: Account for alignment?
686 MFI->LDSSize += Size;
688 Offset = MFI->LocalMemoryObjects[GV];
691 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
693 case AMDGPUAS::CONSTANT_ADDRESS: {
694 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
695 Type *EltType = GV->getType()->getElementType();
696 unsigned Size = TD->getTypeAllocSize(EltType);
697 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
699 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
700 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
702 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
703 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
705 const GlobalVariable *Var = cast<GlobalVariable>(GV);
706 if (!Var->hasInitializer()) {
707 // This has no use, but bugpoint will hit it.
708 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
711 const Constant *Init = Var->getInitializer();
712 SmallVector<SDNode*, 8> WorkList;
714 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
715 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
716 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
718 WorkList.push_back(*I);
720 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
721 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
722 E = WorkList.end(); I != E; ++I) {
723 SmallVector<SDValue, 8> Ops;
724 Ops.push_back(Chain);
725 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
726 Ops.push_back((*I)->getOperand(i));
728 DAG.UpdateNodeOperands(*I, Ops);
730 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
735 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
736 SelectionDAG &DAG) const {
737 SmallVector<SDValue, 8> Args;
738 SDValue A = Op.getOperand(0);
739 SDValue B = Op.getOperand(1);
741 DAG.ExtractVectorElements(A, Args);
742 DAG.ExtractVectorElements(B, Args);
744 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
747 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
748 SelectionDAG &DAG) const {
750 SmallVector<SDValue, 8> Args;
751 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
752 EVT VT = Op.getValueType();
753 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
754 VT.getVectorNumElements());
756 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
759 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
760 SelectionDAG &DAG) const {
762 MachineFunction &MF = DAG.getMachineFunction();
763 const AMDGPUFrameLowering *TFL =
764 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
766 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
768 unsigned FrameIndex = FIN->getIndex();
769 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
770 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
774 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
775 SelectionDAG &DAG) const {
776 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
778 EVT VT = Op.getValueType();
780 switch (IntrinsicID) {
782 case AMDGPUIntrinsic::AMDGPU_abs:
783 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
784 return LowerIntrinsicIABS(Op, DAG);
785 case AMDGPUIntrinsic::AMDGPU_lrp:
786 return LowerIntrinsicLRP(Op, DAG);
787 case AMDGPUIntrinsic::AMDGPU_fract:
788 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
789 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
791 case AMDGPUIntrinsic::AMDGPU_clamp:
792 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
793 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
794 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
796 case Intrinsic::AMDGPU_div_scale: {
797 // 3rd parameter required to be a constant.
798 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
800 return DAG.getUNDEF(VT);
802 // Translate to the operands expected by the machine instruction. The
803 // first parameter must be the same as the first instruction.
804 SDValue Numerator = Op.getOperand(1);
805 SDValue Denominator = Op.getOperand(2);
806 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
808 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, VT,
809 Src0, Denominator, Numerator);
812 case Intrinsic::AMDGPU_div_fmas:
813 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
814 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
816 case Intrinsic::AMDGPU_div_fixup:
817 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
818 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
820 case Intrinsic::AMDGPU_trig_preop:
821 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
822 Op.getOperand(1), Op.getOperand(2));
824 case Intrinsic::AMDGPU_rcp:
825 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
827 case Intrinsic::AMDGPU_rsq:
828 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
830 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
831 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
833 case Intrinsic::AMDGPU_rsq_clamped:
834 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
836 case AMDGPUIntrinsic::AMDGPU_imax:
837 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
839 case AMDGPUIntrinsic::AMDGPU_umax:
840 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
842 case AMDGPUIntrinsic::AMDGPU_imin:
843 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
845 case AMDGPUIntrinsic::AMDGPU_umin:
846 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
849 case AMDGPUIntrinsic::AMDGPU_umul24:
850 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
851 Op.getOperand(1), Op.getOperand(2));
853 case AMDGPUIntrinsic::AMDGPU_imul24:
854 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
855 Op.getOperand(1), Op.getOperand(2));
857 case AMDGPUIntrinsic::AMDGPU_umad24:
858 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
859 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
861 case AMDGPUIntrinsic::AMDGPU_imad24:
862 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
863 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
865 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
866 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
868 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
869 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
871 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
872 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
874 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
875 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
877 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
878 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
883 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
884 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
889 case AMDGPUIntrinsic::AMDGPU_bfi:
890 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
895 case AMDGPUIntrinsic::AMDGPU_bfm:
896 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
900 case AMDGPUIntrinsic::AMDGPU_brev:
901 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
903 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
904 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
906 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
907 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
908 case AMDGPUIntrinsic::AMDGPU_trunc:
909 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
913 ///IABS(a) = SMAX(sub(0, a), a)
914 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
915 SelectionDAG &DAG) const {
917 EVT VT = Op.getValueType();
918 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
921 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
924 /// Linear Interpolation
925 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
926 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
927 SelectionDAG &DAG) const {
929 EVT VT = Op.getValueType();
930 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
931 DAG.getConstantFP(1.0f, MVT::f32),
933 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
935 return DAG.getNode(ISD::FADD, DL, VT,
936 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
940 /// \brief Generate Min/Max node
941 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
942 SelectionDAG &DAG) const {
944 EVT VT = N->getValueType(0);
946 SDValue LHS = N->getOperand(0);
947 SDValue RHS = N->getOperand(1);
948 SDValue True = N->getOperand(2);
949 SDValue False = N->getOperand(3);
950 SDValue CC = N->getOperand(4);
952 if (VT != MVT::f32 ||
953 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
957 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
971 llvm_unreachable("Operation should already be optimised!");
978 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
979 return DAG.getNode(Opc, DL, VT, LHS, RHS);
987 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
988 return DAG.getNode(Opc, DL, VT, LHS, RHS);
990 case ISD::SETCC_INVALID:
991 llvm_unreachable("Invalid setcc condcode!");
996 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
997 SelectionDAG &DAG) const {
998 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
999 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
1000 EVT EltVT = Op.getValueType().getVectorElementType();
1001 EVT PtrVT = Load->getBasePtr().getValueType();
1002 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1003 SmallVector<SDValue, 8> Loads;
1006 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1007 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1008 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
1009 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1010 Load->getChain(), Ptr,
1011 MachinePointerInfo(Load->getMemOperand()->getValue()),
1012 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1013 Load->getAlignment()));
1015 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
1018 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1019 SelectionDAG &DAG) const {
1020 StoreSDNode *Store = cast<StoreSDNode>(Op);
1021 EVT MemVT = Store->getMemoryVT();
1022 unsigned MemBits = MemVT.getSizeInBits();
1024 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1025 // truncating store into an i32 store.
1026 // XXX: We could also handle optimize other vector bitwidths.
1027 if (!MemVT.isVector() || MemBits > 32) {
1032 SDValue Value = Store->getValue();
1033 EVT VT = Value.getValueType();
1034 EVT ElemVT = VT.getVectorElementType();
1035 SDValue Ptr = Store->getBasePtr();
1036 EVT MemEltVT = MemVT.getVectorElementType();
1037 unsigned MemEltBits = MemEltVT.getSizeInBits();
1038 unsigned MemNumElements = MemVT.getVectorNumElements();
1039 unsigned PackedSize = MemVT.getStoreSizeInBits();
1040 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1042 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1044 SDValue PackedValue;
1045 for (unsigned i = 0; i < MemNumElements; ++i) {
1046 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1047 DAG.getConstant(i, MVT::i32));
1048 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1049 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1051 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1052 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1057 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1061 if (PackedSize < 32) {
1062 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1063 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1064 Store->getMemOperand()->getPointerInfo(),
1066 Store->isNonTemporal(), Store->isVolatile(),
1067 Store->getAlignment());
1070 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1071 Store->getMemOperand()->getPointerInfo(),
1072 Store->isVolatile(), Store->isNonTemporal(),
1073 Store->getAlignment());
1076 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1077 SelectionDAG &DAG) const {
1078 StoreSDNode *Store = cast<StoreSDNode>(Op);
1079 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1080 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1081 EVT PtrVT = Store->getBasePtr().getValueType();
1082 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1085 SmallVector<SDValue, 8> Chains;
1087 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1088 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1089 Store->getValue(), DAG.getConstant(i, MVT::i32));
1090 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
1091 Store->getBasePtr(),
1092 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
1094 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1095 MachinePointerInfo(Store->getMemOperand()->getValue()),
1096 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
1097 Store->getAlignment()));
1099 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1102 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1104 LoadSDNode *Load = cast<LoadSDNode>(Op);
1105 ISD::LoadExtType ExtType = Load->getExtensionType();
1106 EVT VT = Op.getValueType();
1107 EVT MemVT = Load->getMemoryVT();
1109 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1110 // We can do the extload to 32-bits, and then need to separately extend to
1113 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1117 Load->getMemOperand());
1118 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
1121 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1122 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1123 // FIXME: Copied from PPC
1124 // First, load into 32 bits, then truncate to 1 bit.
1126 SDValue Chain = Load->getChain();
1127 SDValue BasePtr = Load->getBasePtr();
1128 MachineMemOperand *MMO = Load->getMemOperand();
1130 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1131 BasePtr, MVT::i8, MMO);
1132 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1135 // Lower loads constant address space global variable loads
1136 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1137 isa<GlobalVariable>(
1138 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
1140 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
1141 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1142 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1143 DAG.getConstant(2, MVT::i32));
1144 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1145 Load->getChain(), Ptr,
1146 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1149 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1150 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1154 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1155 DAG.getConstant(2, MVT::i32));
1156 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1157 Load->getChain(), Ptr,
1158 DAG.getTargetConstant(0, MVT::i32),
1160 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1162 DAG.getConstant(0x3, MVT::i32));
1163 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1164 DAG.getConstant(3, MVT::i32));
1166 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1168 EVT MemEltVT = MemVT.getScalarType();
1169 if (ExtType == ISD::SEXTLOAD) {
1170 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1171 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1174 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1177 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1179 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1180 if (Result.getNode()) {
1184 StoreSDNode *Store = cast<StoreSDNode>(Op);
1185 SDValue Chain = Store->getChain();
1186 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1187 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1188 Store->getValue().getValueType().isVector()) {
1189 return SplitVectorStore(Op, DAG);
1192 EVT MemVT = Store->getMemoryVT();
1193 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1194 MemVT.bitsLT(MVT::i32)) {
1196 if (Store->getMemoryVT() == MVT::i8) {
1198 } else if (Store->getMemoryVT() == MVT::i16) {
1201 SDValue BasePtr = Store->getBasePtr();
1202 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1203 DAG.getConstant(2, MVT::i32));
1204 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1205 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1207 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1208 DAG.getConstant(0x3, MVT::i32));
1210 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1211 DAG.getConstant(3, MVT::i32));
1213 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1216 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1218 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1219 MaskedValue, ShiftAmt);
1221 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1223 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1224 DAG.getConstant(0xffffffff, MVT::i32));
1225 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1227 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1228 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1229 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1234 SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
1236 EVT OVT = Op.getValueType();
1237 SDValue LHS = Op.getOperand(0);
1238 SDValue RHS = Op.getOperand(1);
1241 if (!OVT.isVector()) {
1244 } else if (OVT.getVectorNumElements() == 2) {
1247 } else if (OVT.getVectorNumElements() == 4) {
1251 unsigned bitsize = OVT.getScalarType().getSizeInBits();
1252 // char|short jq = ia ^ ib;
1253 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
1255 // jq = jq >> (bitsize - 2)
1256 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
1259 jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
1262 jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
1264 // int ia = (int)LHS;
1265 SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
1267 // int ib, (int)RHS;
1268 SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
1270 // float fa = (float)ia;
1271 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
1273 // float fb = (float)ib;
1274 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
1276 // float fq = native_divide(fa, fb);
1277 SDValue fq = DAG.getNode(ISD::FMUL, DL, FLTTY,
1278 fa, DAG.getNode(AMDGPUISD::RCP, DL, FLTTY, fb));
1281 fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
1283 // float fqneg = -fq;
1284 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
1286 // float fr = mad(fqneg, fb, fa);
1287 SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
1288 DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
1290 // int iq = (int)fq;
1291 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
1294 fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
1297 fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
1299 // int cv = fr >= fb;
1301 if (INTTY == MVT::i32) {
1302 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1304 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1306 // jq = (cv ? jq : 0);
1307 jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
1308 DAG.getConstant(0, OVT));
1310 iq = DAG.getSExtOrTrunc(iq, DL, OVT);
1311 iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
1315 SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
1317 EVT OVT = Op.getValueType();
1318 SDValue LHS = Op.getOperand(0);
1319 SDValue RHS = Op.getOperand(1);
1320 // The LowerSDIV32 function generates equivalent to the following IL.
1330 // ixor r10, r10, r11
1332 // ixor DST, r0, r10
1341 SDValue r10 = DAG.getSelectCC(DL,
1342 r0, DAG.getConstant(0, OVT),
1343 DAG.getConstant(-1, OVT),
1344 DAG.getConstant(0, OVT),
1348 SDValue r11 = DAG.getSelectCC(DL,
1349 r1, DAG.getConstant(0, OVT),
1350 DAG.getConstant(-1, OVT),
1351 DAG.getConstant(0, OVT),
1355 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1358 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1361 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1364 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1367 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
1369 // ixor r10, r10, r11
1370 r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
1373 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1375 // ixor DST, r0, r10
1376 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1380 SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
1381 return SDValue(Op.getNode(), 0);
1384 SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
1385 EVT OVT = Op.getValueType().getScalarType();
1387 if (OVT == MVT::i64)
1388 return LowerSDIV64(Op, DAG);
1390 if (OVT.getScalarType() == MVT::i32)
1391 return LowerSDIV32(Op, DAG);
1393 if (OVT == MVT::i16 || OVT == MVT::i8) {
1394 // FIXME: We should be checking for the masked bits. This isn't reached
1395 // because i8 and i16 are not legal types.
1396 return LowerSDIV24(Op, DAG);
1399 return SDValue(Op.getNode(), 0);
1402 SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
1404 EVT OVT = Op.getValueType();
1405 SDValue LHS = Op.getOperand(0);
1406 SDValue RHS = Op.getOperand(1);
1407 // The LowerSREM32 function generates equivalent to the following IL.
1417 // umul r20, r20, r1
1420 // ixor DST, r0, r10
1429 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
1432 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
1435 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1438 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1441 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1444 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1447 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
1449 // umul r20, r20, r1
1450 r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
1453 r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
1456 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1458 // ixor DST, r0, r10
1459 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1463 SDValue AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
1464 return SDValue(Op.getNode(), 0);
1467 SDValue AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
1468 EVT OVT = Op.getValueType();
1470 if (OVT.getScalarType() == MVT::i64)
1471 return LowerSREM64(Op, DAG);
1473 if (OVT.getScalarType() == MVT::i32)
1474 return LowerSREM32(Op, DAG);
1476 return SDValue(Op.getNode(), 0);
1479 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1480 SelectionDAG &DAG) const {
1482 EVT VT = Op.getValueType();
1484 SDValue Num = Op.getOperand(0);
1485 SDValue Den = Op.getOperand(1);
1487 // RCP = URECIP(Den) = 2^32 / Den + e
1488 // e is rounding error.
1489 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1491 // RCP_LO = umulo(RCP, Den) */
1492 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1494 // RCP_HI = mulhu (RCP, Den) */
1495 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1497 // NEG_RCP_LO = -RCP_LO
1498 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1501 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1502 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1505 // Calculate the rounding error from the URECIP instruction
1506 // E = mulhu(ABS_RCP_LO, RCP)
1507 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1509 // RCP_A_E = RCP + E
1510 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1512 // RCP_S_E = RCP - E
1513 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1515 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1516 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1519 // Quotient = mulhu(Tmp0, Num)
1520 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1522 // Num_S_Remainder = Quotient * Den
1523 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1525 // Remainder = Num - Num_S_Remainder
1526 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1528 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1529 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1530 DAG.getConstant(-1, VT),
1531 DAG.getConstant(0, VT),
1533 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1534 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1536 DAG.getConstant(-1, VT),
1537 DAG.getConstant(0, VT),
1539 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1540 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1543 // Calculate Division result:
1545 // Quotient_A_One = Quotient + 1
1546 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1547 DAG.getConstant(1, VT));
1549 // Quotient_S_One = Quotient - 1
1550 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1551 DAG.getConstant(1, VT));
1553 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1554 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1555 Quotient, Quotient_A_One, ISD::SETEQ);
1557 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1558 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1559 Quotient_S_One, Div, ISD::SETEQ);
1561 // Calculate Rem result:
1563 // Remainder_S_Den = Remainder - Den
1564 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1566 // Remainder_A_Den = Remainder + Den
1567 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1569 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1570 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1571 Remainder, Remainder_S_Den, ISD::SETEQ);
1573 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1574 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1575 Remainder_A_Den, Rem, ISD::SETEQ);
1580 return DAG.getMergeValues(Ops, DL);
1583 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1584 SelectionDAG &DAG) const {
1586 EVT VT = Op.getValueType();
1588 SDValue Zero = DAG.getConstant(0, VT);
1589 SDValue NegOne = DAG.getConstant(-1, VT);
1591 SDValue LHS = Op.getOperand(0);
1592 SDValue RHS = Op.getOperand(1);
1594 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1595 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1596 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1597 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1599 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1600 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1602 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1603 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1605 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1606 SDValue Rem = Div.getValue(1);
1608 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1609 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1611 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1612 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1618 return DAG.getMergeValues(Res, DL);
1621 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1623 SDValue Src = Op.getOperand(0);
1625 // result = trunc(src)
1626 // if (src > 0.0 && src != result)
1629 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1631 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1632 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1634 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1636 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1637 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1638 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1640 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1641 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1644 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1646 SDValue Src = Op.getOperand(0);
1648 assert(Op.getValueType() == MVT::f64);
1650 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1651 const SDValue One = DAG.getConstant(1, MVT::i32);
1653 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1655 // Extract the upper half, since this is where we will find the sign and
1657 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1659 const unsigned FractBits = 52;
1660 const unsigned ExpBits = 11;
1662 // Extract the exponent.
1663 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_I32, SL, MVT::i32,
1665 DAG.getConstant(FractBits - 32, MVT::i32),
1666 DAG.getConstant(ExpBits, MVT::i32));
1667 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1668 DAG.getConstant(1023, MVT::i32));
1670 // Extract the sign bit.
1671 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1672 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1674 // Extend back to to 64-bits.
1675 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1677 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1679 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1680 const SDValue FractMask
1681 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1683 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1684 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1685 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1687 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1689 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1691 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1692 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1694 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1695 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1697 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1700 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1702 SDValue Src = Op.getOperand(0);
1704 assert(Op.getValueType() == MVT::f64);
1706 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1707 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1708 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1710 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1711 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1713 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1715 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1716 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1718 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1719 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1721 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1724 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1725 // FNEARBYINT and FRINT are the same, except in their handling of FP
1726 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1727 // rint, so just treat them as equivalent.
1728 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1731 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1733 SDValue Src = Op.getOperand(0);
1735 // result = trunc(src);
1736 // if (src < 0.0 && src != result)
1739 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1741 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1742 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1744 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1746 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1747 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1748 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1750 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1751 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1754 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1755 SelectionDAG &DAG) const {
1756 SDValue S0 = Op.getOperand(0);
1758 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1761 // f32 uint_to_fp i64
1762 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1763 DAG.getConstant(0, MVT::i32));
1764 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1765 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1766 DAG.getConstant(1, MVT::i32));
1767 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1768 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1769 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1770 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1773 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1775 SelectionDAG &DAG) const {
1776 MVT VT = Op.getSimpleValueType();
1778 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1779 // Shift left by 'Shift' bits.
1780 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1781 // Signed shift Right by 'Shift' bits.
1782 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1785 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1786 SelectionDAG &DAG) const {
1787 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1788 MVT VT = Op.getSimpleValueType();
1789 MVT ScalarVT = VT.getScalarType();
1794 SDValue Src = Op.getOperand(0);
1797 // TODO: Don't scalarize on Evergreen?
1798 unsigned NElts = VT.getVectorNumElements();
1799 SmallVector<SDValue, 8> Args;
1800 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1802 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1803 for (unsigned I = 0; I < NElts; ++I)
1804 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1806 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1809 //===----------------------------------------------------------------------===//
1810 // Custom DAG optimizations
1811 //===----------------------------------------------------------------------===//
1813 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1814 APInt KnownZero, KnownOne;
1815 EVT VT = Op.getValueType();
1816 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1818 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1821 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1822 EVT VT = Op.getValueType();
1824 // In order for this to be a signed 24-bit value, bit 23, must
1826 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1827 // as unsigned 24-bit values.
1828 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1831 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1833 SelectionDAG &DAG = DCI.DAG;
1834 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1835 EVT VT = Op.getValueType();
1837 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1838 APInt KnownZero, KnownOne;
1839 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1840 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1841 DCI.CommitTargetLoweringOpt(TLO);
1844 template <typename IntTy>
1845 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1846 uint32_t Offset, uint32_t Width) {
1847 if (Width + Offset < 32) {
1848 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1849 return DAG.getConstant(Result, MVT::i32);
1852 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1855 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1856 DAGCombinerInfo &DCI) const {
1857 SelectionDAG &DAG = DCI.DAG;
1860 switch(N->getOpcode()) {
1863 EVT VT = N->getValueType(0);
1864 SDValue N0 = N->getOperand(0);
1865 SDValue N1 = N->getOperand(1);
1868 // FIXME: Add support for 24-bit multiply with 64-bit output on SI.
1869 if (VT.isVector() || VT.getSizeInBits() > 32)
1872 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1873 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1874 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1875 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1876 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1877 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1878 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1879 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1884 // We need to use sext even for MUL_U24, because MUL_U24 is used
1885 // for signed multiply of 8 and 16-bit types.
1886 SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
1890 case AMDGPUISD::MUL_I24:
1891 case AMDGPUISD::MUL_U24: {
1892 SDValue N0 = N->getOperand(0);
1893 SDValue N1 = N->getOperand(1);
1894 simplifyI24(N0, DCI);
1895 simplifyI24(N1, DCI);
1898 case ISD::SELECT_CC: {
1899 return CombineMinMax(N, DAG);
1901 case AMDGPUISD::BFE_I32:
1902 case AMDGPUISD::BFE_U32: {
1903 assert(!N->getValueType(0).isVector() &&
1904 "Vector handling of BFE not implemented");
1905 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
1909 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
1911 return DAG.getConstant(0, MVT::i32);
1913 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
1917 SDValue BitsFrom = N->getOperand(0);
1918 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
1920 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
1922 if (OffsetVal == 0) {
1923 // This is already sign / zero extended, so try to fold away extra BFEs.
1924 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
1926 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
1927 if (OpSignBits >= SignBits)
1930 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
1932 // This is a sign_extend_inreg. Replace it to take advantage of existing
1933 // DAG Combines. If not eliminated, we will match back to BFE during
1936 // TODO: The sext_inreg of extended types ends, although we can could
1937 // handle them in a single BFE.
1938 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
1939 DAG.getValueType(SmallVT));
1942 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
1945 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1947 return constantFoldBFE<int32_t>(DAG,
1948 Val->getSExtValue(),
1953 return constantFoldBFE<uint32_t>(DAG,
1954 Val->getZExtValue(),
1959 APInt Demanded = APInt::getBitsSet(32,
1961 OffsetVal + WidthVal);
1963 if ((OffsetVal + WidthVal) >= 32) {
1964 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
1965 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1966 BitsFrom, ShiftVal);
1969 APInt KnownZero, KnownOne;
1970 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1971 !DCI.isBeforeLegalizeOps());
1972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1973 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
1974 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
1975 DCI.CommitTargetLoweringOpt(TLO);
1984 //===----------------------------------------------------------------------===//
1986 //===----------------------------------------------------------------------===//
1988 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1991 const SmallVectorImpl<ISD::InputArg> &Ins,
1992 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1994 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1995 if (Ins[i].ArgVT == Ins[i].VT) {
1996 OrigIns.push_back(Ins[i]);
2001 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2002 // Vector has been split into scalars.
2003 VT = Ins[i].ArgVT.getVectorElementType();
2004 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2005 Ins[i].ArgVT.getVectorElementType() !=
2006 Ins[i].VT.getVectorElementType()) {
2007 // Vector elements have been promoted
2010 // Vector has been spilt into smaller vectors.
2014 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2015 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2016 OrigIns.push_back(Arg);
2020 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2021 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2022 return CFP->isExactlyValue(1.0);
2024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2025 return C->isAllOnesValue();
2030 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2031 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2032 return CFP->getValueAPF().isZero();
2034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2035 return C->isNullValue();
2040 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2041 const TargetRegisterClass *RC,
2042 unsigned Reg, EVT VT) const {
2043 MachineFunction &MF = DAG.getMachineFunction();
2044 MachineRegisterInfo &MRI = MF.getRegInfo();
2045 unsigned VirtualRegister;
2046 if (!MRI.isLiveIn(Reg)) {
2047 VirtualRegister = MRI.createVirtualRegister(RC);
2048 MRI.addLiveIn(Reg, VirtualRegister);
2050 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2052 return DAG.getRegister(VirtualRegister, VT);
2055 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2057 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2059 default: return nullptr;
2061 NODE_NAME_CASE(CALL);
2062 NODE_NAME_CASE(UMUL);
2063 NODE_NAME_CASE(RET_FLAG);
2064 NODE_NAME_CASE(BRANCH_COND);
2067 NODE_NAME_CASE(DWORDADDR)
2068 NODE_NAME_CASE(FRACT)
2069 NODE_NAME_CASE(CLAMP)
2070 NODE_NAME_CASE(FMAX)
2071 NODE_NAME_CASE(SMAX)
2072 NODE_NAME_CASE(UMAX)
2073 NODE_NAME_CASE(FMIN)
2074 NODE_NAME_CASE(SMIN)
2075 NODE_NAME_CASE(UMIN)
2076 NODE_NAME_CASE(URECIP)
2077 NODE_NAME_CASE(DIV_SCALE)
2078 NODE_NAME_CASE(DIV_FMAS)
2079 NODE_NAME_CASE(DIV_FIXUP)
2080 NODE_NAME_CASE(TRIG_PREOP)
2083 NODE_NAME_CASE(RSQ_LEGACY)
2084 NODE_NAME_CASE(RSQ_CLAMPED)
2085 NODE_NAME_CASE(DOT4)
2086 NODE_NAME_CASE(BFE_U32)
2087 NODE_NAME_CASE(BFE_I32)
2090 NODE_NAME_CASE(BREV)
2091 NODE_NAME_CASE(MUL_U24)
2092 NODE_NAME_CASE(MUL_I24)
2093 NODE_NAME_CASE(MAD_U24)
2094 NODE_NAME_CASE(MAD_I24)
2095 NODE_NAME_CASE(EXPORT)
2096 NODE_NAME_CASE(CONST_ADDRESS)
2097 NODE_NAME_CASE(REGISTER_LOAD)
2098 NODE_NAME_CASE(REGISTER_STORE)
2099 NODE_NAME_CASE(LOAD_CONSTANT)
2100 NODE_NAME_CASE(LOAD_INPUT)
2101 NODE_NAME_CASE(SAMPLE)
2102 NODE_NAME_CASE(SAMPLEB)
2103 NODE_NAME_CASE(SAMPLED)
2104 NODE_NAME_CASE(SAMPLEL)
2105 NODE_NAME_CASE(CVT_F32_UBYTE0)
2106 NODE_NAME_CASE(CVT_F32_UBYTE1)
2107 NODE_NAME_CASE(CVT_F32_UBYTE2)
2108 NODE_NAME_CASE(CVT_F32_UBYTE3)
2109 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2110 NODE_NAME_CASE(STORE_MSKOR)
2111 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2115 static void computeKnownBitsForMinMax(const SDValue Op0,
2119 const SelectionDAG &DAG,
2121 APInt Op0Zero, Op0One;
2122 APInt Op1Zero, Op1One;
2123 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2124 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2126 KnownZero = Op0Zero & Op1Zero;
2127 KnownOne = Op0One & Op1One;
2130 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2134 const SelectionDAG &DAG,
2135 unsigned Depth) const {
2137 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2141 unsigned Opc = Op.getOpcode();
2146 case ISD::INTRINSIC_WO_CHAIN: {
2147 // FIXME: The intrinsic should just use the node.
2148 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2149 case AMDGPUIntrinsic::AMDGPU_imax:
2150 case AMDGPUIntrinsic::AMDGPU_umax:
2151 case AMDGPUIntrinsic::AMDGPU_imin:
2152 case AMDGPUIntrinsic::AMDGPU_umin:
2153 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2154 KnownZero, KnownOne, DAG, Depth);
2162 case AMDGPUISD::SMAX:
2163 case AMDGPUISD::UMAX:
2164 case AMDGPUISD::SMIN:
2165 case AMDGPUISD::UMIN:
2166 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2167 KnownZero, KnownOne, DAG, Depth);
2170 case AMDGPUISD::BFE_I32:
2171 case AMDGPUISD::BFE_U32: {
2172 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2176 unsigned BitWidth = 32;
2177 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2179 KnownZero = APInt::getAllOnesValue(BitWidth);
2180 KnownOne = APInt::getNullValue(BitWidth);
2184 // FIXME: This could do a lot more. If offset is 0, should be the same as
2185 // sign_extend_inreg implementation, but that involves duplicating it.
2186 if (Opc == AMDGPUISD::BFE_I32)
2187 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2189 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2196 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2198 const SelectionDAG &DAG,
2199 unsigned Depth) const {
2200 switch (Op.getOpcode()) {
2201 case AMDGPUISD::BFE_I32: {
2202 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2206 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2207 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2208 if (!Offset || !Offset->isNullValue())
2211 // TODO: Could probably figure something out with non-0 offsets.
2212 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2213 return std::max(SignBits, Op0SignBits);
2216 case AMDGPUISD::BFE_U32: {
2217 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2218 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;