Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://problem...
[oota-llvm.git] / lib / CodeGen / SelectionDAG / ScheduleDAGRRList.cpp
2011-12-07 Eli FriedmanMake sure we correctly set LiveRegGens when a call...
2011-12-07 Eli FriedmanFix an assertion in the scheduler. PR11386. No testca...
2011-12-07 Nick LewyckyThese global variables aren't thread-safe, STATISTIC...
2011-11-16 Owen AndersonRename MVT::untyped to MVT::Untyped to match similar...
2011-11-15 Pete CooperAdded custom lowering for load->dec->store sequence...
2011-11-10 Evan ChengUse a bigger hammer to fix PR11314 by disabling the...
2011-11-09 Duncan SandsSpeculatively revert commit 144124 (djg) in the hope...
2011-11-08 Dan GohmanAdd a hack to the scheduler to disable pseudo-two-addre...
2011-11-03 Dan GohmanReapply r143206, with fixes. Disallow physical register...
2011-10-29 Dan GohmanRevert r143206, as there are still some failing tests.
2011-10-28 Dan GohmanReapply r143177 and r143179 (reverting r143188), with...
2011-10-28 Duncan SandsSpeculatively disable Dan's commits 143177 and 143179...
2011-10-28 Dan GohmanEliminate LegalizeOps' LegalizedNodes map and have...
2011-10-24 Dan GohmanChange this overloaded use of Sched::Latency to be...
2011-10-21 Chandler CarruthRemove a now dead function, fixing -Wunused-function...
2011-10-20 Dan GohmanDelete the list-tdrr scheduler. Top-down schedulers...
2011-09-01 Andrew TrickPreRA scheduler should avoid cloning compares.
2011-06-28 Evan Cheng- Rename TargetInstrDesc, TargetOperandInfo to MCInstrD...
2011-06-27 Evan ChengMore refactoring. Move getRegClass from TargetOperandIn...
2011-06-27 Andrew Trickpre-RA-sched: Cleanup register pressure tracking.
2011-06-27 Jakob Stoklund OlesenDistinguish early clobber output operands from clobbere...
2011-06-21 Owen AndersonFix some trailing issues from my introduction of MVT...
2011-06-18 Benjamin KramerRemove unused but set variables.
2011-06-15 Owen AndersonAdd a new MVT::untyped. This will be used in future...
2011-06-15 Andrew TrickAdded -stress-sched flag in the Asserts build.
2011-06-08 Andrew TrickRemove a temporary test case probe in CheckForLiveRegDef.
2011-06-07 Andrew TrickFix a merge bug in preRAsched for handling physreg...
2011-04-26 Evan ChengBe careful about scheduling nodes above previous calls...
2011-04-26 Evan ChengFix typo
2011-04-14 Andrew TrickIn the pre-RA scheduler, maintain cmp+br proximity.
2011-04-13 Andrew TrickRecommit r129383. PreRA scheduler heuristic fixes:...
2011-04-12 Andrew TrickRevert 129383. It causes some targets to hit a schedule...
2011-04-12 Andrew TrickPreRA scheduler heuristic fixes: VRegCycle, TokenFactor...
2011-04-07 Andrew TrickAdded a check in the preRA scheduler for potential...
2011-03-25 Andrew TrickFix for -pre-RA-sched=source.
2011-03-23 Andrew TrickEnsure that def-side physreg copies are scheduled above...
2011-03-23 Andrew Trickwhitespace
2011-03-21 Eric ChristopherGrammar-o.
2011-03-10 Evan ChengRe-commit 127368 and 127371. They are exonerated.
2011-03-09 Evan ChengRevert 127368 and 127371 for now.
2011-03-09 Evan ChengChange the definition of TargetRegisterInfo::getCrossCo...
2011-03-09 Benjamin KramerFix typo, make helper static.
2011-03-08 Eric ChristopherFix some latent bugs if the nodes are unschedulable...
2011-03-08 Andrew TrickFurther improvements to pre-RA-sched=list-ilp.
2011-03-07 Cameron ZwarichMove getRegPressureLimit() from TargetLoweringInfo...
2011-03-06 Eric ChristopherTypo.
2011-03-06 Andrew TrickDisable a couple of experimental heuristics to get...
2011-03-05 Andrew TrickBe explicit with abs(). Visual Studio workaround.
2011-03-05 Andrew TrickMissing comment.
2011-03-05 Andrew TrickIncreased the register pressure limit on x86_64 from...
2011-03-04 Andrew TrickMinor pre-RA-sched fixes and cleanup.
2011-02-04 Andrew TrickIntroducing a new method of tracking register pressure...
2011-01-27 Andrew TrickRemove a temporary workaround for a lencod miscompile...
2011-01-24 Andrew TrickTemporarily workaround JM/lencod miscompile (SIGSEGV).
2011-01-21 Andrew TrickEnable support for precise scheduling of the instructio...
2011-01-21 Andrew TrickConvert -enable-sched-cycles and -enable-sched-hazard...
2011-01-20 Andrew TrickSelection DAG scheduler register pressure heuristic...
2011-01-14 Andrew TrickSupport for precise scheduling of the instruction selec...
2010-12-24 Andrew TrickMinor cleanup related to my latest scheduler changes.
2010-12-24 Andrew TrickFix a few cases where the scheduler is not checking...
2010-12-24 Andrew TrickVarious bits of framework needed for precise machine...
2010-12-23 Chris Lattnerflags -> glue for selectiondag
2010-12-23 Andrew TrickReorganize ListScheduleBottomUp in preparation for...
2010-12-23 Andrew TrickConverted LiveRegCycles to LiveRegGens. It's easier...
2010-12-23 Andrew TrickIn CheckForLiveRegDef use TRI->getOverlaps.
2010-12-23 Andrew TrickFixes PR8823: add-with-overflow-128.ll
2010-12-21 Andrew TrickIn DelayForLiveRegsBottomUp, handle instructions that...
2010-12-21 Andrew Trickwhitespace
2010-12-21 Chris Lattnerrename MVT::Flag to MVT::Glue. "Flag" is a terrible...
2010-12-20 Chris LattnerFix a bug in the scheduler's handling of "unspillable...
2010-12-20 Chris Lattnerthe result of CheckForLiveRegDef is dead, remove it.
2010-11-03 Evan ChengTwo sets of changes. Sorry they are intermingled.
2010-10-29 Evan ChengAvoiding overly aggressive latency scheduling. If the...
2010-07-26 Evan ChengThe "excess register pressure" returned by HighRegPress...
2010-07-26 Duncan SandsPacify gcc-4.5 which wrongly thinks that RExcess (passe...
2010-07-25 Evan ChengAdd comments.
2010-07-25 Bob WilsonFix crashes when scheduling a CopyToReg node -- getMach...
2010-07-24 Evan ChengAdd an ILP scheduler. This is a register pressure aware...
2010-07-23 Evan Cheng- Allow target to specify when is register pressure...
2010-07-22 Evan ChengRe-apply r109079 with fix.
2010-07-22 Owen AndersonRevert r109079, which broke a lot of CodeGen tests.
2010-07-22 Evan ChengInitialize RegLimit only when register pressure is...
2010-07-21 Evan ChengMore register pressure aware scheduling work.
2010-07-21 Evan ChengTeach bottom up pre-ra scheduler to track register...
2010-06-29 Rafael EspindolaAdd a VT argument to getMinimalPhysRegClass and replace...
2010-05-30 Oscar FuentesUse `llvm::next' instead of `next' to make VC++ 2010...
2010-05-28 Evan ChengFix some latency computation bugs: if the use is not...
2010-05-26 Dan GohmanEliminate the use of PriorityQueue and just use a std...
2010-05-26 Dan GohmanDelete an unused function.
2010-05-26 Dan GohmanChange push_all to a non-virtual function and implement...
2010-05-21 Evan ChengRename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
2010-05-20 Evan ChengAllow targets more controls on what nodes are scheduled...
2010-05-20 Evan ChengAdd a hybrid bottom up scheduler that reduce register...
2010-04-07 Chris LattnerThree changes:
2010-02-09 Chris Lattnermove target-independent opcodes out of TargetInstrInfo
2010-02-05 Evan ChengWhen the scheduler unfold a load folding instruction...
2010-01-23 Bill WendlingRemove the '-disable-scheduling' flag and replace it...
2010-01-06 Bill WendlingThe previous code could potentially cause a cycle....
2010-01-06 Bill WendlingOnly check the ordering if there is an ordering for...
2010-01-05 Bill WendlingAdd a semi-primitive form of scheduling via the "SDNode...
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