Temporarily workaround JM/lencod miscompile (SIGSEGV).

rdar://problem/8893967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124137 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index ad835806a4e79ad23f26b4ced97137b1d9fa71ea..87739c0391473ecea9744d04cefb863be8de7fd2 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1645,11 +1645,13 @@ bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
     // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
     // counts data deps.  To be more precise, we could maintain a
     // NumDataSuccsLeft count.
+    /* FIXME: exposing a downstream bug, JM/lencode miscompile
     if (PredSU->NumSuccsLeft != PredSU->Succs.size()) {
       DEBUG(dbgs() << "  SU(" << PredSU->NodeNum << ") live across SU("
             << SU->NodeNum << ")\n");
       continue;
     }
+    */
     const SDNode *PN = PredSU->getNode();
     if (!PN->isMachineOpcode()) {
       if (PN->getOpcode() == ISD::CopyFromReg) {