The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92810 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 4d51f0c13e8cfc3b98c0b74d6ae9ed5c9dcc9309..1ad7919962b3048a04747ad08d5d4e15046b4913 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1129,8 +1129,8 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
 
   // Prefer an ordering where the lower the non-zero order number, the higher
   // the preference.
-  if (LOrder && ROrder && LOrder != ROrder)
-    return LOrder < ROrder;
+  if ((LOrder || ROrder) && LOrder != ROrder)
+    return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
 
   unsigned LPriority = SPQ->getNodePriority(left);
   unsigned RPriority = SPQ->getNodePriority(right);