1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "pre-RA-sched"
19 #include "ScheduleDAGSDNodes.h"
20 #include "llvm/InlineAsm.h"
21 #include "llvm/CodeGen/SchedulerRegistry.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/ADT/SmallSet.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 STATISTIC(NumBacktracks, "Number of times scheduler backtracked");
39 STATISTIC(NumUnfolds, "Number of nodes unfolded");
40 STATISTIC(NumDups, "Number of duplicated nodes");
41 STATISTIC(NumPRCopies, "Number of physical register copies");
43 static RegisterScheduler
44 burrListDAGScheduler("list-burr",
45 "Bottom-up register reduction list scheduling",
46 createBURRListDAGScheduler);
47 static RegisterScheduler
48 tdrListrDAGScheduler("list-tdrr",
49 "Top-down register reduction list scheduling",
50 createTDRRListDAGScheduler);
51 static RegisterScheduler
52 sourceListDAGScheduler("source",
53 "Similar to list-burr but schedules in source "
54 "order when possible",
55 createSourceListDAGScheduler);
57 static RegisterScheduler
58 hybridListDAGScheduler("list-hybrid",
59 "Bottom-up register pressure aware list scheduling "
60 "which tries to balance latency and register pressure",
61 createHybridListDAGScheduler);
63 static RegisterScheduler
64 ILPListDAGScheduler("list-ilp",
65 "Bottom-up register pressure aware list scheduling "
66 "which tries to balance ILP and register pressure",
67 createILPListDAGScheduler);
69 static cl::opt<bool> DisableSchedCycles(
70 "disable-sched-cycles", cl::Hidden, cl::init(false),
71 cl::desc("Disable cycle-level precision during preRA scheduling"));
73 // Temporary sched=list-ilp flags until the heuristics are robust.
74 // Some options are also available under sched=list-hybrid.
75 static cl::opt<bool> DisableSchedRegPressure(
76 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
77 cl::desc("Disable regpressure priority in sched=list-ilp"));
78 static cl::opt<bool> DisableSchedLiveUses(
79 "disable-sched-live-uses", cl::Hidden, cl::init(true),
80 cl::desc("Disable live use priority in sched=list-ilp"));
81 static cl::opt<bool> DisableSchedVRegCycle(
82 "disable-sched-vrcycle", cl::Hidden, cl::init(false),
83 cl::desc("Disable virtual register cycle interference checks"));
84 static cl::opt<bool> DisableSchedPhysRegJoin(
85 "disable-sched-physreg-join", cl::Hidden, cl::init(false),
86 cl::desc("Disable physreg def-use affinity"));
87 static cl::opt<bool> DisableSchedStalls(
88 "disable-sched-stalls", cl::Hidden, cl::init(true),
89 cl::desc("Disable no-stall priority in sched=list-ilp"));
90 static cl::opt<bool> DisableSchedCriticalPath(
91 "disable-sched-critical-path", cl::Hidden, cl::init(false),
92 cl::desc("Disable critical path priority in sched=list-ilp"));
93 static cl::opt<bool> DisableSchedHeight(
94 "disable-sched-height", cl::Hidden, cl::init(false),
95 cl::desc("Disable scheduled-height priority in sched=list-ilp"));
97 static cl::opt<int> MaxReorderWindow(
98 "max-sched-reorder", cl::Hidden, cl::init(6),
99 cl::desc("Number of instructions to allow ahead of the critical path "
100 "in sched=list-ilp"));
102 static cl::opt<unsigned> AvgIPC(
103 "sched-avg-ipc", cl::Hidden, cl::init(1),
104 cl::desc("Average inst/cycle whan no target itinerary exists."));
108 // For sched=list-ilp, Count the number of times each factor comes into play.
109 enum { FactPressureDiff, FactRegUses, FactStall, FactHeight, FactDepth,
110 FactStatic, FactOther, NumFactors };
112 static const char *FactorName[NumFactors] =
113 {"PressureDiff", "RegUses", "Stall", "Height", "Depth","Static", "Other"};
114 static int FactorCount[NumFactors];
118 //===----------------------------------------------------------------------===//
119 /// ScheduleDAGRRList - The actual register reduction list scheduler
120 /// implementation. This supports both top-down and bottom-up scheduling.
122 class ScheduleDAGRRList : public ScheduleDAGSDNodes {
124 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
128 /// NeedLatency - True if the scheduler will make use of latency information.
132 /// AvailableQueue - The priority queue to use for the available SUnits.
133 SchedulingPriorityQueue *AvailableQueue;
135 /// PendingQueue - This contains all of the instructions whose operands have
136 /// been issued, but their results are not ready yet (due to the latency of
137 /// the operation). Once the operands becomes available, the instruction is
138 /// added to the AvailableQueue.
139 std::vector<SUnit*> PendingQueue;
141 /// HazardRec - The hazard recognizer to use.
142 ScheduleHazardRecognizer *HazardRec;
144 /// CurCycle - The current scheduler state corresponds to this cycle.
147 /// MinAvailableCycle - Cycle of the soonest available instruction.
148 unsigned MinAvailableCycle;
150 /// IssueCount - Count instructions issued in this cycle
151 /// Currently valid only for bottom-up scheduling.
154 /// LiveRegDefs - A set of physical registers and their definition
155 /// that are "live". These nodes must be scheduled before any other nodes that
156 /// modifies the registers can be scheduled.
157 unsigned NumLiveRegs;
158 std::vector<SUnit*> LiveRegDefs;
159 std::vector<SUnit*> LiveRegGens;
161 /// Topo - A topological ordering for SUnits which permits fast IsReachable
162 /// and similar queries.
163 ScheduleDAGTopologicalSort Topo;
166 ScheduleDAGRRList(MachineFunction &mf, bool needlatency,
167 SchedulingPriorityQueue *availqueue,
168 CodeGenOpt::Level OptLevel)
169 : ScheduleDAGSDNodes(mf), isBottomUp(availqueue->isBottomUp()),
170 NeedLatency(needlatency), AvailableQueue(availqueue), CurCycle(0),
173 const TargetMachine &tm = mf.getTarget();
174 if (DisableSchedCycles || !NeedLatency)
175 HazardRec = new ScheduleHazardRecognizer();
177 HazardRec = tm.getInstrInfo()->CreateTargetHazardRecognizer(&tm, this);
180 ~ScheduleDAGRRList() {
182 delete AvailableQueue;
187 ScheduleHazardRecognizer *getHazardRec() { return HazardRec; }
189 /// IsReachable - Checks if SU is reachable from TargetSU.
190 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
191 return Topo.IsReachable(SU, TargetSU);
194 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
196 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
197 return Topo.WillCreateCycle(SU, TargetSU);
200 /// AddPred - adds a predecessor edge to SUnit SU.
201 /// This returns true if this is a new predecessor.
202 /// Updates the topological ordering if required.
203 void AddPred(SUnit *SU, const SDep &D) {
204 Topo.AddPred(SU, D.getSUnit());
208 /// RemovePred - removes a predecessor edge from SUnit SU.
209 /// This returns true if an edge was removed.
210 /// Updates the topological ordering if required.
211 void RemovePred(SUnit *SU, const SDep &D) {
212 Topo.RemovePred(SU, D.getSUnit());
217 bool isReady(SUnit *SU) {
218 return DisableSchedCycles || !AvailableQueue->hasReadyFilter() ||
219 AvailableQueue->isReady(SU);
222 void ReleasePred(SUnit *SU, const SDep *PredEdge);
223 void ReleasePredecessors(SUnit *SU);
224 void ReleaseSucc(SUnit *SU, const SDep *SuccEdge);
225 void ReleaseSuccessors(SUnit *SU);
226 void ReleasePending();
227 void AdvanceToCycle(unsigned NextCycle);
228 void AdvancePastStalls(SUnit *SU);
229 void EmitNode(SUnit *SU);
230 void ScheduleNodeBottomUp(SUnit*);
231 void CapturePred(SDep *PredEdge);
232 void UnscheduleNodeBottomUp(SUnit*);
233 void RestoreHazardCheckerBottomUp();
234 void BacktrackBottomUp(SUnit*, SUnit*);
235 SUnit *CopyAndMoveSuccessors(SUnit*);
236 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
237 const TargetRegisterClass*,
238 const TargetRegisterClass*,
239 SmallVector<SUnit*, 2>&);
240 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
242 SUnit *PickNodeToScheduleBottomUp();
243 void ListScheduleBottomUp();
245 void ScheduleNodeTopDown(SUnit*);
246 void ListScheduleTopDown();
249 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
250 /// Updates the topological ordering if required.
251 SUnit *CreateNewSUnit(SDNode *N) {
252 unsigned NumSUnits = SUnits.size();
253 SUnit *NewNode = NewSUnit(N);
254 // Update the topological ordering.
255 if (NewNode->NodeNum >= NumSUnits)
256 Topo.InitDAGTopologicalSorting();
260 /// CreateClone - Creates a new SUnit from an existing one.
261 /// Updates the topological ordering if required.
262 SUnit *CreateClone(SUnit *N) {
263 unsigned NumSUnits = SUnits.size();
264 SUnit *NewNode = Clone(N);
265 // Update the topological ordering.
266 if (NewNode->NodeNum >= NumSUnits)
267 Topo.InitDAGTopologicalSorting();
271 /// ForceUnitLatencies - Register-pressure-reducing scheduling doesn't
272 /// need actual latency information but the hybrid scheduler does.
273 bool ForceUnitLatencies() const {
277 } // end anonymous namespace
280 /// Schedule - Schedule the DAG using list scheduling.
281 void ScheduleDAGRRList::Schedule() {
283 << "********** List Scheduling BB#" << BB->getNumber()
284 << " '" << BB->getName() << "' **********\n");
286 for (int i = 0; i < NumFactors; ++i) {
293 MinAvailableCycle = DisableSchedCycles ? 0 : UINT_MAX;
295 LiveRegDefs.resize(TRI->getNumRegs(), NULL);
296 LiveRegGens.resize(TRI->getNumRegs(), NULL);
298 // Build the scheduling graph.
299 BuildSchedGraph(NULL);
301 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
302 SUnits[su].dumpAll(this));
303 Topo.InitDAGTopologicalSorting();
305 AvailableQueue->initNodes(SUnits);
309 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
311 ListScheduleBottomUp();
313 ListScheduleTopDown();
316 for (int i = 0; i < NumFactors; ++i) {
317 DEBUG(dbgs() << FactorName[i] << "\t" << FactorCount[i] << "\n");
320 AvailableQueue->releaseState();
323 //===----------------------------------------------------------------------===//
324 // Bottom-Up Scheduling
325 //===----------------------------------------------------------------------===//
327 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
328 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
329 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
330 SUnit *PredSU = PredEdge->getSUnit();
333 if (PredSU->NumSuccsLeft == 0) {
334 dbgs() << "*** Scheduling failed! ***\n";
336 dbgs() << " has been released too many times!\n";
340 --PredSU->NumSuccsLeft;
342 if (!ForceUnitLatencies()) {
343 // Updating predecessor's height. This is now the cycle when the
344 // predecessor can be scheduled without causing a pipeline stall.
345 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
348 // If all the node's successors are scheduled, this node is ready
349 // to be scheduled. Ignore the special EntrySU node.
350 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
351 PredSU->isAvailable = true;
353 unsigned Height = PredSU->getHeight();
354 if (Height < MinAvailableCycle)
355 MinAvailableCycle = Height;
357 if (isReady(PredSU)) {
358 AvailableQueue->push(PredSU);
360 // CapturePred and others may have left the node in the pending queue, avoid
362 else if (!PredSU->isPending) {
363 PredSU->isPending = true;
364 PendingQueue.push_back(PredSU);
369 /// Call ReleasePred for each predecessor, then update register live def/gen.
370 /// Always update LiveRegDefs for a register dependence even if the current SU
371 /// also defines the register. This effectively create one large live range
372 /// across a sequence of two-address node. This is important because the
373 /// entire chain must be scheduled together. Example:
376 /// flags = (2) addc flags
377 /// flags = (1) addc flags
381 /// LiveRegDefs[flags] = 3
382 /// LiveRegGens[flags] = 1
384 /// If (2) addc is unscheduled, then (1) addc must also be unscheduled to avoid
385 /// interference on flags.
386 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
387 // Bottom up: release predecessors
388 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
390 ReleasePred(SU, &*I);
391 if (I->isAssignedRegDep()) {
392 // This is a physical register dependency and it's impossible or
393 // expensive to copy the register. Make sure nothing that can
394 // clobber the register is scheduled between the predecessor and
396 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
397 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
398 "interference on register dependence");
399 LiveRegDefs[I->getReg()] = I->getSUnit();
400 if (!LiveRegGens[I->getReg()]) {
402 LiveRegGens[I->getReg()] = SU;
408 /// Check to see if any of the pending instructions are ready to issue. If
409 /// so, add them to the available queue.
410 void ScheduleDAGRRList::ReleasePending() {
411 if (DisableSchedCycles) {
412 assert(PendingQueue.empty() && "pending instrs not allowed in this mode");
416 // If the available queue is empty, it is safe to reset MinAvailableCycle.
417 if (AvailableQueue->empty())
418 MinAvailableCycle = UINT_MAX;
420 // Check to see if any of the pending instructions are ready to issue. If
421 // so, add them to the available queue.
422 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
423 unsigned ReadyCycle =
424 isBottomUp ? PendingQueue[i]->getHeight() : PendingQueue[i]->getDepth();
425 if (ReadyCycle < MinAvailableCycle)
426 MinAvailableCycle = ReadyCycle;
428 if (PendingQueue[i]->isAvailable) {
429 if (!isReady(PendingQueue[i]))
431 AvailableQueue->push(PendingQueue[i]);
433 PendingQueue[i]->isPending = false;
434 PendingQueue[i] = PendingQueue.back();
435 PendingQueue.pop_back();
440 /// Move the scheduler state forward by the specified number of Cycles.
441 void ScheduleDAGRRList::AdvanceToCycle(unsigned NextCycle) {
442 if (NextCycle <= CurCycle)
446 AvailableQueue->setCurCycle(NextCycle);
447 if (!HazardRec->isEnabled()) {
448 // Bypass lots of virtual calls in case of long latency.
449 CurCycle = NextCycle;
452 for (; CurCycle != NextCycle; ++CurCycle) {
454 HazardRec->RecedeCycle();
456 HazardRec->AdvanceCycle();
459 // FIXME: Instead of visiting the pending Q each time, set a dirty flag on the
460 // available Q to release pending nodes at least once before popping.
464 /// Move the scheduler state forward until the specified node's dependents are
465 /// ready and can be scheduled with no resource conflicts.
466 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
467 if (DisableSchedCycles)
470 // FIXME: Nodes such as CopyFromReg probably should not advance the current
471 // cycle. Otherwise, we can wrongly mask real stalls. If the non-machine node
472 // has predecessors the cycle will be advanced when they are scheduled.
473 // But given the crude nature of modeling latency though such nodes, we
474 // currently need to treat these nodes like real instructions.
475 // if (!SU->getNode() || !SU->getNode()->isMachineOpcode()) return;
477 unsigned ReadyCycle = isBottomUp ? SU->getHeight() : SU->getDepth();
479 // Bump CurCycle to account for latency. We assume the latency of other
480 // available instructions may be hidden by the stall (not a full pipe stall).
481 // This updates the hazard recognizer's cycle before reserving resources for
483 AdvanceToCycle(ReadyCycle);
485 // Calls are scheduled in their preceding cycle, so don't conflict with
486 // hazards from instructions after the call. EmitNode will reset the
487 // scoreboard state before emitting the call.
488 if (isBottomUp && SU->isCall)
491 // FIXME: For resource conflicts in very long non-pipelined stages, we
492 // should probably skip ahead here to avoid useless scoreboard checks.
495 ScheduleHazardRecognizer::HazardType HT =
496 HazardRec->getHazardType(SU, isBottomUp ? -Stalls : Stalls);
498 if (HT == ScheduleHazardRecognizer::NoHazard)
503 AdvanceToCycle(CurCycle + Stalls);
506 /// Record this SUnit in the HazardRecognizer.
507 /// Does not update CurCycle.
508 void ScheduleDAGRRList::EmitNode(SUnit *SU) {
509 if (!HazardRec->isEnabled())
512 // Check for phys reg copy.
516 switch (SU->getNode()->getOpcode()) {
518 assert(SU->getNode()->isMachineOpcode() &&
519 "This target-independent node should not be scheduled.");
521 case ISD::MERGE_VALUES:
522 case ISD::TokenFactor:
524 case ISD::CopyFromReg:
526 // Noops don't affect the scoreboard state. Copies are likely to be
530 // For inline asm, clear the pipeline state.
534 if (isBottomUp && SU->isCall) {
535 // Calls are scheduled with their preceding instructions. For bottom-up
536 // scheduling, clear the pipeline state before emitting.
540 HazardRec->EmitInstruction(SU);
542 if (!isBottomUp && SU->isCall) {
547 static void resetVRegCycle(SUnit *SU);
549 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
550 /// count of its predecessors. If a predecessor pending count is zero, add it to
551 /// the Available queue.
552 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
553 DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: ");
554 DEBUG(SU->dump(this));
557 if (CurCycle < SU->getHeight())
558 DEBUG(dbgs() << " Height [" << SU->getHeight()
559 << "] pipeline stall!\n");
562 // FIXME: Do not modify node height. It may interfere with
563 // backtracking. Instead add a "ready cycle" to SUnit. Before scheduling the
564 // node its ready cycle can aid heuristics, and after scheduling it can
565 // indicate the scheduled cycle.
566 SU->setHeightToAtLeast(CurCycle);
568 // Reserve resources for the scheduled intruction.
571 Sequence.push_back(SU);
573 AvailableQueue->ScheduledNode(SU);
575 // If HazardRec is disabled, and each inst counts as one cycle, then
576 // advance CurCycle before ReleasePredecessors to avoid useless pushes to
577 // PendingQueue for schedulers that implement HasReadyFilter.
578 if (!HazardRec->isEnabled() && AvgIPC < 2)
579 AdvanceToCycle(CurCycle + 1);
581 // Update liveness of predecessors before successors to avoid treating a
582 // two-address node as a live range def.
583 ReleasePredecessors(SU);
585 // Release all the implicit physical register defs that are live.
586 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
588 // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
589 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
590 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
592 LiveRegDefs[I->getReg()] = NULL;
593 LiveRegGens[I->getReg()] = NULL;
599 SU->isScheduled = true;
601 // Conditions under which the scheduler should eagerly advance the cycle:
602 // (1) No available instructions
603 // (2) All pipelines full, so available instructions must have hazards.
605 // If HazardRec is disabled, the cycle was pre-advanced before calling
606 // ReleasePredecessors. In that case, IssueCount should remain 0.
608 // Check AvailableQueue after ReleasePredecessors in case of zero latency.
609 if (HazardRec->isEnabled() || AvgIPC > 1) {
610 if (SU->getNode() && SU->getNode()->isMachineOpcode())
612 if ((HazardRec->isEnabled() && HazardRec->atIssueLimit())
613 || (!HazardRec->isEnabled() && IssueCount == AvgIPC))
614 AdvanceToCycle(CurCycle + 1);
618 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
619 /// unscheduled, incrcease the succ left count of its predecessors. Remove
620 /// them from AvailableQueue if necessary.
621 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
622 SUnit *PredSU = PredEdge->getSUnit();
623 if (PredSU->isAvailable) {
624 PredSU->isAvailable = false;
625 if (!PredSU->isPending)
626 AvailableQueue->remove(PredSU);
629 assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
630 ++PredSU->NumSuccsLeft;
633 /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
634 /// its predecessor states to reflect the change.
635 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
636 DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: ");
637 DEBUG(SU->dump(this));
639 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
642 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){
643 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
644 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
645 "Physical register dependency violated?");
647 LiveRegDefs[I->getReg()] = NULL;
648 LiveRegGens[I->getReg()] = NULL;
652 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
654 if (I->isAssignedRegDep()) {
655 // This becomes the nearest def. Note that an earlier def may still be
656 // pending if this is a two-address node.
657 LiveRegDefs[I->getReg()] = SU;
658 if (!LiveRegDefs[I->getReg()]) {
661 if (LiveRegGens[I->getReg()] == NULL ||
662 I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
663 LiveRegGens[I->getReg()] = I->getSUnit();
666 if (SU->getHeight() < MinAvailableCycle)
667 MinAvailableCycle = SU->getHeight();
669 SU->setHeightDirty();
670 SU->isScheduled = false;
671 SU->isAvailable = true;
672 if (!DisableSchedCycles && AvailableQueue->hasReadyFilter()) {
673 // Don't make available until backtracking is complete.
674 SU->isPending = true;
675 PendingQueue.push_back(SU);
678 AvailableQueue->push(SU);
680 AvailableQueue->UnscheduledNode(SU);
683 /// After backtracking, the hazard checker needs to be restored to a state
684 /// corresponding the the current cycle.
685 void ScheduleDAGRRList::RestoreHazardCheckerBottomUp() {
688 unsigned LookAhead = std::min((unsigned)Sequence.size(),
689 HazardRec->getMaxLookAhead());
693 std::vector<SUnit*>::const_iterator I = (Sequence.end() - LookAhead);
694 unsigned HazardCycle = (*I)->getHeight();
695 for (std::vector<SUnit*>::const_iterator E = Sequence.end(); I != E; ++I) {
697 for (; SU->getHeight() > HazardCycle; ++HazardCycle) {
698 HazardRec->RecedeCycle();
704 /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
705 /// BTCycle in order to schedule a specific node.
706 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
707 SUnit *OldSU = Sequence.back();
710 if (SU->isSucc(OldSU))
711 // Don't try to remove SU from AvailableQueue.
712 SU->isAvailable = false;
713 // FIXME: use ready cycle instead of height
714 CurCycle = OldSU->getHeight();
715 UnscheduleNodeBottomUp(OldSU);
716 AvailableQueue->setCurCycle(CurCycle);
719 OldSU = Sequence.back();
722 assert(!SU->isSucc(OldSU) && "Something is wrong!");
724 RestoreHazardCheckerBottomUp();
731 static bool isOperandOf(const SUnit *SU, SDNode *N) {
732 for (const SDNode *SUNode = SU->getNode(); SUNode;
733 SUNode = SUNode->getGluedNode()) {
734 if (SUNode->isOperandOf(N))
740 /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
741 /// successors to the newly created node.
742 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
743 SDNode *N = SU->getNode();
747 if (SU->getNode()->getGluedNode())
751 bool TryUnfold = false;
752 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
753 EVT VT = N->getValueType(i);
756 else if (VT == MVT::Other)
759 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
760 const SDValue &Op = N->getOperand(i);
761 EVT VT = Op.getNode()->getValueType(Op.getResNo());
767 SmallVector<SDNode*, 2> NewNodes;
768 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
771 DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
772 assert(NewNodes.size() == 2 && "Expected a load folding node!");
775 SDNode *LoadNode = NewNodes[0];
776 unsigned NumVals = N->getNumValues();
777 unsigned OldNumVals = SU->getNode()->getNumValues();
778 for (unsigned i = 0; i != NumVals; ++i)
779 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
780 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
781 SDValue(LoadNode, 1));
783 // LoadNode may already exist. This can happen when there is another
784 // load from the same location and producing the same type of value
785 // but it has different alignment or volatileness.
786 bool isNewLoad = true;
788 if (LoadNode->getNodeId() != -1) {
789 LoadSU = &SUnits[LoadNode->getNodeId()];
792 LoadSU = CreateNewSUnit(LoadNode);
793 LoadNode->setNodeId(LoadSU->NodeNum);
795 InitNumRegDefsLeft(LoadSU);
796 ComputeLatency(LoadSU);
799 SUnit *NewSU = CreateNewSUnit(N);
800 assert(N->getNodeId() == -1 && "Node already inserted!");
801 N->setNodeId(NewSU->NodeNum);
803 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
804 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
805 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
806 NewSU->isTwoAddress = true;
810 if (TID.isCommutable())
811 NewSU->isCommutable = true;
813 InitNumRegDefsLeft(NewSU);
814 ComputeLatency(NewSU);
816 // Record all the edges to and from the old SU, by category.
817 SmallVector<SDep, 4> ChainPreds;
818 SmallVector<SDep, 4> ChainSuccs;
819 SmallVector<SDep, 4> LoadPreds;
820 SmallVector<SDep, 4> NodePreds;
821 SmallVector<SDep, 4> NodeSuccs;
822 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
825 ChainPreds.push_back(*I);
826 else if (isOperandOf(I->getSUnit(), LoadNode))
827 LoadPreds.push_back(*I);
829 NodePreds.push_back(*I);
831 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
834 ChainSuccs.push_back(*I);
836 NodeSuccs.push_back(*I);
839 // Now assign edges to the newly-created nodes.
840 for (unsigned i = 0, e = ChainPreds.size(); i != e; ++i) {
841 const SDep &Pred = ChainPreds[i];
842 RemovePred(SU, Pred);
844 AddPred(LoadSU, Pred);
846 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
847 const SDep &Pred = LoadPreds[i];
848 RemovePred(SU, Pred);
850 AddPred(LoadSU, Pred);
852 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
853 const SDep &Pred = NodePreds[i];
854 RemovePred(SU, Pred);
855 AddPred(NewSU, Pred);
857 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
858 SDep D = NodeSuccs[i];
859 SUnit *SuccDep = D.getSUnit();
861 RemovePred(SuccDep, D);
864 // Balance register pressure.
865 if (AvailableQueue->tracksRegPressure() && SuccDep->isScheduled
866 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0)
867 --NewSU->NumRegDefsLeft;
869 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
870 SDep D = ChainSuccs[i];
871 SUnit *SuccDep = D.getSUnit();
873 RemovePred(SuccDep, D);
880 // Add a data dependency to reflect that NewSU reads the value defined
882 AddPred(NewSU, SDep(LoadSU, SDep::Data, LoadSU->Latency));
885 AvailableQueue->addNode(LoadSU);
886 AvailableQueue->addNode(NewSU);
890 if (NewSU->NumSuccsLeft == 0) {
891 NewSU->isAvailable = true;
897 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n");
898 NewSU = CreateClone(SU);
900 // New SUnit has the exact same predecessors.
901 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
903 if (!I->isArtificial())
906 // Only copy scheduled successors. Cut them from old node's successor
907 // list and move them over.
908 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
909 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
911 if (I->isArtificial())
913 SUnit *SuccSU = I->getSUnit();
914 if (SuccSU->isScheduled) {
919 DelDeps.push_back(std::make_pair(SuccSU, D));
922 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
923 RemovePred(DelDeps[i].first, DelDeps[i].second);
925 AvailableQueue->updateNode(SU);
926 AvailableQueue->addNode(NewSU);
932 /// InsertCopiesAndMoveSuccs - Insert register copies and move all
933 /// scheduled successors of the given SUnit to the last copy.
934 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
935 const TargetRegisterClass *DestRC,
936 const TargetRegisterClass *SrcRC,
937 SmallVector<SUnit*, 2> &Copies) {
938 SUnit *CopyFromSU = CreateNewSUnit(NULL);
939 CopyFromSU->CopySrcRC = SrcRC;
940 CopyFromSU->CopyDstRC = DestRC;
942 SUnit *CopyToSU = CreateNewSUnit(NULL);
943 CopyToSU->CopySrcRC = DestRC;
944 CopyToSU->CopyDstRC = SrcRC;
946 // Only copy scheduled successors. Cut them from old node's successor
947 // list and move them over.
948 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
949 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
951 if (I->isArtificial())
953 SUnit *SuccSU = I->getSUnit();
954 if (SuccSU->isScheduled) {
956 D.setSUnit(CopyToSU);
958 DelDeps.push_back(std::make_pair(SuccSU, *I));
961 // Avoid scheduling the def-side copy before other successors. Otherwise
962 // we could introduce another physreg interference on the copy and
963 // continue inserting copies indefinitely.
964 SDep D(CopyFromSU, SDep::Order, /*Latency=*/0,
965 /*Reg=*/0, /*isNormalMemory=*/false,
966 /*isMustAlias=*/false, /*isArtificial=*/true);
970 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
971 RemovePred(DelDeps[i].first, DelDeps[i].second);
973 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg));
974 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0));
976 AvailableQueue->updateNode(SU);
977 AvailableQueue->addNode(CopyFromSU);
978 AvailableQueue->addNode(CopyToSU);
979 Copies.push_back(CopyFromSU);
980 Copies.push_back(CopyToSU);
985 /// getPhysicalRegisterVT - Returns the ValueType of the physical register
986 /// definition of the specified node.
987 /// FIXME: Move to SelectionDAG?
988 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
989 const TargetInstrInfo *TII) {
990 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
991 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
992 unsigned NumRes = TID.getNumDefs();
993 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
998 return N->getValueType(NumRes);
1001 /// CheckForLiveRegDef - Return true and update live register vector if the
1002 /// specified register def of the specified SUnit clobbers any "live" registers.
1003 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
1004 std::vector<SUnit*> &LiveRegDefs,
1005 SmallSet<unsigned, 4> &RegAdded,
1006 SmallVector<unsigned, 4> &LRegs,
1007 const TargetRegisterInfo *TRI) {
1008 for (const unsigned *AliasI = TRI->getOverlaps(Reg); *AliasI; ++AliasI) {
1010 // Check if Ref is live.
1011 if (!LiveRegDefs[Reg]) continue;
1013 // Allow multiple uses of the same def.
1014 if (LiveRegDefs[Reg] == SU) continue;
1016 // Add Reg to the set of interfering live regs.
1017 if (RegAdded.insert(Reg))
1018 LRegs.push_back(Reg);
1022 /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
1023 /// scheduling of the given node to satisfy live physical register dependencies.
1024 /// If the specific node is the last one that's available to schedule, do
1025 /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
1026 bool ScheduleDAGRRList::
1027 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {
1028 if (NumLiveRegs == 0)
1031 SmallSet<unsigned, 4> RegAdded;
1032 // If this node would clobber any "live" register, then it's not ready.
1034 // If SU is the currently live definition of the same register that it uses,
1035 // then we are free to schedule it.
1036 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1038 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
1039 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
1040 RegAdded, LRegs, TRI);
1043 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
1044 if (Node->getOpcode() == ISD::INLINEASM) {
1045 // Inline asm can clobber physical defs.
1046 unsigned NumOps = Node->getNumOperands();
1047 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1048 --NumOps; // Ignore the glue operand.
1050 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1052 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1053 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1055 ++i; // Skip the ID value.
1056 if (InlineAsm::isRegDefKind(Flags) ||
1057 InlineAsm::isRegDefEarlyClobberKind(Flags)) {
1058 // Check for def of register or earlyclobber register.
1059 for (; NumVals; --NumVals, ++i) {
1060 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1061 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1062 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1070 if (!Node->isMachineOpcode())
1072 const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
1073 if (!TID.ImplicitDefs)
1075 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg)
1076 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1079 return !LRegs.empty();
1082 /// Return a node that can be scheduled in this cycle. Requirements:
1083 /// (1) Ready: latency has been satisfied
1084 /// (2) No Hazards: resources are available
1085 /// (3) No Interferences: may unschedule to break register interferences.
1086 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
1087 SmallVector<SUnit*, 4> Interferences;
1088 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
1090 SUnit *CurSU = AvailableQueue->pop();
1092 SmallVector<unsigned, 4> LRegs;
1093 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
1095 LRegsMap.insert(std::make_pair(CurSU, LRegs));
1097 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
1098 Interferences.push_back(CurSU);
1099 CurSU = AvailableQueue->pop();
1102 // Add the nodes that aren't ready back onto the available list.
1103 for (unsigned i = 0, e = Interferences.size(); i != e; ++i) {
1104 Interferences[i]->isPending = false;
1105 assert(Interferences[i]->isAvailable && "must still be available");
1106 AvailableQueue->push(Interferences[i]);
1111 // All candidates are delayed due to live physical reg dependencies.
1112 // Try backtracking, code duplication, or inserting cross class copies
1114 for (unsigned i = 0, e = Interferences.size(); i != e; ++i) {
1115 SUnit *TrySU = Interferences[i];
1116 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
1118 // Try unscheduling up to the point where it's safe to schedule
1121 unsigned LiveCycle = UINT_MAX;
1122 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) {
1123 unsigned Reg = LRegs[j];
1124 if (LiveRegGens[Reg]->getHeight() < LiveCycle) {
1125 BtSU = LiveRegGens[Reg];
1126 LiveCycle = BtSU->getHeight();
1129 if (!WillCreateCycle(TrySU, BtSU)) {
1130 BacktrackBottomUp(TrySU, BtSU);
1132 // Force the current node to be scheduled before the node that
1133 // requires the physical reg dep.
1134 if (BtSU->isAvailable) {
1135 BtSU->isAvailable = false;
1136 if (!BtSU->isPending)
1137 AvailableQueue->remove(BtSU);
1139 AddPred(TrySU, SDep(BtSU, SDep::Order, /*Latency=*/1,
1140 /*Reg=*/0, /*isNormalMemory=*/false,
1141 /*isMustAlias=*/false, /*isArtificial=*/true));
1143 // If one or more successors has been unscheduled, then the current
1144 // node is no longer avaialable. Schedule a successor that's now
1145 // available instead.
1146 if (!TrySU->isAvailable) {
1147 CurSU = AvailableQueue->pop();
1151 TrySU->isPending = false;
1152 Interferences.erase(Interferences.begin()+i);
1159 // Can't backtrack. If it's too expensive to copy the value, then try
1160 // duplicate the nodes that produces these "too expensive to copy"
1161 // values to break the dependency. In case even that doesn't work,
1162 // insert cross class copies.
1163 // If it's not too expensive, i.e. cost != -1, issue copies.
1164 SUnit *TrySU = Interferences[0];
1165 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
1166 assert(LRegs.size() == 1 && "Can't handle this yet!");
1167 unsigned Reg = LRegs[0];
1168 SUnit *LRDef = LiveRegDefs[Reg];
1169 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
1170 const TargetRegisterClass *RC =
1171 TRI->getMinimalPhysRegClass(Reg, VT);
1172 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
1174 // If cross copy register class is the same as RC, then it must be possible
1175 // copy the value directly. Do not try duplicate the def.
1176 // If cross copy register class is not the same as RC, then it's possible to
1177 // copy the value but it require cross register class copies and it is
1179 // If cross copy register class is null, then it's not possible to copy
1180 // the value at all.
1183 NewDef = CopyAndMoveSuccessors(LRDef);
1184 if (!DestRC && !NewDef)
1185 report_fatal_error("Can't handle live physical register dependency!");
1188 // Issue copies, these can be expensive cross register class copies.
1189 SmallVector<SUnit*, 2> Copies;
1190 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
1191 DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNum
1192 << " to SU #" << Copies.front()->NodeNum << "\n");
1193 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
1194 /*Reg=*/0, /*isNormalMemory=*/false,
1195 /*isMustAlias=*/false,
1196 /*isArtificial=*/true));
1197 NewDef = Copies.back();
1200 DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNum
1201 << " to SU #" << TrySU->NodeNum << "\n");
1202 LiveRegDefs[Reg] = NewDef;
1203 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
1204 /*Reg=*/0, /*isNormalMemory=*/false,
1205 /*isMustAlias=*/false,
1206 /*isArtificial=*/true));
1207 TrySU->isAvailable = false;
1211 assert(CurSU && "Unable to resolve live physical register dependencies!");
1213 // Add the nodes that aren't ready back onto the available list.
1214 for (unsigned i = 0, e = Interferences.size(); i != e; ++i) {
1215 Interferences[i]->isPending = false;
1216 // May no longer be available due to backtracking.
1217 if (Interferences[i]->isAvailable) {
1218 AvailableQueue->push(Interferences[i]);
1224 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
1226 void ScheduleDAGRRList::ListScheduleBottomUp() {
1227 // Release any predecessors of the special Exit node.
1228 ReleasePredecessors(&ExitSU);
1230 // Add root to Available queue.
1231 if (!SUnits.empty()) {
1232 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
1233 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
1234 RootSU->isAvailable = true;
1235 AvailableQueue->push(RootSU);
1238 // While Available queue is not empty, grab the node with the highest
1239 // priority. If it is not ready put it back. Schedule the node.
1240 Sequence.reserve(SUnits.size());
1241 while (!AvailableQueue->empty()) {
1242 DEBUG(dbgs() << "\nExamining Available:\n";
1243 AvailableQueue->dump(this));
1245 // Pick the best node to schedule taking all constraints into
1247 SUnit *SU = PickNodeToScheduleBottomUp();
1249 AdvancePastStalls(SU);
1251 ScheduleNodeBottomUp(SU);
1253 while (AvailableQueue->empty() && !PendingQueue.empty()) {
1254 // Advance the cycle to free resources. Skip ahead to the next ready SU.
1255 assert(MinAvailableCycle < UINT_MAX && "MinAvailableCycle uninitialized");
1256 AdvanceToCycle(std::max(CurCycle + 1, MinAvailableCycle));
1260 // Reverse the order if it is bottom up.
1261 std::reverse(Sequence.begin(), Sequence.end());
1264 VerifySchedule(isBottomUp);
1268 //===----------------------------------------------------------------------===//
1269 // Top-Down Scheduling
1270 //===----------------------------------------------------------------------===//
1272 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
1273 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
1274 void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
1275 SUnit *SuccSU = SuccEdge->getSUnit();
1278 if (SuccSU->NumPredsLeft == 0) {
1279 dbgs() << "*** Scheduling failed! ***\n";
1281 dbgs() << " has been released too many times!\n";
1282 llvm_unreachable(0);
1285 --SuccSU->NumPredsLeft;
1287 // If all the node's predecessors are scheduled, this node is ready
1288 // to be scheduled. Ignore the special ExitSU node.
1289 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) {
1290 SuccSU->isAvailable = true;
1291 AvailableQueue->push(SuccSU);
1295 void ScheduleDAGRRList::ReleaseSuccessors(SUnit *SU) {
1296 // Top down: release successors
1297 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1299 assert(!I->isAssignedRegDep() &&
1300 "The list-tdrr scheduler doesn't yet support physreg dependencies!");
1302 ReleaseSucc(SU, &*I);
1306 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
1307 /// count of its successors. If a successor pending count is zero, add it to
1308 /// the Available queue.
1309 void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU) {
1310 DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
1311 DEBUG(SU->dump(this));
1313 assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
1314 SU->setDepthToAtLeast(CurCycle);
1315 Sequence.push_back(SU);
1317 ReleaseSuccessors(SU);
1318 SU->isScheduled = true;
1319 AvailableQueue->ScheduledNode(SU);
1322 /// ListScheduleTopDown - The main loop of list scheduling for top-down
1324 void ScheduleDAGRRList::ListScheduleTopDown() {
1325 AvailableQueue->setCurCycle(CurCycle);
1327 // Release any successors of the special Entry node.
1328 ReleaseSuccessors(&EntrySU);
1330 // All leaves to Available queue.
1331 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
1332 // It is available if it has no predecessors.
1333 if (SUnits[i].Preds.empty()) {
1334 AvailableQueue->push(&SUnits[i]);
1335 SUnits[i].isAvailable = true;
1339 // While Available queue is not empty, grab the node with the highest
1340 // priority. If it is not ready put it back. Schedule the node.
1341 Sequence.reserve(SUnits.size());
1342 while (!AvailableQueue->empty()) {
1343 SUnit *CurSU = AvailableQueue->pop();
1346 ScheduleNodeTopDown(CurSU);
1348 AvailableQueue->setCurCycle(CurCycle);
1352 VerifySchedule(isBottomUp);
1357 //===----------------------------------------------------------------------===//
1358 // RegReductionPriorityQueue Definition
1359 //===----------------------------------------------------------------------===//
1361 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
1362 // to reduce register pressure.
1365 class RegReductionPQBase;
1367 struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1368 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
1371 /// bu_ls_rr_sort - Priority function for bottom up register pressure
1372 // reduction scheduler.
1373 struct bu_ls_rr_sort : public queue_sort {
1376 HasReadyFilter = false
1379 RegReductionPQBase *SPQ;
1380 bu_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {}
1381 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
1383 bool operator()(SUnit* left, SUnit* right) const;
1386 // td_ls_rr_sort - Priority function for top down register pressure reduction
1388 struct td_ls_rr_sort : public queue_sort {
1391 HasReadyFilter = false
1394 RegReductionPQBase *SPQ;
1395 td_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {}
1396 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
1398 bool operator()(const SUnit* left, const SUnit* right) const;
1401 // src_ls_rr_sort - Priority function for source order scheduler.
1402 struct src_ls_rr_sort : public queue_sort {
1405 HasReadyFilter = false
1408 RegReductionPQBase *SPQ;
1409 src_ls_rr_sort(RegReductionPQBase *spq)
1411 src_ls_rr_sort(const src_ls_rr_sort &RHS)
1414 bool operator()(SUnit* left, SUnit* right) const;
1417 // hybrid_ls_rr_sort - Priority function for hybrid scheduler.
1418 struct hybrid_ls_rr_sort : public queue_sort {
1421 HasReadyFilter = false
1424 RegReductionPQBase *SPQ;
1425 hybrid_ls_rr_sort(RegReductionPQBase *spq)
1427 hybrid_ls_rr_sort(const hybrid_ls_rr_sort &RHS)
1430 bool isReady(SUnit *SU, unsigned CurCycle) const;
1432 bool operator()(SUnit* left, SUnit* right) const;
1435 // ilp_ls_rr_sort - Priority function for ILP (instruction level parallelism)
1437 struct ilp_ls_rr_sort : public queue_sort {
1440 HasReadyFilter = false
1443 RegReductionPQBase *SPQ;
1444 ilp_ls_rr_sort(RegReductionPQBase *spq)
1446 ilp_ls_rr_sort(const ilp_ls_rr_sort &RHS)
1449 bool isReady(SUnit *SU, unsigned CurCycle) const;
1451 bool operator()(SUnit* left, SUnit* right) const;
1454 class RegReductionPQBase : public SchedulingPriorityQueue {
1456 std::vector<SUnit*> Queue;
1457 unsigned CurQueueId;
1458 bool TracksRegPressure;
1460 // SUnits - The SUnits for the current graph.
1461 std::vector<SUnit> *SUnits;
1463 MachineFunction &MF;
1464 const TargetInstrInfo *TII;
1465 const TargetRegisterInfo *TRI;
1466 const TargetLowering *TLI;
1467 ScheduleDAGRRList *scheduleDAG;
1469 // SethiUllmanNumbers - The SethiUllman number for each node.
1470 std::vector<unsigned> SethiUllmanNumbers;
1472 /// RegPressure - Tracking current reg pressure per register class.
1474 std::vector<unsigned> RegPressure;
1476 /// RegLimit - Tracking the number of allocatable registers per register
1478 std::vector<unsigned> RegLimit;
1481 RegReductionPQBase(MachineFunction &mf,
1482 bool hasReadyFilter,
1484 const TargetInstrInfo *tii,
1485 const TargetRegisterInfo *tri,
1486 const TargetLowering *tli)
1487 : SchedulingPriorityQueue(hasReadyFilter),
1488 CurQueueId(0), TracksRegPressure(tracksrp),
1489 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
1490 if (TracksRegPressure) {
1491 unsigned NumRC = TRI->getNumRegClasses();
1492 RegLimit.resize(NumRC);
1493 RegPressure.resize(NumRC);
1494 std::fill(RegLimit.begin(), RegLimit.end(), 0);
1495 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1496 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
1497 E = TRI->regclass_end(); I != E; ++I)
1498 RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF);
1502 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
1503 scheduleDAG = scheduleDag;
1506 ScheduleHazardRecognizer* getHazardRec() {
1507 return scheduleDAG->getHazardRec();
1510 void initNodes(std::vector<SUnit> &sunits);
1512 void addNode(const SUnit *SU);
1514 void updateNode(const SUnit *SU);
1516 void releaseState() {
1518 SethiUllmanNumbers.clear();
1519 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1522 unsigned getNodePriority(const SUnit *SU) const;
1524 unsigned getNodeOrdering(const SUnit *SU) const {
1525 if (!SU->getNode()) return 0;
1527 return scheduleDAG->DAG->GetOrdering(SU->getNode());
1530 bool empty() const { return Queue.empty(); }
1532 void push(SUnit *U) {
1533 assert(!U->NodeQueueId && "Node in the queue already");
1534 U->NodeQueueId = ++CurQueueId;
1538 void remove(SUnit *SU) {
1539 assert(!Queue.empty() && "Queue is empty!");
1540 assert(SU->NodeQueueId != 0 && "Not in queue!");
1541 std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(),
1543 if (I != prior(Queue.end()))
1544 std::swap(*I, Queue.back());
1546 SU->NodeQueueId = 0;
1549 bool tracksRegPressure() const { return TracksRegPressure; }
1551 void dumpRegPressure() const;
1553 bool HighRegPressure(const SUnit *SU) const;
1555 bool MayReduceRegPressure(SUnit *SU) const;
1557 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1559 void ScheduledNode(SUnit *SU);
1561 void UnscheduledNode(SUnit *SU);
1564 bool canClobber(const SUnit *SU, const SUnit *Op);
1565 void AddPseudoTwoAddrDeps();
1566 void PrescheduleNodesWithMultipleUses();
1567 void CalculateSethiUllmanNumbers();
1571 class RegReductionPriorityQueue : public RegReductionPQBase {
1572 static SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker) {
1573 std::vector<SUnit *>::iterator Best = Q.begin();
1574 for (std::vector<SUnit *>::iterator I = llvm::next(Q.begin()),
1575 E = Q.end(); I != E; ++I)
1576 if (Picker(*Best, *I))
1579 if (Best != prior(Q.end()))
1580 std::swap(*Best, Q.back());
1588 RegReductionPriorityQueue(MachineFunction &mf,
1590 const TargetInstrInfo *tii,
1591 const TargetRegisterInfo *tri,
1592 const TargetLowering *tli)
1593 : RegReductionPQBase(mf, SF::HasReadyFilter, tracksrp, tii, tri, tli),
1596 bool isBottomUp() const { return SF::IsBottomUp; }
1598 bool isReady(SUnit *U) const {
1599 return Picker.HasReadyFilter && Picker.isReady(U, getCurCycle());
1603 if (Queue.empty()) return NULL;
1605 SUnit *V = popFromQueue(Queue, Picker);
1610 void dump(ScheduleDAG *DAG) const {
1611 // Emulate pop() without clobbering NodeQueueIds.
1612 std::vector<SUnit*> DumpQueue = Queue;
1613 SF DumpPicker = Picker;
1614 while (!DumpQueue.empty()) {
1615 SUnit *SU = popFromQueue(DumpQueue, DumpPicker);
1617 dbgs() << "Height " << SU->getHeight() << ": ";
1619 dbgs() << "Depth " << SU->getDepth() << ": ";
1625 typedef RegReductionPriorityQueue<bu_ls_rr_sort>
1626 BURegReductionPriorityQueue;
1628 typedef RegReductionPriorityQueue<td_ls_rr_sort>
1629 TDRegReductionPriorityQueue;
1631 typedef RegReductionPriorityQueue<src_ls_rr_sort>
1632 SrcRegReductionPriorityQueue;
1634 typedef RegReductionPriorityQueue<hybrid_ls_rr_sort>
1635 HybridBURRPriorityQueue;
1637 typedef RegReductionPriorityQueue<ilp_ls_rr_sort>
1638 ILPBURRPriorityQueue;
1639 } // end anonymous namespace
1641 //===----------------------------------------------------------------------===//
1642 // Static Node Priority for Register Pressure Reduction
1643 //===----------------------------------------------------------------------===//
1645 // Check for special nodes that bypass scheduling heuristics.
1646 // Currently this pushes TokenFactor nodes down, but may be used for other
1647 // pseudo-ops as well.
1649 // Return -1 to schedule right above left, 1 for left above right.
1650 // Return 0 if no bias exists.
1651 static int checkSpecialNodes(const SUnit *left, const SUnit *right) {
1652 bool LSchedLow = left->isScheduleLow;
1653 bool RSchedLow = right->isScheduleLow;
1654 if (LSchedLow != RSchedLow)
1655 return LSchedLow < RSchedLow ? 1 : -1;
1659 /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
1660 /// Smaller number is the higher priority.
1662 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
1663 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
1664 if (SethiUllmanNumber != 0)
1665 return SethiUllmanNumber;
1668 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1670 if (I->isCtrl()) continue; // ignore chain preds
1671 SUnit *PredSU = I->getSUnit();
1672 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
1673 if (PredSethiUllman > SethiUllmanNumber) {
1674 SethiUllmanNumber = PredSethiUllman;
1676 } else if (PredSethiUllman == SethiUllmanNumber)
1680 SethiUllmanNumber += Extra;
1682 if (SethiUllmanNumber == 0)
1683 SethiUllmanNumber = 1;
1685 return SethiUllmanNumber;
1688 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1689 /// scheduling units.
1690 void RegReductionPQBase::CalculateSethiUllmanNumbers() {
1691 SethiUllmanNumbers.assign(SUnits->size(), 0);
1693 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1694 CalcNodeSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
1697 void RegReductionPQBase::addNode(const SUnit *SU) {
1698 unsigned SUSize = SethiUllmanNumbers.size();
1699 if (SUnits->size() > SUSize)
1700 SethiUllmanNumbers.resize(SUSize*2, 0);
1701 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1704 void RegReductionPQBase::updateNode(const SUnit *SU) {
1705 SethiUllmanNumbers[SU->NodeNum] = 0;
1706 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1709 // Lower priority means schedule further down. For bottom-up scheduling, lower
1710 // priority SUs are scheduled before higher priority SUs.
1711 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
1712 assert(SU->NodeNum < SethiUllmanNumbers.size());
1713 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
1714 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1715 // CopyToReg should be close to its uses to facilitate coalescing and
1718 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1719 Opc == TargetOpcode::SUBREG_TO_REG ||
1720 Opc == TargetOpcode::INSERT_SUBREG)
1721 // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
1722 // close to their uses to facilitate coalescing.
1724 if (SU->NumSuccs == 0 && SU->NumPreds != 0)
1725 // If SU does not have a register use, i.e. it doesn't produce a value
1726 // that would be consumed (e.g. store), then it terminates a chain of
1727 // computation. Give it a large SethiUllman number so it will be
1728 // scheduled right before its predecessors that it doesn't lengthen
1729 // their live ranges.
1731 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
1732 // If SU does not have a register def, schedule it close to its uses
1733 // because it does not lengthen any live ranges.
1735 return SethiUllmanNumbers[SU->NodeNum];
1738 //===----------------------------------------------------------------------===//
1739 // Register Pressure Tracking
1740 //===----------------------------------------------------------------------===//
1742 void RegReductionPQBase::dumpRegPressure() const {
1743 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
1744 E = TRI->regclass_end(); I != E; ++I) {
1745 const TargetRegisterClass *RC = *I;
1746 unsigned Id = RC->getID();
1747 unsigned RP = RegPressure[Id];
1749 DEBUG(dbgs() << RC->getName() << ": " << RP << " / " << RegLimit[Id]
1754 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
1758 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1762 SUnit *PredSU = I->getSUnit();
1763 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1764 // to cover the number of registers defined (they are all live).
1765 if (PredSU->NumRegDefsLeft == 0) {
1768 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
1769 RegDefPos.IsValid(); RegDefPos.Advance()) {
1770 EVT VT = RegDefPos.GetValue();
1771 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1772 unsigned Cost = TLI->getRepRegClassCostFor(VT);
1773 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
1780 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const {
1781 const SDNode *N = SU->getNode();
1783 if (!N->isMachineOpcode() || !SU->NumSuccs)
1786 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
1787 for (unsigned i = 0; i != NumDefs; ++i) {
1788 EVT VT = N->getValueType(i);
1789 if (!N->hasAnyUseOfValue(i))
1791 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1792 if (RegPressure[RCId] >= RegLimit[RCId])
1798 // Compute the register pressure contribution by this instruction by count up
1799 // for uses that are not live and down for defs. Only count register classes
1800 // that are already under high pressure. As a side effect, compute the number of
1801 // uses of registers that are already live.
1803 // FIXME: This encompasses the logic in HighRegPressure and MayReduceRegPressure
1804 // so could probably be factored.
1805 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
1808 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1812 SUnit *PredSU = I->getSUnit();
1813 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1814 // to cover the number of registers defined (they are all live).
1815 if (PredSU->NumRegDefsLeft == 0) {
1816 if (PredSU->getNode()->isMachineOpcode())
1820 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
1821 RegDefPos.IsValid(); RegDefPos.Advance()) {
1822 EVT VT = RegDefPos.GetValue();
1823 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1824 if (RegPressure[RCId] >= RegLimit[RCId])
1828 const SDNode *N = SU->getNode();
1830 if (!N || !N->isMachineOpcode() || !SU->NumSuccs)
1833 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
1834 for (unsigned i = 0; i != NumDefs; ++i) {
1835 EVT VT = N->getValueType(i);
1836 if (!N->hasAnyUseOfValue(i))
1838 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1839 if (RegPressure[RCId] >= RegLimit[RCId])
1845 void RegReductionPQBase::ScheduledNode(SUnit *SU) {
1846 if (!TracksRegPressure)
1852 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1856 SUnit *PredSU = I->getSUnit();
1857 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1858 // to cover the number of registers defined (they are all live).
1859 if (PredSU->NumRegDefsLeft == 0) {
1862 // FIXME: The ScheduleDAG currently loses information about which of a
1863 // node's values is consumed by each dependence. Consequently, if the node
1864 // defines multiple register classes, we don't know which to pressurize
1865 // here. Instead the following loop consumes the register defs in an
1866 // arbitrary order. At least it handles the common case of clustered loads
1867 // to the same class. For precise liveness, each SDep needs to indicate the
1868 // result number. But that tightly couples the ScheduleDAG with the
1869 // SelectionDAG making updates tricky. A simpler hack would be to attach a
1870 // value type or register class to SDep.
1872 // The most important aspect of register tracking is balancing the increase
1873 // here with the reduction further below. Note that this SU may use multiple
1874 // defs in PredSU. The can't be determined here, but we've already
1875 // compensated by reducing NumRegDefsLeft in PredSU during
1876 // ScheduleDAGSDNodes::AddSchedEdges.
1877 --PredSU->NumRegDefsLeft;
1878 unsigned SkipRegDefs = PredSU->NumRegDefsLeft;
1879 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
1880 RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
1883 EVT VT = RegDefPos.GetValue();
1884 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1885 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
1890 // We should have this assert, but there may be dead SDNodes that never
1891 // materialize as SUnits, so they don't appear to generate liveness.
1892 //assert(SU->NumRegDefsLeft == 0 && "not all regdefs have scheduled uses");
1893 int SkipRegDefs = (int)SU->NumRegDefsLeft;
1894 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG);
1895 RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
1896 if (SkipRegDefs > 0)
1898 EVT VT = RegDefPos.GetValue();
1899 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1900 if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT)) {
1901 // Register pressure tracking is imprecise. This can happen. But we try
1902 // hard not to let it happen because it likely results in poor scheduling.
1903 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n");
1904 RegPressure[RCId] = 0;
1907 RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
1913 void RegReductionPQBase::UnscheduledNode(SUnit *SU) {
1914 if (!TracksRegPressure)
1917 const SDNode *N = SU->getNode();
1920 if (!N->isMachineOpcode()) {
1921 if (N->getOpcode() != ISD::CopyToReg)
1924 unsigned Opc = N->getMachineOpcode();
1925 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1926 Opc == TargetOpcode::INSERT_SUBREG ||
1927 Opc == TargetOpcode::SUBREG_TO_REG ||
1928 Opc == TargetOpcode::REG_SEQUENCE ||
1929 Opc == TargetOpcode::IMPLICIT_DEF)
1933 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1937 SUnit *PredSU = I->getSUnit();
1938 // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
1939 // counts data deps.
1940 if (PredSU->NumSuccsLeft != PredSU->Succs.size())
1942 const SDNode *PN = PredSU->getNode();
1943 if (!PN->isMachineOpcode()) {
1944 if (PN->getOpcode() == ISD::CopyFromReg) {
1945 EVT VT = PN->getValueType(0);
1946 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1947 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
1951 unsigned POpc = PN->getMachineOpcode();
1952 if (POpc == TargetOpcode::IMPLICIT_DEF)
1954 if (POpc == TargetOpcode::EXTRACT_SUBREG) {
1955 EVT VT = PN->getOperand(0).getValueType();
1956 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1957 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
1959 } else if (POpc == TargetOpcode::INSERT_SUBREG ||
1960 POpc == TargetOpcode::SUBREG_TO_REG) {
1961 EVT VT = PN->getValueType(0);
1962 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1963 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
1966 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
1967 for (unsigned i = 0; i != NumDefs; ++i) {
1968 EVT VT = PN->getValueType(i);
1969 if (!PN->hasAnyUseOfValue(i))
1971 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1972 if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
1973 // Register pressure tracking is imprecise. This can happen.
1974 RegPressure[RCId] = 0;
1976 RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
1980 // Check for isMachineOpcode() as PrescheduleNodesWithMultipleUses()
1981 // may transfer data dependencies to CopyToReg.
1982 if (SU->NumSuccs && N->isMachineOpcode()) {
1983 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
1984 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
1985 EVT VT = N->getValueType(i);
1986 if (VT == MVT::Glue || VT == MVT::Other)
1988 if (!N->hasAnyUseOfValue(i))
1990 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1991 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
1998 //===----------------------------------------------------------------------===//
1999 // Dynamic Node Priority for Register Pressure Reduction
2000 //===----------------------------------------------------------------------===//
2002 /// closestSucc - Returns the scheduled cycle of the successor which is
2003 /// closest to the current cycle.
2004 static unsigned closestSucc(const SUnit *SU) {
2005 unsigned MaxHeight = 0;
2006 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2008 if (I->isCtrl()) continue; // ignore chain succs
2009 unsigned Height = I->getSUnit()->getHeight();
2010 // If there are bunch of CopyToRegs stacked up, they should be considered
2011 // to be at the same position.
2012 if (I->getSUnit()->getNode() &&
2013 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2014 Height = closestSucc(I->getSUnit())+1;
2015 if (Height > MaxHeight)
2021 /// calcMaxScratches - Returns an cost estimate of the worse case requirement
2022 /// for scratch registers, i.e. number of data dependencies.
2023 static unsigned calcMaxScratches(const SUnit *SU) {
2024 unsigned Scratches = 0;
2025 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2027 if (I->isCtrl()) continue; // ignore chain preds
2033 /// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are
2034 /// CopyFromReg from a virtual register.
2035 static bool hasOnlyLiveInOpers(const SUnit *SU) {
2036 bool RetVal = false;
2037 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2039 if (I->isCtrl()) continue;
2040 const SUnit *PredSU = I->getSUnit();
2041 if (PredSU->getNode() &&
2042 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
2044 cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2045 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2055 /// hasOnlyLiveOutUses - Return true if SU has only value successors that are
2056 /// CopyToReg to a virtual register. This SU def is probably a liveout and
2057 /// it has no other use. It should be scheduled closer to the terminator.
2058 static bool hasOnlyLiveOutUses(const SUnit *SU) {
2059 bool RetVal = false;
2060 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2062 if (I->isCtrl()) continue;
2063 const SUnit *SuccSU = I->getSUnit();
2064 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) {
2066 cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();
2067 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2077 // Set isVRegCycle for a node with only live in opers and live out uses. Also
2078 // set isVRegCycle for its CopyFromReg operands.
2080 // This is only relevant for single-block loops, in which case the VRegCycle
2081 // node is likely an induction variable in which the operand and target virtual
2082 // registers should be coalesced (e.g. pre/post increment values). Setting the
2083 // isVRegCycle flag helps the scheduler prioritize other uses of the same
2084 // CopyFromReg so that this node becomes the virtual register "kill". This
2085 // avoids interference between the values live in and out of the block and
2086 // eliminates a copy inside the loop.
2087 static void initVRegCycle(SUnit *SU) {
2088 if (DisableSchedVRegCycle)
2091 if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU))
2094 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n");
2096 SU->isVRegCycle = true;
2098 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2100 if (I->isCtrl()) continue;
2101 I->getSUnit()->isVRegCycle = true;
2105 // After scheduling the definition of a VRegCycle, clear the isVRegCycle flag of
2106 // CopyFromReg operands. We should no longer penalize other uses of this VReg.
2107 static void resetVRegCycle(SUnit *SU) {
2108 if (!SU->isVRegCycle)
2111 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2113 if (I->isCtrl()) continue; // ignore chain preds
2114 SUnit *PredSU = I->getSUnit();
2115 if (PredSU->isVRegCycle) {
2116 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
2117 "VRegCycle def must be CopyFromReg");
2118 I->getSUnit()->isVRegCycle = 0;
2123 // Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This
2124 // means a node that defines the VRegCycle has not been scheduled yet.
2125 static bool hasVRegCycleUse(const SUnit *SU) {
2126 // If this SU also defines the VReg, don't hoist it as a "use".
2127 if (SU->isVRegCycle)
2130 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2132 if (I->isCtrl()) continue; // ignore chain preds
2133 if (I->getSUnit()->isVRegCycle &&
2134 I->getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2135 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n");
2142 // Check for either a dependence (latency) or resource (hazard) stall.
2144 // Note: The ScheduleHazardRecognizer interface requires a non-const SU.
2145 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) {
2146 if ((int)SPQ->getCurCycle() < Height) return true;
2147 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2148 != ScheduleHazardRecognizer::NoHazard)
2153 // Return -1 if left has higher priority, 1 if right has higher priority.
2154 // Return 0 if latency-based priority is equivalent.
2155 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
2156 RegReductionPQBase *SPQ) {
2157 // Scheduling an instruction that uses a VReg whose postincrement has not yet
2158 // been scheduled will induce a copy. Model this as an extra cycle of latency.
2159 int LPenalty = hasVRegCycleUse(left) ? 1 : 0;
2160 int RPenalty = hasVRegCycleUse(right) ? 1 : 0;
2161 int LHeight = (int)left->getHeight() + LPenalty;
2162 int RHeight = (int)right->getHeight() + RPenalty;
2164 bool LStall = (!checkPref || left->SchedulingPref == Sched::Latency) &&
2165 BUHasStall(left, LHeight, SPQ);
2166 bool RStall = (!checkPref || right->SchedulingPref == Sched::Latency) &&
2167 BUHasStall(right, RHeight, SPQ);
2169 // If scheduling one of the node will cause a pipeline stall, delay it.
2170 // If scheduling either one of the node will cause a pipeline stall, sort
2171 // them according to their height.
2174 DEBUG(++FactorCount[FactStall]);
2177 if (LHeight != RHeight) {
2178 DEBUG(++FactorCount[FactStall]);
2179 return LHeight > RHeight ? 1 : -1;
2181 } else if (RStall) {
2182 DEBUG(++FactorCount[FactStall]);
2186 // If either node is scheduling for latency, sort them by height/depth
2188 if (!checkPref || (left->SchedulingPref == Sched::Latency ||
2189 right->SchedulingPref == Sched::Latency)) {
2190 if (DisableSchedCycles) {
2191 if (LHeight != RHeight) {
2192 DEBUG(++FactorCount[FactHeight]);
2193 return LHeight > RHeight ? 1 : -1;
2197 // If neither instruction stalls (!LStall && !RStall) then
2198 // its height is already covered so only its depth matters. We also reach
2199 // this if both stall but have the same height.
2200 int LDepth = left->getDepth() - LPenalty;
2201 int RDepth = right->getDepth() - RPenalty;
2202 if (LDepth != RDepth) {
2203 DEBUG(++FactorCount[FactDepth]);
2204 DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum
2205 << ") depth " << LDepth << " vs SU (" << right->NodeNum
2206 << ") depth " << RDepth << "\n");
2207 return LDepth < RDepth ? 1 : -1;
2210 if (left->Latency != right->Latency) {
2211 DEBUG(++FactorCount[FactOther]);
2212 return left->Latency > right->Latency ? 1 : -1;
2218 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
2219 // Schedule physical register definitions close to their use. This is
2220 // motivated by microarchitectures that can fuse cmp+jump macro-ops. But as
2221 // long as shortening physreg live ranges is generally good, we can defer
2222 // creating a subtarget hook.
2223 if (!DisableSchedPhysRegJoin) {
2224 bool LHasPhysReg = left->hasPhysRegDefs;
2225 bool RHasPhysReg = right->hasPhysRegDefs;
2226 if (LHasPhysReg != RHasPhysReg) {
2227 DEBUG(++FactorCount[FactRegUses]);
2229 const char *PhysRegMsg[] = {" has no physreg", " defines a physreg"};
2231 DEBUG(dbgs() << " SU (" << left->NodeNum << ") "
2232 << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") "
2233 << PhysRegMsg[RHasPhysReg] << "\n");
2234 return LHasPhysReg < RHasPhysReg;
2238 // Prioritize by Sethi-Ulmann number and push CopyToReg nodes down.
2239 unsigned LPriority = SPQ->getNodePriority(left);
2240 unsigned RPriority = SPQ->getNodePriority(right);
2241 if (LPriority != RPriority) {
2242 DEBUG(++FactorCount[FactStatic]);
2243 return LPriority > RPriority;
2246 // Try schedule def + use closer when Sethi-Ullman numbers are the same.
2251 // and the following instructions are both ready.
2255 // Then schedule t2 = op first.
2262 // This creates more short live intervals.
2263 unsigned LDist = closestSucc(left);
2264 unsigned RDist = closestSucc(right);
2265 if (LDist != RDist) {
2266 DEBUG(++FactorCount[FactOther]);
2267 return LDist < RDist;
2270 // How many registers becomes live when the node is scheduled.
2271 unsigned LScratch = calcMaxScratches(left);
2272 unsigned RScratch = calcMaxScratches(right);
2273 if (LScratch != RScratch) {
2274 DEBUG(++FactorCount[FactOther]);
2275 return LScratch > RScratch;
2278 if (!DisableSchedCycles) {
2279 int result = BUCompareLatency(left, right, false /*checkPref*/, SPQ);
2284 if (left->getHeight() != right->getHeight()) {
2285 DEBUG(++FactorCount[FactHeight]);
2286 return left->getHeight() > right->getHeight();
2289 if (left->getDepth() != right->getDepth()) {
2290 DEBUG(++FactorCount[FactDepth]);
2291 return left->getDepth() < right->getDepth();
2295 assert(left->NodeQueueId && right->NodeQueueId &&
2296 "NodeQueueId cannot be zero");
2297 DEBUG(++FactorCount[FactOther]);
2298 return (left->NodeQueueId > right->NodeQueueId);
2302 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2303 if (int res = checkSpecialNodes(left, right))
2306 return BURRSort(left, right, SPQ);
2309 // Source order, otherwise bottom up.
2310 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2311 if (int res = checkSpecialNodes(left, right))
2314 unsigned LOrder = SPQ->getNodeOrdering(left);
2315 unsigned ROrder = SPQ->getNodeOrdering(right);
2317 // Prefer an ordering where the lower the non-zero order number, the higher
2319 if ((LOrder || ROrder) && LOrder != ROrder)
2320 return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
2322 return BURRSort(left, right, SPQ);
2325 // If the time between now and when the instruction will be ready can cover
2326 // the spill code, then avoid adding it to the ready queue. This gives long
2327 // stalls highest priority and allows hoisting across calls. It should also
2328 // speed up processing the available queue.
2329 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2330 static const unsigned ReadyDelay = 3;
2332 if (SPQ->MayReduceRegPressure(SU)) return true;
2334 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false;
2336 if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay)
2337 != ScheduleHazardRecognizer::NoHazard)
2343 // Return true if right should be scheduled with higher priority than left.
2344 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2345 if (int res = checkSpecialNodes(left, right))
2348 if (left->isCall || right->isCall)
2349 // No way to compute latency of calls.
2350 return BURRSort(left, right, SPQ);
2352 bool LHigh = SPQ->HighRegPressure(left);
2353 bool RHigh = SPQ->HighRegPressure(right);
2354 // Avoid causing spills. If register pressure is high, schedule for
2355 // register pressure reduction.
2356 if (LHigh && !RHigh) {
2357 DEBUG(++FactorCount[FactPressureDiff]);
2358 DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("
2359 << right->NodeNum << ")\n");
2362 else if (!LHigh && RHigh) {
2363 DEBUG(++FactorCount[FactPressureDiff]);
2364 DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("
2365 << left->NodeNum << ")\n");
2368 if (!LHigh && !RHigh) {
2369 int result = BUCompareLatency(left, right, true /*checkPref*/, SPQ);
2373 return BURRSort(left, right, SPQ);
2376 // Schedule as many instructions in each cycle as possible. So don't make an
2377 // instruction available unless it is ready in the current cycle.
2378 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2379 if (SU->getHeight() > CurCycle) return false;
2381 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2382 != ScheduleHazardRecognizer::NoHazard)
2388 static bool canEnableCoalescing(SUnit *SU) {
2389 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
2390 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
2391 // CopyToReg should be close to its uses to facilitate coalescing and
2395 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
2396 Opc == TargetOpcode::SUBREG_TO_REG ||
2397 Opc == TargetOpcode::INSERT_SUBREG)
2398 // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
2399 // close to their uses to facilitate coalescing.
2402 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
2403 // If SU does not have a register def, schedule it close to its uses
2404 // because it does not lengthen any live ranges.
2410 // list-ilp is currently an experimental scheduler that allows various
2411 // heuristics to be enabled prior to the normal register reduction logic.
2412 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2413 if (int res = checkSpecialNodes(left, right))
2416 if (left->isCall || right->isCall)
2417 // No way to compute latency of calls.
2418 return BURRSort(left, right, SPQ);
2420 unsigned LLiveUses = 0, RLiveUses = 0;
2421 int LPDiff = 0, RPDiff = 0;
2422 if (!DisableSchedRegPressure || !DisableSchedLiveUses) {
2423 LPDiff = SPQ->RegPressureDiff(left, LLiveUses);
2424 RPDiff = SPQ->RegPressureDiff(right, RLiveUses);
2426 if (!DisableSchedRegPressure && LPDiff != RPDiff) {
2427 DEBUG(++FactorCount[FactPressureDiff]);
2428 DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff
2429 << " != SU(" << right->NodeNum << "): " << RPDiff << "\n");
2430 return LPDiff > RPDiff;
2433 if (!DisableSchedRegPressure && (LPDiff > 0 || RPDiff > 0)) {
2434 bool LReduce = canEnableCoalescing(left);
2435 bool RReduce = canEnableCoalescing(right);
2436 DEBUG(if (LReduce != RReduce) ++FactorCount[FactPressureDiff]);
2437 if (LReduce && !RReduce) return false;
2438 if (RReduce && !LReduce) return true;
2441 if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) {
2442 DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
2443 << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n");
2444 DEBUG(++FactorCount[FactRegUses]);
2445 return LLiveUses < RLiveUses;
2448 if (!DisableSchedStalls) {
2449 bool LStall = BUHasStall(left, left->getHeight(), SPQ);
2450 bool RStall = BUHasStall(right, right->getHeight(), SPQ);
2451 if (LStall != RStall) {
2452 DEBUG(++FactorCount[FactHeight]);
2453 return left->getHeight() > right->getHeight();
2457 if (!DisableSchedCriticalPath) {
2458 int spread = (int)left->getDepth() - (int)right->getDepth();
2459 if (std::abs(spread) > MaxReorderWindow) {
2460 DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
2461 << left->getDepth() << " != SU(" << right->NodeNum << "): "
2462 << right->getDepth() << "\n");
2463 DEBUG(++FactorCount[FactDepth]);
2464 return left->getDepth() < right->getDepth();
2468 if (!DisableSchedHeight && left->getHeight() != right->getHeight()) {
2469 int spread = (int)left->getHeight() - (int)right->getHeight();
2470 if (std::abs(spread) > MaxReorderWindow) {
2471 DEBUG(++FactorCount[FactHeight]);
2472 return left->getHeight() > right->getHeight();
2476 return BURRSort(left, right, SPQ);
2479 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
2481 // Add pseudo dependency edges for two-address nodes.
2482 AddPseudoTwoAddrDeps();
2483 // Reroute edges to nodes with multiple uses.
2484 if (!TracksRegPressure)
2485 PrescheduleNodesWithMultipleUses();
2486 // Calculate node priorities.
2487 CalculateSethiUllmanNumbers();
2489 // For single block loops, mark nodes that look like canonical IV increments.
2490 if (scheduleDAG->BB->isSuccessor(scheduleDAG->BB)) {
2491 for (unsigned i = 0, e = sunits.size(); i != e; ++i) {
2492 initVRegCycle(&sunits[i]);
2497 //===----------------------------------------------------------------------===//
2498 // Preschedule for Register Pressure
2499 //===----------------------------------------------------------------------===//
2501 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
2502 if (SU->isTwoAddress) {
2503 unsigned Opc = SU->getNode()->getMachineOpcode();
2504 const TargetInstrDesc &TID = TII->get(Opc);
2505 unsigned NumRes = TID.getNumDefs();
2506 unsigned NumOps = TID.getNumOperands() - NumRes;
2507 for (unsigned i = 0; i != NumOps; ++i) {
2508 if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
2509 SDNode *DU = SU->getNode()->getOperand(i).getNode();
2510 if (DU->getNodeId() != -1 &&
2511 Op->OrigNode == &(*SUnits)[DU->getNodeId()])
2519 /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
2520 /// physical register defs.
2521 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
2522 const TargetInstrInfo *TII,
2523 const TargetRegisterInfo *TRI) {
2524 SDNode *N = SuccSU->getNode();
2525 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2526 const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2527 assert(ImpDefs && "Caller should check hasPhysRegDefs");
2528 for (const SDNode *SUNode = SU->getNode(); SUNode;
2529 SUNode = SUNode->getGluedNode()) {
2530 if (!SUNode->isMachineOpcode())
2532 const unsigned *SUImpDefs =
2533 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
2536 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
2537 EVT VT = N->getValueType(i);
2538 if (VT == MVT::Glue || VT == MVT::Other)
2540 if (!N->hasAnyUseOfValue(i))
2542 unsigned Reg = ImpDefs[i - NumDefs];
2543 for (;*SUImpDefs; ++SUImpDefs) {
2544 unsigned SUReg = *SUImpDefs;
2545 if (TRI->regsOverlap(Reg, SUReg))
2553 /// PrescheduleNodesWithMultipleUses - Nodes with multiple uses
2554 /// are not handled well by the general register pressure reduction
2555 /// heuristics. When presented with code like this:
2564 /// the heuristics tend to push the store up, but since the
2565 /// operand of the store has another use (U), this would increase
2566 /// the length of that other use (the U->N edge).
2568 /// This function transforms code like the above to route U's
2569 /// dependence through the store when possible, like this:
2580 /// This results in the store being scheduled immediately
2581 /// after N, which shortens the U->N live range, reducing
2582 /// register pressure.
2584 void RegReductionPQBase::PrescheduleNodesWithMultipleUses() {
2585 // Visit all the nodes in topological order, working top-down.
2586 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
2587 SUnit *SU = &(*SUnits)[i];
2588 // For now, only look at nodes with no data successors, such as stores.
2589 // These are especially important, due to the heuristics in
2590 // getNodePriority for nodes with no data successors.
2591 if (SU->NumSuccs != 0)
2593 // For now, only look at nodes with exactly one data predecessor.
2594 if (SU->NumPreds != 1)
2596 // Avoid prescheduling copies to virtual registers, which don't behave
2597 // like other nodes from the perspective of scheduling heuristics.
2598 if (SDNode *N = SU->getNode())
2599 if (N->getOpcode() == ISD::CopyToReg &&
2600 TargetRegisterInfo::isVirtualRegister
2601 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2604 // Locate the single data predecessor.
2606 for (SUnit::const_pred_iterator II = SU->Preds.begin(),
2607 EE = SU->Preds.end(); II != EE; ++II)
2608 if (!II->isCtrl()) {
2609 PredSU = II->getSUnit();
2614 // Don't rewrite edges that carry physregs, because that requires additional
2615 // support infrastructure.
2616 if (PredSU->hasPhysRegDefs)
2618 // Short-circuit the case where SU is PredSU's only data successor.
2619 if (PredSU->NumSuccs == 1)
2621 // Avoid prescheduling to copies from virtual registers, which don't behave
2622 // like other nodes from the perspective of scheduling heuristics.
2623 if (SDNode *N = SU->getNode())
2624 if (N->getOpcode() == ISD::CopyFromReg &&
2625 TargetRegisterInfo::isVirtualRegister
2626 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2629 // Perform checks on the successors of PredSU.
2630 for (SUnit::const_succ_iterator II = PredSU->Succs.begin(),
2631 EE = PredSU->Succs.end(); II != EE; ++II) {
2632 SUnit *PredSuccSU = II->getSUnit();
2633 if (PredSuccSU == SU) continue;
2634 // If PredSU has another successor with no data successors, for
2635 // now don't attempt to choose either over the other.
2636 if (PredSuccSU->NumSuccs == 0)
2637 goto outer_loop_continue;
2638 // Don't break physical register dependencies.
2639 if (SU->hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs)
2640 if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI))
2641 goto outer_loop_continue;
2642 // Don't introduce graph cycles.
2643 if (scheduleDAG->IsReachable(SU, PredSuccSU))
2644 goto outer_loop_continue;
2647 // Ok, the transformation is safe and the heuristics suggest it is
2648 // profitable. Update the graph.
2649 DEBUG(dbgs() << " Prescheduling SU #" << SU->NodeNum
2650 << " next to PredSU #" << PredSU->NodeNum
2651 << " to guide scheduling in the presence of multiple uses\n");
2652 for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
2653 SDep Edge = PredSU->Succs[i];
2654 assert(!Edge.isAssignedRegDep());
2655 SUnit *SuccSU = Edge.getSUnit();
2657 Edge.setSUnit(PredSU);
2658 scheduleDAG->RemovePred(SuccSU, Edge);
2659 scheduleDAG->AddPred(SU, Edge);
2661 scheduleDAG->AddPred(SuccSU, Edge);
2665 outer_loop_continue:;
2669 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
2670 /// it as a def&use operand. Add a pseudo control edge from it to the other
2671 /// node (if it won't create a cycle) so the two-address one will be scheduled
2672 /// first (lower in the schedule). If both nodes are two-address, favor the
2673 /// one that has a CopyToReg use (more likely to be a loop induction update).
2674 /// If both are two-address, but one is commutable while the other is not
2675 /// commutable, favor the one that's not commutable.
2676 void RegReductionPQBase::AddPseudoTwoAddrDeps() {
2677 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
2678 SUnit *SU = &(*SUnits)[i];
2679 if (!SU->isTwoAddress)
2682 SDNode *Node = SU->getNode();
2683 if (!Node || !Node->isMachineOpcode() || SU->getNode()->getGluedNode())
2686 bool isLiveOut = hasOnlyLiveOutUses(SU);
2687 unsigned Opc = Node->getMachineOpcode();
2688 const TargetInstrDesc &TID = TII->get(Opc);
2689 unsigned NumRes = TID.getNumDefs();
2690 unsigned NumOps = TID.getNumOperands() - NumRes;
2691 for (unsigned j = 0; j != NumOps; ++j) {
2692 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
2694 SDNode *DU = SU->getNode()->getOperand(j).getNode();
2695 if (DU->getNodeId() == -1)
2697 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
2698 if (!DUSU) continue;
2699 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
2700 E = DUSU->Succs.end(); I != E; ++I) {
2701 if (I->isCtrl()) continue;
2702 SUnit *SuccSU = I->getSUnit();
2705 // Be conservative. Ignore if nodes aren't at roughly the same
2706 // depth and height.
2707 if (SuccSU->getHeight() < SU->getHeight() &&
2708 (SU->getHeight() - SuccSU->getHeight()) > 1)
2710 // Skip past COPY_TO_REGCLASS nodes, so that the pseudo edge
2711 // constrains whatever is using the copy, instead of the copy
2712 // itself. In the case that the copy is coalesced, this
2713 // preserves the intent of the pseudo two-address heurietics.
2714 while (SuccSU->Succs.size() == 1 &&
2715 SuccSU->getNode()->isMachineOpcode() &&
2716 SuccSU->getNode()->getMachineOpcode() ==
2717 TargetOpcode::COPY_TO_REGCLASS)
2718 SuccSU = SuccSU->Succs.front().getSUnit();
2719 // Don't constrain non-instruction nodes.
2720 if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
2722 // Don't constrain nodes with physical register defs if the
2723 // predecessor can clobber them.
2724 if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) {
2725 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
2728 // Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG;
2729 // these may be coalesced away. We want them close to their uses.
2730 unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
2731 if (SuccOpc == TargetOpcode::EXTRACT_SUBREG ||
2732 SuccOpc == TargetOpcode::INSERT_SUBREG ||
2733 SuccOpc == TargetOpcode::SUBREG_TO_REG)
2735 if ((!canClobber(SuccSU, DUSU) ||
2736 (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) ||
2737 (!SU->isCommutable && SuccSU->isCommutable)) &&
2738 !scheduleDAG->IsReachable(SuccSU, SU)) {
2739 DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #"
2740 << SU->NodeNum << " to SU #" << SuccSU->NodeNum << "\n");
2741 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/0,
2742 /*Reg=*/0, /*isNormalMemory=*/false,
2743 /*isMustAlias=*/false,
2744 /*isArtificial=*/true));
2751 /// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled
2752 /// predecessors of the successors of the SUnit SU. Stop when the provided
2753 /// limit is exceeded.
2754 static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
2757 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2759 const SUnit *SuccSU = I->getSUnit();
2760 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
2761 EE = SuccSU->Preds.end(); II != EE; ++II) {
2762 SUnit *PredSU = II->getSUnit();
2763 if (!PredSU->isScheduled)
2773 bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
2774 if (int res = checkSpecialNodes(left, right))
2777 unsigned LPriority = SPQ->getNodePriority(left);
2778 unsigned RPriority = SPQ->getNodePriority(right);
2779 bool LIsTarget = left->getNode() && left->getNode()->isMachineOpcode();
2780 bool RIsTarget = right->getNode() && right->getNode()->isMachineOpcode();
2781 bool LIsFloater = LIsTarget && left->NumPreds == 0;
2782 bool RIsFloater = RIsTarget && right->NumPreds == 0;
2783 unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0;
2784 unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0;
2786 if (left->NumSuccs == 0 && right->NumSuccs != 0)
2788 else if (left->NumSuccs != 0 && right->NumSuccs == 0)
2795 if (left->NumSuccs == 1)
2797 if (right->NumSuccs == 1)
2800 if (LPriority+LBonus != RPriority+RBonus)
2801 return LPriority+LBonus < RPriority+RBonus;
2803 if (left->getDepth() != right->getDepth())
2804 return left->getDepth() < right->getDepth();
2806 if (left->NumSuccsLeft != right->NumSuccsLeft)
2807 return left->NumSuccsLeft > right->NumSuccsLeft;
2809 assert(left->NodeQueueId && right->NodeQueueId &&
2810 "NodeQueueId cannot be zero");
2811 return (left->NodeQueueId > right->NodeQueueId);
2814 //===----------------------------------------------------------------------===//
2815 // Public Constructor Functions
2816 //===----------------------------------------------------------------------===//
2818 llvm::ScheduleDAGSDNodes *
2819 llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
2820 CodeGenOpt::Level OptLevel) {
2821 const TargetMachine &TM = IS->TM;
2822 const TargetInstrInfo *TII = TM.getInstrInfo();
2823 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2825 BURegReductionPriorityQueue *PQ =
2826 new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
2827 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2828 PQ->setScheduleDAG(SD);
2832 llvm::ScheduleDAGSDNodes *
2833 llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
2834 CodeGenOpt::Level OptLevel) {
2835 const TargetMachine &TM = IS->TM;
2836 const TargetInstrInfo *TII = TM.getInstrInfo();
2837 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2839 TDRegReductionPriorityQueue *PQ =
2840 new TDRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
2841 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2842 PQ->setScheduleDAG(SD);
2846 llvm::ScheduleDAGSDNodes *
2847 llvm::createSourceListDAGScheduler(SelectionDAGISel *IS,
2848 CodeGenOpt::Level OptLevel) {
2849 const TargetMachine &TM = IS->TM;
2850 const TargetInstrInfo *TII = TM.getInstrInfo();
2851 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2853 SrcRegReductionPriorityQueue *PQ =
2854 new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
2855 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2856 PQ->setScheduleDAG(SD);
2860 llvm::ScheduleDAGSDNodes *
2861 llvm::createHybridListDAGScheduler(SelectionDAGISel *IS,
2862 CodeGenOpt::Level OptLevel) {
2863 const TargetMachine &TM = IS->TM;
2864 const TargetInstrInfo *TII = TM.getInstrInfo();
2865 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2866 const TargetLowering *TLI = &IS->getTargetLowering();
2868 HybridBURRPriorityQueue *PQ =
2869 new HybridBURRPriorityQueue(*IS->MF, true, TII, TRI, TLI);
2871 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
2872 PQ->setScheduleDAG(SD);
2876 llvm::ScheduleDAGSDNodes *
2877 llvm::createILPListDAGScheduler(SelectionDAGISel *IS,
2878 CodeGenOpt::Level OptLevel) {
2879 const TargetMachine &TM = IS->TM;
2880 const TargetInstrInfo *TII = TM.getInstrInfo();
2881 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2882 const TargetLowering *TLI = &IS->getTargetLowering();
2884 ILPBURRPriorityQueue *PQ =
2885 new ILPBURRPriorityQueue(*IS->MF, true, TII, TRI, TLI);
2886 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
2887 PQ->setScheduleDAG(SD);