Added a check in the preRA scheduler for potential interference on a
authorAndrew Trick <atrick@apple.com>
Thu, 7 Apr 2011 19:54:57 +0000 (19:54 +0000)
committerAndrew Trick <atrick@apple.com>
Thu, 7 Apr 2011 19:54:57 +0000 (19:54 +0000)
commit54699765064842fd08d1466adc93453660bc2a85
tree7b7dd1f577848063e5f0a0beb05f633edbe7705e
parent9777e7afd4a9a348f043e914192d491b620659f1
Added a check in the preRA scheduler for potential interference on a
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/ScheduleDAG.h
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
test/CodeGen/ARM/2011-04-07-schediv.ll [new file with mode: 0644]