1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "pre-RA-sched"
19 #include "ScheduleDAGSDNodes.h"
20 #include "llvm/InlineAsm.h"
21 #include "llvm/CodeGen/SchedulerRegistry.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/ADT/SmallSet.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 STATISTIC(NumBacktracks, "Number of times scheduler backtracked");
39 STATISTIC(NumUnfolds, "Number of nodes unfolded");
40 STATISTIC(NumDups, "Number of duplicated nodes");
41 STATISTIC(NumPRCopies, "Number of physical register copies");
43 static RegisterScheduler
44 burrListDAGScheduler("list-burr",
45 "Bottom-up register reduction list scheduling",
46 createBURRListDAGScheduler);
47 static RegisterScheduler
48 sourceListDAGScheduler("source",
49 "Similar to list-burr but schedules in source "
50 "order when possible",
51 createSourceListDAGScheduler);
53 static RegisterScheduler
54 hybridListDAGScheduler("list-hybrid",
55 "Bottom-up register pressure aware list scheduling "
56 "which tries to balance latency and register pressure",
57 createHybridListDAGScheduler);
59 static RegisterScheduler
60 ILPListDAGScheduler("list-ilp",
61 "Bottom-up register pressure aware list scheduling "
62 "which tries to balance ILP and register pressure",
63 createILPListDAGScheduler);
65 static cl::opt<bool> DisableSchedCycles(
66 "disable-sched-cycles", cl::Hidden, cl::init(false),
67 cl::desc("Disable cycle-level precision during preRA scheduling"));
69 // Temporary sched=list-ilp flags until the heuristics are robust.
70 // Some options are also available under sched=list-hybrid.
71 static cl::opt<bool> DisableSchedRegPressure(
72 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
73 cl::desc("Disable regpressure priority in sched=list-ilp"));
74 static cl::opt<bool> DisableSchedLiveUses(
75 "disable-sched-live-uses", cl::Hidden, cl::init(true),
76 cl::desc("Disable live use priority in sched=list-ilp"));
77 static cl::opt<bool> DisableSchedVRegCycle(
78 "disable-sched-vrcycle", cl::Hidden, cl::init(false),
79 cl::desc("Disable virtual register cycle interference checks"));
80 static cl::opt<bool> DisableSchedPhysRegJoin(
81 "disable-sched-physreg-join", cl::Hidden, cl::init(false),
82 cl::desc("Disable physreg def-use affinity"));
83 static cl::opt<bool> DisableSchedStalls(
84 "disable-sched-stalls", cl::Hidden, cl::init(true),
85 cl::desc("Disable no-stall priority in sched=list-ilp"));
86 static cl::opt<bool> DisableSchedCriticalPath(
87 "disable-sched-critical-path", cl::Hidden, cl::init(false),
88 cl::desc("Disable critical path priority in sched=list-ilp"));
89 static cl::opt<bool> DisableSchedHeight(
90 "disable-sched-height", cl::Hidden, cl::init(false),
91 cl::desc("Disable scheduled-height priority in sched=list-ilp"));
92 static cl::opt<bool> Disable2AddrHack(
93 "disable-2addr-hack", cl::Hidden, cl::init(true),
94 cl::desc("Disable scheduler's two-address hack"));
96 static cl::opt<int> MaxReorderWindow(
97 "max-sched-reorder", cl::Hidden, cl::init(6),
98 cl::desc("Number of instructions to allow ahead of the critical path "
99 "in sched=list-ilp"));
101 static cl::opt<unsigned> AvgIPC(
102 "sched-avg-ipc", cl::Hidden, cl::init(1),
103 cl::desc("Average inst/cycle whan no target itinerary exists."));
106 //===----------------------------------------------------------------------===//
107 /// ScheduleDAGRRList - The actual register reduction list scheduler
108 /// implementation. This supports both top-down and bottom-up scheduling.
110 class ScheduleDAGRRList : public ScheduleDAGSDNodes {
112 /// NeedLatency - True if the scheduler will make use of latency information.
116 /// AvailableQueue - The priority queue to use for the available SUnits.
117 SchedulingPriorityQueue *AvailableQueue;
119 /// PendingQueue - This contains all of the instructions whose operands have
120 /// been issued, but their results are not ready yet (due to the latency of
121 /// the operation). Once the operands becomes available, the instruction is
122 /// added to the AvailableQueue.
123 std::vector<SUnit*> PendingQueue;
125 /// HazardRec - The hazard recognizer to use.
126 ScheduleHazardRecognizer *HazardRec;
128 /// CurCycle - The current scheduler state corresponds to this cycle.
131 /// MinAvailableCycle - Cycle of the soonest available instruction.
132 unsigned MinAvailableCycle;
134 /// IssueCount - Count instructions issued in this cycle
135 /// Currently valid only for bottom-up scheduling.
138 /// LiveRegDefs - A set of physical registers and their definition
139 /// that are "live". These nodes must be scheduled before any other nodes that
140 /// modifies the registers can be scheduled.
141 unsigned NumLiveRegs;
142 std::vector<SUnit*> LiveRegDefs;
143 std::vector<SUnit*> LiveRegGens;
145 /// Topo - A topological ordering for SUnits which permits fast IsReachable
146 /// and similar queries.
147 ScheduleDAGTopologicalSort Topo;
150 ScheduleDAGRRList(MachineFunction &mf, bool needlatency,
151 SchedulingPriorityQueue *availqueue,
152 CodeGenOpt::Level OptLevel)
153 : ScheduleDAGSDNodes(mf),
154 NeedLatency(needlatency), AvailableQueue(availqueue), CurCycle(0),
157 const TargetMachine &tm = mf.getTarget();
158 if (DisableSchedCycles || !NeedLatency)
159 HazardRec = new ScheduleHazardRecognizer();
161 HazardRec = tm.getInstrInfo()->CreateTargetHazardRecognizer(&tm, this);
164 ~ScheduleDAGRRList() {
166 delete AvailableQueue;
171 ScheduleHazardRecognizer *getHazardRec() { return HazardRec; }
173 /// IsReachable - Checks if SU is reachable from TargetSU.
174 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
175 return Topo.IsReachable(SU, TargetSU);
178 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
180 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
181 return Topo.WillCreateCycle(SU, TargetSU);
184 /// AddPred - adds a predecessor edge to SUnit SU.
185 /// This returns true if this is a new predecessor.
186 /// Updates the topological ordering if required.
187 void AddPred(SUnit *SU, const SDep &D) {
188 Topo.AddPred(SU, D.getSUnit());
192 /// RemovePred - removes a predecessor edge from SUnit SU.
193 /// This returns true if an edge was removed.
194 /// Updates the topological ordering if required.
195 void RemovePred(SUnit *SU, const SDep &D) {
196 Topo.RemovePred(SU, D.getSUnit());
201 bool isReady(SUnit *SU) {
202 return DisableSchedCycles || !AvailableQueue->hasReadyFilter() ||
203 AvailableQueue->isReady(SU);
206 void ReleasePred(SUnit *SU, const SDep *PredEdge);
207 void ReleasePredecessors(SUnit *SU);
208 void ReleasePending();
209 void AdvanceToCycle(unsigned NextCycle);
210 void AdvancePastStalls(SUnit *SU);
211 void EmitNode(SUnit *SU);
212 void ScheduleNodeBottomUp(SUnit*);
213 void CapturePred(SDep *PredEdge);
214 void UnscheduleNodeBottomUp(SUnit*);
215 void RestoreHazardCheckerBottomUp();
216 void BacktrackBottomUp(SUnit*, SUnit*);
217 SUnit *CopyAndMoveSuccessors(SUnit*);
218 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
219 const TargetRegisterClass*,
220 const TargetRegisterClass*,
221 SmallVector<SUnit*, 2>&);
222 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
224 SUnit *PickNodeToScheduleBottomUp();
225 void ListScheduleBottomUp();
227 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
228 /// Updates the topological ordering if required.
229 SUnit *CreateNewSUnit(SDNode *N) {
230 unsigned NumSUnits = SUnits.size();
231 SUnit *NewNode = NewSUnit(N);
232 // Update the topological ordering.
233 if (NewNode->NodeNum >= NumSUnits)
234 Topo.InitDAGTopologicalSorting();
238 /// CreateClone - Creates a new SUnit from an existing one.
239 /// Updates the topological ordering if required.
240 SUnit *CreateClone(SUnit *N) {
241 unsigned NumSUnits = SUnits.size();
242 SUnit *NewNode = Clone(N);
243 // Update the topological ordering.
244 if (NewNode->NodeNum >= NumSUnits)
245 Topo.InitDAGTopologicalSorting();
249 /// ForceUnitLatencies - Register-pressure-reducing scheduling doesn't
250 /// need actual latency information but the hybrid scheduler does.
251 bool ForceUnitLatencies() const {
255 } // end anonymous namespace
257 /// GetCostForDef - Looks up the register class and cost for a given definition.
258 /// Typically this just means looking up the representative register class,
259 /// but for untyped values (MVT::Untyped) it means inspecting the node's
260 /// opcode to determine what register class is being generated.
261 static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
262 const TargetLowering *TLI,
263 const TargetInstrInfo *TII,
264 const TargetRegisterInfo *TRI,
265 unsigned &RegClass, unsigned &Cost) {
266 EVT VT = RegDefPos.GetValue();
268 // Special handling for untyped values. These values can only come from
269 // the expansion of custom DAG-to-DAG patterns.
270 if (VT == MVT::Untyped) {
271 const SDNode *Node = RegDefPos.GetNode();
272 unsigned Opcode = Node->getMachineOpcode();
274 if (Opcode == TargetOpcode::REG_SEQUENCE) {
275 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
276 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
277 RegClass = RC->getID();
282 unsigned Idx = RegDefPos.GetIdx();
283 const MCInstrDesc Desc = TII->get(Opcode);
284 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
285 RegClass = RC->getID();
286 // FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
287 // better way to determine it.
290 RegClass = TLI->getRepRegClassFor(VT)->getID();
291 Cost = TLI->getRepRegClassCostFor(VT);
295 /// Schedule - Schedule the DAG using list scheduling.
296 void ScheduleDAGRRList::Schedule() {
298 << "********** List Scheduling BB#" << BB->getNumber()
299 << " '" << BB->getName() << "' **********\n");
303 MinAvailableCycle = DisableSchedCycles ? 0 : UINT_MAX;
305 // Allocate slots for each physical register, plus one for a special register
306 // to track the virtual resource of a calling sequence.
307 LiveRegDefs.resize(TRI->getNumRegs() + 1, NULL);
308 LiveRegGens.resize(TRI->getNumRegs() + 1, NULL);
310 // Build the scheduling graph.
311 BuildSchedGraph(NULL);
313 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
314 SUnits[su].dumpAll(this));
315 Topo.InitDAGTopologicalSorting();
317 AvailableQueue->initNodes(SUnits);
321 // Execute the actual scheduling loop.
322 ListScheduleBottomUp();
324 AvailableQueue->releaseState();
327 //===----------------------------------------------------------------------===//
328 // Bottom-Up Scheduling
329 //===----------------------------------------------------------------------===//
331 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
332 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
333 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
334 SUnit *PredSU = PredEdge->getSUnit();
337 if (PredSU->NumSuccsLeft == 0) {
338 dbgs() << "*** Scheduling failed! ***\n";
340 dbgs() << " has been released too many times!\n";
344 --PredSU->NumSuccsLeft;
346 if (!ForceUnitLatencies()) {
347 // Updating predecessor's height. This is now the cycle when the
348 // predecessor can be scheduled without causing a pipeline stall.
349 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
352 // If all the node's successors are scheduled, this node is ready
353 // to be scheduled. Ignore the special EntrySU node.
354 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
355 PredSU->isAvailable = true;
357 unsigned Height = PredSU->getHeight();
358 if (Height < MinAvailableCycle)
359 MinAvailableCycle = Height;
361 if (isReady(PredSU)) {
362 AvailableQueue->push(PredSU);
364 // CapturePred and others may have left the node in the pending queue, avoid
366 else if (!PredSU->isPending) {
367 PredSU->isPending = true;
368 PendingQueue.push_back(PredSU);
373 /// IsChainDependent - Test if Outer is reachable from Inner through
374 /// chain dependencies.
375 static bool IsChainDependent(SDNode *Outer, SDNode *Inner,
377 const TargetInstrInfo *TII) {
382 // For a TokenFactor, examine each operand. There may be multiple ways
383 // to get to the CALLSEQ_BEGIN, but we need to find the path with the
384 // most nesting in order to ensure that we find the corresponding match.
385 if (N->getOpcode() == ISD::TokenFactor) {
386 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
387 if (IsChainDependent(N->getOperand(i).getNode(), Inner, NestLevel, TII))
391 // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
392 if (N->isMachineOpcode()) {
393 if (N->getMachineOpcode() ==
394 (unsigned)TII->getCallFrameDestroyOpcode()) {
396 } else if (N->getMachineOpcode() ==
397 (unsigned)TII->getCallFrameSetupOpcode()) {
403 // Otherwise, find the chain and continue climbing.
404 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
405 if (N->getOperand(i).getValueType() == MVT::Other) {
406 N = N->getOperand(i).getNode();
407 goto found_chain_operand;
410 found_chain_operand:;
411 if (N->getOpcode() == ISD::EntryToken)
416 /// FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate
417 /// the corresponding (lowered) CALLSEQ_BEGIN node.
419 /// NestLevel and MaxNested are used in recursion to indcate the current level
420 /// of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum
421 /// level seen so far.
423 /// TODO: It would be better to give CALLSEQ_END an explicit operand to point
424 /// to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.
426 FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest,
427 const TargetInstrInfo *TII) {
429 // For a TokenFactor, examine each operand. There may be multiple ways
430 // to get to the CALLSEQ_BEGIN, but we need to find the path with the
431 // most nesting in order to ensure that we find the corresponding match.
432 if (N->getOpcode() == ISD::TokenFactor) {
434 unsigned BestMaxNest = MaxNest;
435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
436 unsigned MyNestLevel = NestLevel;
437 unsigned MyMaxNest = MaxNest;
438 if (SDNode *New = FindCallSeqStart(N->getOperand(i).getNode(),
439 MyNestLevel, MyMaxNest, TII))
440 if (!Best || (MyMaxNest > BestMaxNest)) {
442 BestMaxNest = MyMaxNest;
446 MaxNest = BestMaxNest;
449 // Check for a lowered CALLSEQ_BEGIN or CALLSEQ_END.
450 if (N->isMachineOpcode()) {
451 if (N->getMachineOpcode() ==
452 (unsigned)TII->getCallFrameDestroyOpcode()) {
454 MaxNest = std::max(MaxNest, NestLevel);
455 } else if (N->getMachineOpcode() ==
456 (unsigned)TII->getCallFrameSetupOpcode()) {
457 assert(NestLevel != 0);
463 // Otherwise, find the chain and continue climbing.
464 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
465 if (N->getOperand(i).getValueType() == MVT::Other) {
466 N = N->getOperand(i).getNode();
467 goto found_chain_operand;
470 found_chain_operand:;
471 if (N->getOpcode() == ISD::EntryToken)
476 /// Call ReleasePred for each predecessor, then update register live def/gen.
477 /// Always update LiveRegDefs for a register dependence even if the current SU
478 /// also defines the register. This effectively create one large live range
479 /// across a sequence of two-address node. This is important because the
480 /// entire chain must be scheduled together. Example:
483 /// flags = (2) addc flags
484 /// flags = (1) addc flags
488 /// LiveRegDefs[flags] = 3
489 /// LiveRegGens[flags] = 1
491 /// If (2) addc is unscheduled, then (1) addc must also be unscheduled to avoid
492 /// interference on flags.
493 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
494 // Bottom up: release predecessors
495 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
497 ReleasePred(SU, &*I);
498 if (I->isAssignedRegDep()) {
499 // This is a physical register dependency and it's impossible or
500 // expensive to copy the register. Make sure nothing that can
501 // clobber the register is scheduled between the predecessor and
503 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
504 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
505 "interference on register dependence");
506 LiveRegDefs[I->getReg()] = I->getSUnit();
507 if (!LiveRegGens[I->getReg()]) {
509 LiveRegGens[I->getReg()] = SU;
514 // If we're scheduling a lowered CALLSEQ_END, find the corresponding
515 // CALLSEQ_BEGIN. Inject an artificial physical register dependence between
516 // these nodes, to prevent other calls from being interscheduled with them.
517 unsigned CallResource = TRI->getNumRegs();
518 if (!LiveRegDefs[CallResource])
519 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode())
520 if (Node->isMachineOpcode() &&
521 Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
522 unsigned NestLevel = 0;
523 unsigned MaxNest = 0;
524 SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
526 SUnit *Def = &SUnits[N->getNodeId()];
528 LiveRegDefs[CallResource] = Def;
529 LiveRegGens[CallResource] = SU;
534 /// Check to see if any of the pending instructions are ready to issue. If
535 /// so, add them to the available queue.
536 void ScheduleDAGRRList::ReleasePending() {
537 if (DisableSchedCycles) {
538 assert(PendingQueue.empty() && "pending instrs not allowed in this mode");
542 // If the available queue is empty, it is safe to reset MinAvailableCycle.
543 if (AvailableQueue->empty())
544 MinAvailableCycle = UINT_MAX;
546 // Check to see if any of the pending instructions are ready to issue. If
547 // so, add them to the available queue.
548 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
549 unsigned ReadyCycle = PendingQueue[i]->getHeight();
550 if (ReadyCycle < MinAvailableCycle)
551 MinAvailableCycle = ReadyCycle;
553 if (PendingQueue[i]->isAvailable) {
554 if (!isReady(PendingQueue[i]))
556 AvailableQueue->push(PendingQueue[i]);
558 PendingQueue[i]->isPending = false;
559 PendingQueue[i] = PendingQueue.back();
560 PendingQueue.pop_back();
565 /// Move the scheduler state forward by the specified number of Cycles.
566 void ScheduleDAGRRList::AdvanceToCycle(unsigned NextCycle) {
567 if (NextCycle <= CurCycle)
571 AvailableQueue->setCurCycle(NextCycle);
572 if (!HazardRec->isEnabled()) {
573 // Bypass lots of virtual calls in case of long latency.
574 CurCycle = NextCycle;
577 for (; CurCycle != NextCycle; ++CurCycle) {
578 HazardRec->RecedeCycle();
581 // FIXME: Instead of visiting the pending Q each time, set a dirty flag on the
582 // available Q to release pending nodes at least once before popping.
586 /// Move the scheduler state forward until the specified node's dependents are
587 /// ready and can be scheduled with no resource conflicts.
588 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
589 if (DisableSchedCycles)
592 // FIXME: Nodes such as CopyFromReg probably should not advance the current
593 // cycle. Otherwise, we can wrongly mask real stalls. If the non-machine node
594 // has predecessors the cycle will be advanced when they are scheduled.
595 // But given the crude nature of modeling latency though such nodes, we
596 // currently need to treat these nodes like real instructions.
597 // if (!SU->getNode() || !SU->getNode()->isMachineOpcode()) return;
599 unsigned ReadyCycle = SU->getHeight();
601 // Bump CurCycle to account for latency. We assume the latency of other
602 // available instructions may be hidden by the stall (not a full pipe stall).
603 // This updates the hazard recognizer's cycle before reserving resources for
605 AdvanceToCycle(ReadyCycle);
607 // Calls are scheduled in their preceding cycle, so don't conflict with
608 // hazards from instructions after the call. EmitNode will reset the
609 // scoreboard state before emitting the call.
613 // FIXME: For resource conflicts in very long non-pipelined stages, we
614 // should probably skip ahead here to avoid useless scoreboard checks.
617 ScheduleHazardRecognizer::HazardType HT =
618 HazardRec->getHazardType(SU, -Stalls);
620 if (HT == ScheduleHazardRecognizer::NoHazard)
625 AdvanceToCycle(CurCycle + Stalls);
628 /// Record this SUnit in the HazardRecognizer.
629 /// Does not update CurCycle.
630 void ScheduleDAGRRList::EmitNode(SUnit *SU) {
631 if (!HazardRec->isEnabled())
634 // Check for phys reg copy.
638 switch (SU->getNode()->getOpcode()) {
640 assert(SU->getNode()->isMachineOpcode() &&
641 "This target-independent node should not be scheduled.");
643 case ISD::MERGE_VALUES:
644 case ISD::TokenFactor:
646 case ISD::CopyFromReg:
648 // Noops don't affect the scoreboard state. Copies are likely to be
652 // For inline asm, clear the pipeline state.
657 // Calls are scheduled with their preceding instructions. For bottom-up
658 // scheduling, clear the pipeline state before emitting.
662 HazardRec->EmitInstruction(SU);
665 static void resetVRegCycle(SUnit *SU);
667 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
668 /// count of its predecessors. If a predecessor pending count is zero, add it to
669 /// the Available queue.
670 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
671 DEBUG(dbgs() << "\n*** Scheduling [" << CurCycle << "]: ");
672 DEBUG(SU->dump(this));
675 if (CurCycle < SU->getHeight())
676 DEBUG(dbgs() << " Height [" << SU->getHeight()
677 << "] pipeline stall!\n");
680 // FIXME: Do not modify node height. It may interfere with
681 // backtracking. Instead add a "ready cycle" to SUnit. Before scheduling the
682 // node its ready cycle can aid heuristics, and after scheduling it can
683 // indicate the scheduled cycle.
684 SU->setHeightToAtLeast(CurCycle);
686 // Reserve resources for the scheduled intruction.
689 Sequence.push_back(SU);
691 AvailableQueue->ScheduledNode(SU);
693 // If HazardRec is disabled, and each inst counts as one cycle, then
694 // advance CurCycle before ReleasePredecessors to avoid useless pushes to
695 // PendingQueue for schedulers that implement HasReadyFilter.
696 if (!HazardRec->isEnabled() && AvgIPC < 2)
697 AdvanceToCycle(CurCycle + 1);
699 // Update liveness of predecessors before successors to avoid treating a
700 // two-address node as a live range def.
701 ReleasePredecessors(SU);
703 // Release all the implicit physical register defs that are live.
704 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
706 // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
707 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
708 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
710 LiveRegDefs[I->getReg()] = NULL;
711 LiveRegGens[I->getReg()] = NULL;
714 // Release the special call resource dependence, if this is the beginning
716 unsigned CallResource = TRI->getNumRegs();
717 if (LiveRegDefs[CallResource] == SU)
718 for (const SDNode *SUNode = SU->getNode(); SUNode;
719 SUNode = SUNode->getGluedNode()) {
720 if (SUNode->isMachineOpcode() &&
721 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
722 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
724 LiveRegDefs[CallResource] = NULL;
725 LiveRegGens[CallResource] = NULL;
731 SU->isScheduled = true;
733 // Conditions under which the scheduler should eagerly advance the cycle:
734 // (1) No available instructions
735 // (2) All pipelines full, so available instructions must have hazards.
737 // If HazardRec is disabled, the cycle was pre-advanced before calling
738 // ReleasePredecessors. In that case, IssueCount should remain 0.
740 // Check AvailableQueue after ReleasePredecessors in case of zero latency.
741 if (HazardRec->isEnabled() || AvgIPC > 1) {
742 if (SU->getNode() && SU->getNode()->isMachineOpcode())
744 if ((HazardRec->isEnabled() && HazardRec->atIssueLimit())
745 || (!HazardRec->isEnabled() && IssueCount == AvgIPC))
746 AdvanceToCycle(CurCycle + 1);
750 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
751 /// unscheduled, incrcease the succ left count of its predecessors. Remove
752 /// them from AvailableQueue if necessary.
753 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
754 SUnit *PredSU = PredEdge->getSUnit();
755 if (PredSU->isAvailable) {
756 PredSU->isAvailable = false;
757 if (!PredSU->isPending)
758 AvailableQueue->remove(PredSU);
761 assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
762 ++PredSU->NumSuccsLeft;
765 /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
766 /// its predecessor states to reflect the change.
767 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
768 DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: ");
769 DEBUG(SU->dump(this));
771 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
774 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){
775 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
776 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
777 "Physical register dependency violated?");
779 LiveRegDefs[I->getReg()] = NULL;
780 LiveRegGens[I->getReg()] = NULL;
784 // Reclaim the special call resource dependence, if this is the beginning
786 unsigned CallResource = TRI->getNumRegs();
787 for (const SDNode *SUNode = SU->getNode(); SUNode;
788 SUNode = SUNode->getGluedNode()) {
789 if (SUNode->isMachineOpcode() &&
790 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameSetupOpcode()) {
792 LiveRegDefs[CallResource] = SU;
793 LiveRegGens[CallResource] = NULL;
797 // Release the special call resource dependence, if this is the end
799 if (LiveRegGens[CallResource] == SU)
800 for (const SDNode *SUNode = SU->getNode(); SUNode;
801 SUNode = SUNode->getGluedNode()) {
802 if (SUNode->isMachineOpcode() &&
803 SUNode->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
804 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
806 LiveRegDefs[CallResource] = NULL;
807 LiveRegGens[CallResource] = NULL;
811 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
813 if (I->isAssignedRegDep()) {
814 // This becomes the nearest def. Note that an earlier def may still be
815 // pending if this is a two-address node.
816 LiveRegDefs[I->getReg()] = SU;
817 if (!LiveRegDefs[I->getReg()]) {
820 if (LiveRegGens[I->getReg()] == NULL ||
821 I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
822 LiveRegGens[I->getReg()] = I->getSUnit();
825 if (SU->getHeight() < MinAvailableCycle)
826 MinAvailableCycle = SU->getHeight();
828 SU->setHeightDirty();
829 SU->isScheduled = false;
830 SU->isAvailable = true;
831 if (!DisableSchedCycles && AvailableQueue->hasReadyFilter()) {
832 // Don't make available until backtracking is complete.
833 SU->isPending = true;
834 PendingQueue.push_back(SU);
837 AvailableQueue->push(SU);
839 AvailableQueue->UnscheduledNode(SU);
842 /// After backtracking, the hazard checker needs to be restored to a state
843 /// corresponding the the current cycle.
844 void ScheduleDAGRRList::RestoreHazardCheckerBottomUp() {
847 unsigned LookAhead = std::min((unsigned)Sequence.size(),
848 HazardRec->getMaxLookAhead());
852 std::vector<SUnit*>::const_iterator I = (Sequence.end() - LookAhead);
853 unsigned HazardCycle = (*I)->getHeight();
854 for (std::vector<SUnit*>::const_iterator E = Sequence.end(); I != E; ++I) {
856 for (; SU->getHeight() > HazardCycle; ++HazardCycle) {
857 HazardRec->RecedeCycle();
863 /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
864 /// BTCycle in order to schedule a specific node.
865 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
866 SUnit *OldSU = Sequence.back();
869 if (SU->isSucc(OldSU))
870 // Don't try to remove SU from AvailableQueue.
871 SU->isAvailable = false;
872 // FIXME: use ready cycle instead of height
873 CurCycle = OldSU->getHeight();
874 UnscheduleNodeBottomUp(OldSU);
875 AvailableQueue->setCurCycle(CurCycle);
878 OldSU = Sequence.back();
881 assert(!SU->isSucc(OldSU) && "Something is wrong!");
883 RestoreHazardCheckerBottomUp();
890 static bool isOperandOf(const SUnit *SU, SDNode *N) {
891 for (const SDNode *SUNode = SU->getNode(); SUNode;
892 SUNode = SUNode->getGluedNode()) {
893 if (SUNode->isOperandOf(N))
899 /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
900 /// successors to the newly created node.
901 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
902 SDNode *N = SU->getNode();
906 if (SU->getNode()->getGluedNode())
910 bool TryUnfold = false;
911 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
912 EVT VT = N->getValueType(i);
915 else if (VT == MVT::Other)
918 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
919 const SDValue &Op = N->getOperand(i);
920 EVT VT = Op.getNode()->getValueType(Op.getResNo());
926 SmallVector<SDNode*, 2> NewNodes;
927 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
930 // unfolding an x86 DEC64m operation results in store, dec, load which
931 // can't be handled here so quit
932 if (NewNodes.size() == 3)
935 DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n");
936 assert(NewNodes.size() == 2 && "Expected a load folding node!");
939 SDNode *LoadNode = NewNodes[0];
940 unsigned NumVals = N->getNumValues();
941 unsigned OldNumVals = SU->getNode()->getNumValues();
942 for (unsigned i = 0; i != NumVals; ++i)
943 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
944 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
945 SDValue(LoadNode, 1));
947 // LoadNode may already exist. This can happen when there is another
948 // load from the same location and producing the same type of value
949 // but it has different alignment or volatileness.
950 bool isNewLoad = true;
952 if (LoadNode->getNodeId() != -1) {
953 LoadSU = &SUnits[LoadNode->getNodeId()];
956 LoadSU = CreateNewSUnit(LoadNode);
957 LoadNode->setNodeId(LoadSU->NodeNum);
959 InitNumRegDefsLeft(LoadSU);
960 ComputeLatency(LoadSU);
963 SUnit *NewSU = CreateNewSUnit(N);
964 assert(N->getNodeId() == -1 && "Node already inserted!");
965 N->setNodeId(NewSU->NodeNum);
967 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
968 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
969 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
970 NewSU->isTwoAddress = true;
974 if (MCID.isCommutable())
975 NewSU->isCommutable = true;
977 InitNumRegDefsLeft(NewSU);
978 ComputeLatency(NewSU);
980 // Record all the edges to and from the old SU, by category.
981 SmallVector<SDep, 4> ChainPreds;
982 SmallVector<SDep, 4> ChainSuccs;
983 SmallVector<SDep, 4> LoadPreds;
984 SmallVector<SDep, 4> NodePreds;
985 SmallVector<SDep, 4> NodeSuccs;
986 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
989 ChainPreds.push_back(*I);
990 else if (isOperandOf(I->getSUnit(), LoadNode))
991 LoadPreds.push_back(*I);
993 NodePreds.push_back(*I);
995 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
998 ChainSuccs.push_back(*I);
1000 NodeSuccs.push_back(*I);
1003 // Now assign edges to the newly-created nodes.
1004 for (unsigned i = 0, e = ChainPreds.size(); i != e; ++i) {
1005 const SDep &Pred = ChainPreds[i];
1006 RemovePred(SU, Pred);
1008 AddPred(LoadSU, Pred);
1010 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
1011 const SDep &Pred = LoadPreds[i];
1012 RemovePred(SU, Pred);
1014 AddPred(LoadSU, Pred);
1016 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
1017 const SDep &Pred = NodePreds[i];
1018 RemovePred(SU, Pred);
1019 AddPred(NewSU, Pred);
1021 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
1022 SDep D = NodeSuccs[i];
1023 SUnit *SuccDep = D.getSUnit();
1025 RemovePred(SuccDep, D);
1027 AddPred(SuccDep, D);
1028 // Balance register pressure.
1029 if (AvailableQueue->tracksRegPressure() && SuccDep->isScheduled
1030 && !D.isCtrl() && NewSU->NumRegDefsLeft > 0)
1031 --NewSU->NumRegDefsLeft;
1033 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
1034 SDep D = ChainSuccs[i];
1035 SUnit *SuccDep = D.getSUnit();
1037 RemovePred(SuccDep, D);
1040 AddPred(SuccDep, D);
1044 // Add a data dependency to reflect that NewSU reads the value defined
1046 AddPred(NewSU, SDep(LoadSU, SDep::Data, LoadSU->Latency));
1049 AvailableQueue->addNode(LoadSU);
1050 AvailableQueue->addNode(NewSU);
1054 if (NewSU->NumSuccsLeft == 0) {
1055 NewSU->isAvailable = true;
1061 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n");
1062 NewSU = CreateClone(SU);
1064 // New SUnit has the exact same predecessors.
1065 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1067 if (!I->isArtificial())
1070 // Only copy scheduled successors. Cut them from old node's successor
1071 // list and move them over.
1072 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1073 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1075 if (I->isArtificial())
1077 SUnit *SuccSU = I->getSUnit();
1078 if (SuccSU->isScheduled) {
1083 DelDeps.push_back(std::make_pair(SuccSU, D));
1086 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
1087 RemovePred(DelDeps[i].first, DelDeps[i].second);
1089 AvailableQueue->updateNode(SU);
1090 AvailableQueue->addNode(NewSU);
1096 /// InsertCopiesAndMoveSuccs - Insert register copies and move all
1097 /// scheduled successors of the given SUnit to the last copy.
1098 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
1099 const TargetRegisterClass *DestRC,
1100 const TargetRegisterClass *SrcRC,
1101 SmallVector<SUnit*, 2> &Copies) {
1102 SUnit *CopyFromSU = CreateNewSUnit(NULL);
1103 CopyFromSU->CopySrcRC = SrcRC;
1104 CopyFromSU->CopyDstRC = DestRC;
1106 SUnit *CopyToSU = CreateNewSUnit(NULL);
1107 CopyToSU->CopySrcRC = DestRC;
1108 CopyToSU->CopyDstRC = SrcRC;
1110 // Only copy scheduled successors. Cut them from old node's successor
1111 // list and move them over.
1112 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
1113 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1115 if (I->isArtificial())
1117 SUnit *SuccSU = I->getSUnit();
1118 if (SuccSU->isScheduled) {
1120 D.setSUnit(CopyToSU);
1122 DelDeps.push_back(std::make_pair(SuccSU, *I));
1125 // Avoid scheduling the def-side copy before other successors. Otherwise
1126 // we could introduce another physreg interference on the copy and
1127 // continue inserting copies indefinitely.
1128 SDep D(CopyFromSU, SDep::Order, /*Latency=*/0,
1129 /*Reg=*/0, /*isNormalMemory=*/false,
1130 /*isMustAlias=*/false, /*isArtificial=*/true);
1134 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
1135 RemovePred(DelDeps[i].first, DelDeps[i].second);
1137 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg));
1138 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0));
1140 AvailableQueue->updateNode(SU);
1141 AvailableQueue->addNode(CopyFromSU);
1142 AvailableQueue->addNode(CopyToSU);
1143 Copies.push_back(CopyFromSU);
1144 Copies.push_back(CopyToSU);
1149 /// getPhysicalRegisterVT - Returns the ValueType of the physical register
1150 /// definition of the specified node.
1151 /// FIXME: Move to SelectionDAG?
1152 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
1153 const TargetInstrInfo *TII) {
1154 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1155 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
1156 unsigned NumRes = MCID.getNumDefs();
1157 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1162 return N->getValueType(NumRes);
1165 /// CheckForLiveRegDef - Return true and update live register vector if the
1166 /// specified register def of the specified SUnit clobbers any "live" registers.
1167 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
1168 std::vector<SUnit*> &LiveRegDefs,
1169 SmallSet<unsigned, 4> &RegAdded,
1170 SmallVector<unsigned, 4> &LRegs,
1171 const TargetRegisterInfo *TRI) {
1172 for (const unsigned *AliasI = TRI->getOverlaps(Reg); *AliasI; ++AliasI) {
1174 // Check if Ref is live.
1175 if (!LiveRegDefs[*AliasI]) continue;
1177 // Allow multiple uses of the same def.
1178 if (LiveRegDefs[*AliasI] == SU) continue;
1180 // Add Reg to the set of interfering live regs.
1181 if (RegAdded.insert(*AliasI)) {
1182 LRegs.push_back(*AliasI);
1187 /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
1188 /// scheduling of the given node to satisfy live physical register dependencies.
1189 /// If the specific node is the last one that's available to schedule, do
1190 /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
1191 bool ScheduleDAGRRList::
1192 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {
1193 if (NumLiveRegs == 0)
1196 SmallSet<unsigned, 4> RegAdded;
1197 // If this node would clobber any "live" register, then it's not ready.
1199 // If SU is the currently live definition of the same register that it uses,
1200 // then we are free to schedule it.
1201 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1203 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
1204 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
1205 RegAdded, LRegs, TRI);
1208 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
1209 if (Node->getOpcode() == ISD::INLINEASM) {
1210 // Inline asm can clobber physical defs.
1211 unsigned NumOps = Node->getNumOperands();
1212 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1213 --NumOps; // Ignore the glue operand.
1215 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1217 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1218 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1220 ++i; // Skip the ID value.
1221 if (InlineAsm::isRegDefKind(Flags) ||
1222 InlineAsm::isRegDefEarlyClobberKind(Flags) ||
1223 InlineAsm::isClobberKind(Flags)) {
1224 // Check for def of register or earlyclobber register.
1225 for (; NumVals; --NumVals, ++i) {
1226 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1227 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1228 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1236 if (!Node->isMachineOpcode())
1238 // If we're in the middle of scheduling a call, don't begin scheduling
1239 // another call. Also, don't allow any physical registers to be live across
1241 if (Node->getMachineOpcode() == (unsigned)TII->getCallFrameDestroyOpcode()) {
1242 // Check the special calling-sequence resource.
1243 unsigned CallResource = TRI->getNumRegs();
1244 if (LiveRegDefs[CallResource]) {
1245 SDNode *Gen = LiveRegGens[CallResource]->getNode();
1246 while (SDNode *Glued = Gen->getGluedNode())
1248 if (!IsChainDependent(Gen, Node, 0, TII) && RegAdded.insert(CallResource))
1249 LRegs.push_back(CallResource);
1252 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
1253 if (!MCID.ImplicitDefs)
1255 for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg)
1256 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1259 return !LRegs.empty();
1262 /// Return a node that can be scheduled in this cycle. Requirements:
1263 /// (1) Ready: latency has been satisfied
1264 /// (2) No Hazards: resources are available
1265 /// (3) No Interferences: may unschedule to break register interferences.
1266 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
1267 SmallVector<SUnit*, 4> Interferences;
1268 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
1270 SUnit *CurSU = AvailableQueue->pop();
1272 SmallVector<unsigned, 4> LRegs;
1273 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
1275 LRegsMap.insert(std::make_pair(CurSU, LRegs));
1277 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
1278 Interferences.push_back(CurSU);
1279 CurSU = AvailableQueue->pop();
1282 // Add the nodes that aren't ready back onto the available list.
1283 for (unsigned i = 0, e = Interferences.size(); i != e; ++i) {
1284 Interferences[i]->isPending = false;
1285 assert(Interferences[i]->isAvailable && "must still be available");
1286 AvailableQueue->push(Interferences[i]);
1291 // All candidates are delayed due to live physical reg dependencies.
1292 // Try backtracking, code duplication, or inserting cross class copies
1294 for (unsigned i = 0, e = Interferences.size(); i != e; ++i) {
1295 SUnit *TrySU = Interferences[i];
1296 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
1298 // Try unscheduling up to the point where it's safe to schedule
1301 unsigned LiveCycle = UINT_MAX;
1302 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) {
1303 unsigned Reg = LRegs[j];
1304 if (LiveRegGens[Reg]->getHeight() < LiveCycle) {
1305 BtSU = LiveRegGens[Reg];
1306 LiveCycle = BtSU->getHeight();
1309 if (!WillCreateCycle(TrySU, BtSU)) {
1310 BacktrackBottomUp(TrySU, BtSU);
1312 // Force the current node to be scheduled before the node that
1313 // requires the physical reg dep.
1314 if (BtSU->isAvailable) {
1315 BtSU->isAvailable = false;
1316 if (!BtSU->isPending)
1317 AvailableQueue->remove(BtSU);
1319 AddPred(TrySU, SDep(BtSU, SDep::Order, /*Latency=*/1,
1320 /*Reg=*/0, /*isNormalMemory=*/false,
1321 /*isMustAlias=*/false, /*isArtificial=*/true));
1323 // If one or more successors has been unscheduled, then the current
1324 // node is no longer avaialable. Schedule a successor that's now
1325 // available instead.
1326 if (!TrySU->isAvailable) {
1327 CurSU = AvailableQueue->pop();
1331 TrySU->isPending = false;
1332 Interferences.erase(Interferences.begin()+i);
1339 // Can't backtrack. If it's too expensive to copy the value, then try
1340 // duplicate the nodes that produces these "too expensive to copy"
1341 // values to break the dependency. In case even that doesn't work,
1342 // insert cross class copies.
1343 // If it's not too expensive, i.e. cost != -1, issue copies.
1344 SUnit *TrySU = Interferences[0];
1345 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
1346 assert(LRegs.size() == 1 && "Can't handle this yet!");
1347 unsigned Reg = LRegs[0];
1348 SUnit *LRDef = LiveRegDefs[Reg];
1349 EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
1350 const TargetRegisterClass *RC =
1351 TRI->getMinimalPhysRegClass(Reg, VT);
1352 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
1354 // If cross copy register class is the same as RC, then it must be possible
1355 // copy the value directly. Do not try duplicate the def.
1356 // If cross copy register class is not the same as RC, then it's possible to
1357 // copy the value but it require cross register class copies and it is
1359 // If cross copy register class is null, then it's not possible to copy
1360 // the value at all.
1363 NewDef = CopyAndMoveSuccessors(LRDef);
1364 if (!DestRC && !NewDef)
1365 report_fatal_error("Can't handle live physical register dependency!");
1368 // Issue copies, these can be expensive cross register class copies.
1369 SmallVector<SUnit*, 2> Copies;
1370 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
1371 DEBUG(dbgs() << " Adding an edge from SU #" << TrySU->NodeNum
1372 << " to SU #" << Copies.front()->NodeNum << "\n");
1373 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
1374 /*Reg=*/0, /*isNormalMemory=*/false,
1375 /*isMustAlias=*/false,
1376 /*isArtificial=*/true));
1377 NewDef = Copies.back();
1380 DEBUG(dbgs() << " Adding an edge from SU #" << NewDef->NodeNum
1381 << " to SU #" << TrySU->NodeNum << "\n");
1382 LiveRegDefs[Reg] = NewDef;
1383 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
1384 /*Reg=*/0, /*isNormalMemory=*/false,
1385 /*isMustAlias=*/false,
1386 /*isArtificial=*/true));
1387 TrySU->isAvailable = false;
1391 assert(CurSU && "Unable to resolve live physical register dependencies!");
1393 // Add the nodes that aren't ready back onto the available list.
1394 for (unsigned i = 0, e = Interferences.size(); i != e; ++i) {
1395 Interferences[i]->isPending = false;
1396 // May no longer be available due to backtracking.
1397 if (Interferences[i]->isAvailable) {
1398 AvailableQueue->push(Interferences[i]);
1404 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
1406 void ScheduleDAGRRList::ListScheduleBottomUp() {
1407 // Release any predecessors of the special Exit node.
1408 ReleasePredecessors(&ExitSU);
1410 // Add root to Available queue.
1411 if (!SUnits.empty()) {
1412 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
1413 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
1414 RootSU->isAvailable = true;
1415 AvailableQueue->push(RootSU);
1418 // While Available queue is not empty, grab the node with the highest
1419 // priority. If it is not ready put it back. Schedule the node.
1420 Sequence.reserve(SUnits.size());
1421 while (!AvailableQueue->empty()) {
1422 DEBUG(dbgs() << "\nExamining Available:\n";
1423 AvailableQueue->dump(this));
1425 // Pick the best node to schedule taking all constraints into
1427 SUnit *SU = PickNodeToScheduleBottomUp();
1429 AdvancePastStalls(SU);
1431 ScheduleNodeBottomUp(SU);
1433 while (AvailableQueue->empty() && !PendingQueue.empty()) {
1434 // Advance the cycle to free resources. Skip ahead to the next ready SU.
1435 assert(MinAvailableCycle < UINT_MAX && "MinAvailableCycle uninitialized");
1436 AdvanceToCycle(std::max(CurCycle + 1, MinAvailableCycle));
1440 // Reverse the order if it is bottom up.
1441 std::reverse(Sequence.begin(), Sequence.end());
1444 VerifySchedule(/*isBottomUp=*/true);
1448 //===----------------------------------------------------------------------===//
1449 // RegReductionPriorityQueue Definition
1450 //===----------------------------------------------------------------------===//
1452 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
1453 // to reduce register pressure.
1456 class RegReductionPQBase;
1458 struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1459 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
1464 struct reverse_sort : public queue_sort {
1466 reverse_sort(SF &sf) : SortFunc(sf) {}
1467 reverse_sort(const reverse_sort &RHS) : SortFunc(RHS.SortFunc) {}
1469 bool operator()(SUnit* left, SUnit* right) const {
1470 // reverse left/right rather than simply !SortFunc(left, right)
1471 // to expose different paths in the comparison logic.
1472 return SortFunc(right, left);
1477 /// bu_ls_rr_sort - Priority function for bottom up register pressure
1478 // reduction scheduler.
1479 struct bu_ls_rr_sort : public queue_sort {
1482 HasReadyFilter = false
1485 RegReductionPQBase *SPQ;
1486 bu_ls_rr_sort(RegReductionPQBase *spq) : SPQ(spq) {}
1487 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
1489 bool operator()(SUnit* left, SUnit* right) const;
1492 // src_ls_rr_sort - Priority function for source order scheduler.
1493 struct src_ls_rr_sort : public queue_sort {
1496 HasReadyFilter = false
1499 RegReductionPQBase *SPQ;
1500 src_ls_rr_sort(RegReductionPQBase *spq)
1502 src_ls_rr_sort(const src_ls_rr_sort &RHS)
1505 bool operator()(SUnit* left, SUnit* right) const;
1508 // hybrid_ls_rr_sort - Priority function for hybrid scheduler.
1509 struct hybrid_ls_rr_sort : public queue_sort {
1512 HasReadyFilter = false
1515 RegReductionPQBase *SPQ;
1516 hybrid_ls_rr_sort(RegReductionPQBase *spq)
1518 hybrid_ls_rr_sort(const hybrid_ls_rr_sort &RHS)
1521 bool isReady(SUnit *SU, unsigned CurCycle) const;
1523 bool operator()(SUnit* left, SUnit* right) const;
1526 // ilp_ls_rr_sort - Priority function for ILP (instruction level parallelism)
1528 struct ilp_ls_rr_sort : public queue_sort {
1531 HasReadyFilter = false
1534 RegReductionPQBase *SPQ;
1535 ilp_ls_rr_sort(RegReductionPQBase *spq)
1537 ilp_ls_rr_sort(const ilp_ls_rr_sort &RHS)
1540 bool isReady(SUnit *SU, unsigned CurCycle) const;
1542 bool operator()(SUnit* left, SUnit* right) const;
1545 class RegReductionPQBase : public SchedulingPriorityQueue {
1547 std::vector<SUnit*> Queue;
1548 unsigned CurQueueId;
1549 bool TracksRegPressure;
1551 // SUnits - The SUnits for the current graph.
1552 std::vector<SUnit> *SUnits;
1554 MachineFunction &MF;
1555 const TargetInstrInfo *TII;
1556 const TargetRegisterInfo *TRI;
1557 const TargetLowering *TLI;
1558 ScheduleDAGRRList *scheduleDAG;
1560 // SethiUllmanNumbers - The SethiUllman number for each node.
1561 std::vector<unsigned> SethiUllmanNumbers;
1563 /// RegPressure - Tracking current reg pressure per register class.
1565 std::vector<unsigned> RegPressure;
1567 /// RegLimit - Tracking the number of allocatable registers per register
1569 std::vector<unsigned> RegLimit;
1572 RegReductionPQBase(MachineFunction &mf,
1573 bool hasReadyFilter,
1575 const TargetInstrInfo *tii,
1576 const TargetRegisterInfo *tri,
1577 const TargetLowering *tli)
1578 : SchedulingPriorityQueue(hasReadyFilter),
1579 CurQueueId(0), TracksRegPressure(tracksrp),
1580 MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
1581 if (TracksRegPressure) {
1582 unsigned NumRC = TRI->getNumRegClasses();
1583 RegLimit.resize(NumRC);
1584 RegPressure.resize(NumRC);
1585 std::fill(RegLimit.begin(), RegLimit.end(), 0);
1586 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1587 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
1588 E = TRI->regclass_end(); I != E; ++I)
1589 RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF);
1593 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
1594 scheduleDAG = scheduleDag;
1597 ScheduleHazardRecognizer* getHazardRec() {
1598 return scheduleDAG->getHazardRec();
1601 void initNodes(std::vector<SUnit> &sunits);
1603 void addNode(const SUnit *SU);
1605 void updateNode(const SUnit *SU);
1607 void releaseState() {
1609 SethiUllmanNumbers.clear();
1610 std::fill(RegPressure.begin(), RegPressure.end(), 0);
1613 unsigned getNodePriority(const SUnit *SU) const;
1615 unsigned getNodeOrdering(const SUnit *SU) const {
1616 if (!SU->getNode()) return 0;
1618 return scheduleDAG->DAG->GetOrdering(SU->getNode());
1621 bool empty() const { return Queue.empty(); }
1623 void push(SUnit *U) {
1624 assert(!U->NodeQueueId && "Node in the queue already");
1625 U->NodeQueueId = ++CurQueueId;
1629 void remove(SUnit *SU) {
1630 assert(!Queue.empty() && "Queue is empty!");
1631 assert(SU->NodeQueueId != 0 && "Not in queue!");
1632 std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(),
1634 if (I != prior(Queue.end()))
1635 std::swap(*I, Queue.back());
1637 SU->NodeQueueId = 0;
1640 bool tracksRegPressure() const { return TracksRegPressure; }
1642 void dumpRegPressure() const;
1644 bool HighRegPressure(const SUnit *SU) const;
1646 bool MayReduceRegPressure(SUnit *SU) const;
1648 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1650 void ScheduledNode(SUnit *SU);
1652 void UnscheduledNode(SUnit *SU);
1655 bool canClobber(const SUnit *SU, const SUnit *Op);
1656 void AddPseudoTwoAddrDeps();
1657 void PrescheduleNodesWithMultipleUses();
1658 void CalculateSethiUllmanNumbers();
1662 static SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) {
1663 std::vector<SUnit *>::iterator Best = Q.begin();
1664 for (std::vector<SUnit *>::iterator I = llvm::next(Q.begin()),
1665 E = Q.end(); I != E; ++I)
1666 if (Picker(*Best, *I))
1669 if (Best != prior(Q.end()))
1670 std::swap(*Best, Q.back());
1676 SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) {
1678 if (DAG->StressSched) {
1679 reverse_sort<SF> RPicker(Picker);
1680 return popFromQueueImpl(Q, RPicker);
1684 return popFromQueueImpl(Q, Picker);
1688 class RegReductionPriorityQueue : public RegReductionPQBase {
1692 RegReductionPriorityQueue(MachineFunction &mf,
1694 const TargetInstrInfo *tii,
1695 const TargetRegisterInfo *tri,
1696 const TargetLowering *tli)
1697 : RegReductionPQBase(mf, SF::HasReadyFilter, tracksrp, tii, tri, tli),
1700 bool isBottomUp() const { return SF::IsBottomUp; }
1702 bool isReady(SUnit *U) const {
1703 return Picker.HasReadyFilter && Picker.isReady(U, getCurCycle());
1707 if (Queue.empty()) return NULL;
1709 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG);
1714 void dump(ScheduleDAG *DAG) const {
1715 // Emulate pop() without clobbering NodeQueueIds.
1716 std::vector<SUnit*> DumpQueue = Queue;
1717 SF DumpPicker = Picker;
1718 while (!DumpQueue.empty()) {
1719 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG);
1720 dbgs() << "Height " << SU->getHeight() << ": ";
1726 typedef RegReductionPriorityQueue<bu_ls_rr_sort>
1727 BURegReductionPriorityQueue;
1729 typedef RegReductionPriorityQueue<src_ls_rr_sort>
1730 SrcRegReductionPriorityQueue;
1732 typedef RegReductionPriorityQueue<hybrid_ls_rr_sort>
1733 HybridBURRPriorityQueue;
1735 typedef RegReductionPriorityQueue<ilp_ls_rr_sort>
1736 ILPBURRPriorityQueue;
1737 } // end anonymous namespace
1739 //===----------------------------------------------------------------------===//
1740 // Static Node Priority for Register Pressure Reduction
1741 //===----------------------------------------------------------------------===//
1743 // Check for special nodes that bypass scheduling heuristics.
1744 // Currently this pushes TokenFactor nodes down, but may be used for other
1745 // pseudo-ops as well.
1747 // Return -1 to schedule right above left, 1 for left above right.
1748 // Return 0 if no bias exists.
1749 static int checkSpecialNodes(const SUnit *left, const SUnit *right) {
1750 bool LSchedLow = left->isScheduleLow;
1751 bool RSchedLow = right->isScheduleLow;
1752 if (LSchedLow != RSchedLow)
1753 return LSchedLow < RSchedLow ? 1 : -1;
1757 /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
1758 /// Smaller number is the higher priority.
1760 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
1761 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
1762 if (SethiUllmanNumber != 0)
1763 return SethiUllmanNumber;
1766 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1768 if (I->isCtrl()) continue; // ignore chain preds
1769 SUnit *PredSU = I->getSUnit();
1770 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
1771 if (PredSethiUllman > SethiUllmanNumber) {
1772 SethiUllmanNumber = PredSethiUllman;
1774 } else if (PredSethiUllman == SethiUllmanNumber)
1778 SethiUllmanNumber += Extra;
1780 if (SethiUllmanNumber == 0)
1781 SethiUllmanNumber = 1;
1783 return SethiUllmanNumber;
1786 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1787 /// scheduling units.
1788 void RegReductionPQBase::CalculateSethiUllmanNumbers() {
1789 SethiUllmanNumbers.assign(SUnits->size(), 0);
1791 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1792 CalcNodeSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
1795 void RegReductionPQBase::addNode(const SUnit *SU) {
1796 unsigned SUSize = SethiUllmanNumbers.size();
1797 if (SUnits->size() > SUSize)
1798 SethiUllmanNumbers.resize(SUSize*2, 0);
1799 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1802 void RegReductionPQBase::updateNode(const SUnit *SU) {
1803 SethiUllmanNumbers[SU->NodeNum] = 0;
1804 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1807 // Lower priority means schedule further down. For bottom-up scheduling, lower
1808 // priority SUs are scheduled before higher priority SUs.
1809 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
1810 assert(SU->NodeNum < SethiUllmanNumbers.size());
1811 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
1812 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1813 // CopyToReg should be close to its uses to facilitate coalescing and
1816 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1817 Opc == TargetOpcode::SUBREG_TO_REG ||
1818 Opc == TargetOpcode::INSERT_SUBREG)
1819 // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
1820 // close to their uses to facilitate coalescing.
1822 if (SU->NumSuccs == 0 && SU->NumPreds != 0)
1823 // If SU does not have a register use, i.e. it doesn't produce a value
1824 // that would be consumed (e.g. store), then it terminates a chain of
1825 // computation. Give it a large SethiUllman number so it will be
1826 // scheduled right before its predecessors that it doesn't lengthen
1827 // their live ranges.
1829 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
1830 // If SU does not have a register def, schedule it close to its uses
1831 // because it does not lengthen any live ranges.
1834 return SethiUllmanNumbers[SU->NodeNum];
1836 unsigned Priority = SethiUllmanNumbers[SU->NodeNum];
1838 // FIXME: This assumes all of the defs are used as call operands.
1839 int NP = (int)Priority - SU->getNode()->getNumValues();
1840 return (NP > 0) ? NP : 0;
1846 //===----------------------------------------------------------------------===//
1847 // Register Pressure Tracking
1848 //===----------------------------------------------------------------------===//
1850 void RegReductionPQBase::dumpRegPressure() const {
1851 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
1852 E = TRI->regclass_end(); I != E; ++I) {
1853 const TargetRegisterClass *RC = *I;
1854 unsigned Id = RC->getID();
1855 unsigned RP = RegPressure[Id];
1857 DEBUG(dbgs() << RC->getName() << ": " << RP << " / " << RegLimit[Id]
1862 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
1866 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1870 SUnit *PredSU = I->getSUnit();
1871 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1872 // to cover the number of registers defined (they are all live).
1873 if (PredSU->NumRegDefsLeft == 0) {
1876 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
1877 RegDefPos.IsValid(); RegDefPos.Advance()) {
1878 unsigned RCId, Cost;
1879 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost);
1881 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
1888 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const {
1889 const SDNode *N = SU->getNode();
1891 if (!N->isMachineOpcode() || !SU->NumSuccs)
1894 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
1895 for (unsigned i = 0; i != NumDefs; ++i) {
1896 EVT VT = N->getValueType(i);
1897 if (!N->hasAnyUseOfValue(i))
1899 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1900 if (RegPressure[RCId] >= RegLimit[RCId])
1906 // Compute the register pressure contribution by this instruction by count up
1907 // for uses that are not live and down for defs. Only count register classes
1908 // that are already under high pressure. As a side effect, compute the number of
1909 // uses of registers that are already live.
1911 // FIXME: This encompasses the logic in HighRegPressure and MayReduceRegPressure
1912 // so could probably be factored.
1913 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
1916 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
1920 SUnit *PredSU = I->getSUnit();
1921 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1922 // to cover the number of registers defined (they are all live).
1923 if (PredSU->NumRegDefsLeft == 0) {
1924 if (PredSU->getNode()->isMachineOpcode())
1928 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
1929 RegDefPos.IsValid(); RegDefPos.Advance()) {
1930 EVT VT = RegDefPos.GetValue();
1931 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1932 if (RegPressure[RCId] >= RegLimit[RCId])
1936 const SDNode *N = SU->getNode();
1938 if (!N || !N->isMachineOpcode() || !SU->NumSuccs)
1941 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
1942 for (unsigned i = 0; i != NumDefs; ++i) {
1943 EVT VT = N->getValueType(i);
1944 if (!N->hasAnyUseOfValue(i))
1946 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
1947 if (RegPressure[RCId] >= RegLimit[RCId])
1953 void RegReductionPQBase::ScheduledNode(SUnit *SU) {
1954 if (!TracksRegPressure)
1960 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1964 SUnit *PredSU = I->getSUnit();
1965 // NumRegDefsLeft is zero when enough uses of this node have been scheduled
1966 // to cover the number of registers defined (they are all live).
1967 if (PredSU->NumRegDefsLeft == 0) {
1970 // FIXME: The ScheduleDAG currently loses information about which of a
1971 // node's values is consumed by each dependence. Consequently, if the node
1972 // defines multiple register classes, we don't know which to pressurize
1973 // here. Instead the following loop consumes the register defs in an
1974 // arbitrary order. At least it handles the common case of clustered loads
1975 // to the same class. For precise liveness, each SDep needs to indicate the
1976 // result number. But that tightly couples the ScheduleDAG with the
1977 // SelectionDAG making updates tricky. A simpler hack would be to attach a
1978 // value type or register class to SDep.
1980 // The most important aspect of register tracking is balancing the increase
1981 // here with the reduction further below. Note that this SU may use multiple
1982 // defs in PredSU. The can't be determined here, but we've already
1983 // compensated by reducing NumRegDefsLeft in PredSU during
1984 // ScheduleDAGSDNodes::AddSchedEdges.
1985 --PredSU->NumRegDefsLeft;
1986 unsigned SkipRegDefs = PredSU->NumRegDefsLeft;
1987 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
1988 RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
1992 unsigned RCId, Cost;
1993 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost);
1994 RegPressure[RCId] += Cost;
1999 // We should have this assert, but there may be dead SDNodes that never
2000 // materialize as SUnits, so they don't appear to generate liveness.
2001 //assert(SU->NumRegDefsLeft == 0 && "not all regdefs have scheduled uses");
2002 int SkipRegDefs = (int)SU->NumRegDefsLeft;
2003 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG);
2004 RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
2005 if (SkipRegDefs > 0)
2007 unsigned RCId, Cost;
2008 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost);
2009 if (RegPressure[RCId] < Cost) {
2010 // Register pressure tracking is imprecise. This can happen. But we try
2011 // hard not to let it happen because it likely results in poor scheduling.
2012 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n");
2013 RegPressure[RCId] = 0;
2016 RegPressure[RCId] -= Cost;
2022 void RegReductionPQBase::UnscheduledNode(SUnit *SU) {
2023 if (!TracksRegPressure)
2026 const SDNode *N = SU->getNode();
2029 if (!N->isMachineOpcode()) {
2030 if (N->getOpcode() != ISD::CopyToReg)
2033 unsigned Opc = N->getMachineOpcode();
2034 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
2035 Opc == TargetOpcode::INSERT_SUBREG ||
2036 Opc == TargetOpcode::SUBREG_TO_REG ||
2037 Opc == TargetOpcode::REG_SEQUENCE ||
2038 Opc == TargetOpcode::IMPLICIT_DEF)
2042 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2046 SUnit *PredSU = I->getSUnit();
2047 // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
2048 // counts data deps.
2049 if (PredSU->NumSuccsLeft != PredSU->Succs.size())
2051 const SDNode *PN = PredSU->getNode();
2052 if (!PN->isMachineOpcode()) {
2053 if (PN->getOpcode() == ISD::CopyFromReg) {
2054 EVT VT = PN->getValueType(0);
2055 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2056 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2060 unsigned POpc = PN->getMachineOpcode();
2061 if (POpc == TargetOpcode::IMPLICIT_DEF)
2063 if (POpc == TargetOpcode::EXTRACT_SUBREG ||
2064 POpc == TargetOpcode::INSERT_SUBREG ||
2065 POpc == TargetOpcode::SUBREG_TO_REG) {
2066 EVT VT = PN->getValueType(0);
2067 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2068 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2071 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
2072 for (unsigned i = 0; i != NumDefs; ++i) {
2073 EVT VT = PN->getValueType(i);
2074 if (!PN->hasAnyUseOfValue(i))
2076 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2077 if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
2078 // Register pressure tracking is imprecise. This can happen.
2079 RegPressure[RCId] = 0;
2081 RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
2085 // Check for isMachineOpcode() as PrescheduleNodesWithMultipleUses()
2086 // may transfer data dependencies to CopyToReg.
2087 if (SU->NumSuccs && N->isMachineOpcode()) {
2088 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2089 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
2090 EVT VT = N->getValueType(i);
2091 if (VT == MVT::Glue || VT == MVT::Other)
2093 if (!N->hasAnyUseOfValue(i))
2095 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2096 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
2103 //===----------------------------------------------------------------------===//
2104 // Dynamic Node Priority for Register Pressure Reduction
2105 //===----------------------------------------------------------------------===//
2107 /// closestSucc - Returns the scheduled cycle of the successor which is
2108 /// closest to the current cycle.
2109 static unsigned closestSucc(const SUnit *SU) {
2110 unsigned MaxHeight = 0;
2111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2113 if (I->isCtrl()) continue; // ignore chain succs
2114 unsigned Height = I->getSUnit()->getHeight();
2115 // If there are bunch of CopyToRegs stacked up, they should be considered
2116 // to be at the same position.
2117 if (I->getSUnit()->getNode() &&
2118 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2119 Height = closestSucc(I->getSUnit())+1;
2120 if (Height > MaxHeight)
2126 /// calcMaxScratches - Returns an cost estimate of the worse case requirement
2127 /// for scratch registers, i.e. number of data dependencies.
2128 static unsigned calcMaxScratches(const SUnit *SU) {
2129 unsigned Scratches = 0;
2130 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2132 if (I->isCtrl()) continue; // ignore chain preds
2138 /// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are
2139 /// CopyFromReg from a virtual register.
2140 static bool hasOnlyLiveInOpers(const SUnit *SU) {
2141 bool RetVal = false;
2142 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2144 if (I->isCtrl()) continue;
2145 const SUnit *PredSU = I->getSUnit();
2146 if (PredSU->getNode() &&
2147 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
2149 cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2150 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2160 /// hasOnlyLiveOutUses - Return true if SU has only value successors that are
2161 /// CopyToReg to a virtual register. This SU def is probably a liveout and
2162 /// it has no other use. It should be scheduled closer to the terminator.
2163 static bool hasOnlyLiveOutUses(const SUnit *SU) {
2164 bool RetVal = false;
2165 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
2167 if (I->isCtrl()) continue;
2168 const SUnit *SuccSU = I->getSUnit();
2169 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) {
2171 cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();
2172 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2182 // Set isVRegCycle for a node with only live in opers and live out uses. Also
2183 // set isVRegCycle for its CopyFromReg operands.
2185 // This is only relevant for single-block loops, in which case the VRegCycle
2186 // node is likely an induction variable in which the operand and target virtual
2187 // registers should be coalesced (e.g. pre/post increment values). Setting the
2188 // isVRegCycle flag helps the scheduler prioritize other uses of the same
2189 // CopyFromReg so that this node becomes the virtual register "kill". This
2190 // avoids interference between the values live in and out of the block and
2191 // eliminates a copy inside the loop.
2192 static void initVRegCycle(SUnit *SU) {
2193 if (DisableSchedVRegCycle)
2196 if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU))
2199 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n");
2201 SU->isVRegCycle = true;
2203 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
2205 if (I->isCtrl()) continue;
2206 I->getSUnit()->isVRegCycle = true;
2210 // After scheduling the definition of a VRegCycle, clear the isVRegCycle flag of
2211 // CopyFromReg operands. We should no longer penalize other uses of this VReg.
2212 static void resetVRegCycle(SUnit *SU) {
2213 if (!SU->isVRegCycle)
2216 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2218 if (I->isCtrl()) continue; // ignore chain preds
2219 SUnit *PredSU = I->getSUnit();
2220 if (PredSU->isVRegCycle) {
2221 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
2222 "VRegCycle def must be CopyFromReg");
2223 I->getSUnit()->isVRegCycle = 0;
2228 // Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This
2229 // means a node that defines the VRegCycle has not been scheduled yet.
2230 static bool hasVRegCycleUse(const SUnit *SU) {
2231 // If this SU also defines the VReg, don't hoist it as a "use".
2232 if (SU->isVRegCycle)
2235 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
2237 if (I->isCtrl()) continue; // ignore chain preds
2238 if (I->getSUnit()->isVRegCycle &&
2239 I->getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2240 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n");
2247 // Check for either a dependence (latency) or resource (hazard) stall.
2249 // Note: The ScheduleHazardRecognizer interface requires a non-const SU.
2250 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) {
2251 if ((int)SPQ->getCurCycle() < Height) return true;
2252 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2253 != ScheduleHazardRecognizer::NoHazard)
2258 // Return -1 if left has higher priority, 1 if right has higher priority.
2259 // Return 0 if latency-based priority is equivalent.
2260 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
2261 RegReductionPQBase *SPQ) {
2262 // Scheduling an instruction that uses a VReg whose postincrement has not yet
2263 // been scheduled will induce a copy. Model this as an extra cycle of latency.
2264 int LPenalty = hasVRegCycleUse(left) ? 1 : 0;
2265 int RPenalty = hasVRegCycleUse(right) ? 1 : 0;
2266 int LHeight = (int)left->getHeight() + LPenalty;
2267 int RHeight = (int)right->getHeight() + RPenalty;
2269 bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) &&
2270 BUHasStall(left, LHeight, SPQ);
2271 bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) &&
2272 BUHasStall(right, RHeight, SPQ);
2274 // If scheduling one of the node will cause a pipeline stall, delay it.
2275 // If scheduling either one of the node will cause a pipeline stall, sort
2276 // them according to their height.
2280 if (LHeight != RHeight)
2281 return LHeight > RHeight ? 1 : -1;
2285 // If either node is scheduling for latency, sort them by height/depth
2287 if (!checkPref || (left->SchedulingPref == Sched::ILP ||
2288 right->SchedulingPref == Sched::ILP)) {
2289 if (DisableSchedCycles) {
2290 if (LHeight != RHeight)
2291 return LHeight > RHeight ? 1 : -1;
2294 // If neither instruction stalls (!LStall && !RStall) then
2295 // its height is already covered so only its depth matters. We also reach
2296 // this if both stall but have the same height.
2297 int LDepth = left->getDepth() - LPenalty;
2298 int RDepth = right->getDepth() - RPenalty;
2299 if (LDepth != RDepth) {
2300 DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum
2301 << ") depth " << LDepth << " vs SU (" << right->NodeNum
2302 << ") depth " << RDepth << "\n");
2303 return LDepth < RDepth ? 1 : -1;
2306 if (left->Latency != right->Latency)
2307 return left->Latency > right->Latency ? 1 : -1;
2312 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
2313 // Schedule physical register definitions close to their use. This is
2314 // motivated by microarchitectures that can fuse cmp+jump macro-ops. But as
2315 // long as shortening physreg live ranges is generally good, we can defer
2316 // creating a subtarget hook.
2317 if (!DisableSchedPhysRegJoin) {
2318 bool LHasPhysReg = left->hasPhysRegDefs;
2319 bool RHasPhysReg = right->hasPhysRegDefs;
2320 if (LHasPhysReg != RHasPhysReg) {
2322 const char *PhysRegMsg[] = {" has no physreg", " defines a physreg"};
2324 DEBUG(dbgs() << " SU (" << left->NodeNum << ") "
2325 << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum << ") "
2326 << PhysRegMsg[RHasPhysReg] << "\n");
2327 return LHasPhysReg < RHasPhysReg;
2331 // Prioritize by Sethi-Ulmann number and push CopyToReg nodes down.
2332 unsigned LPriority = SPQ->getNodePriority(left);
2333 unsigned RPriority = SPQ->getNodePriority(right);
2335 // Be really careful about hoisting call operands above previous calls.
2336 // Only allows it if it would reduce register pressure.
2337 if (left->isCall && right->isCallOp) {
2338 unsigned RNumVals = right->getNode()->getNumValues();
2339 RPriority = (RPriority > RNumVals) ? (RPriority - RNumVals) : 0;
2341 if (right->isCall && left->isCallOp) {
2342 unsigned LNumVals = left->getNode()->getNumValues();
2343 LPriority = (LPriority > LNumVals) ? (LPriority - LNumVals) : 0;
2346 if (LPriority != RPriority)
2347 return LPriority > RPriority;
2349 // One or both of the nodes are calls and their sethi-ullman numbers are the
2350 // same, then keep source order.
2351 if (left->isCall || right->isCall) {
2352 unsigned LOrder = SPQ->getNodeOrdering(left);
2353 unsigned ROrder = SPQ->getNodeOrdering(right);
2355 // Prefer an ordering where the lower the non-zero order number, the higher
2357 if ((LOrder || ROrder) && LOrder != ROrder)
2358 return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
2361 // Try schedule def + use closer when Sethi-Ullman numbers are the same.
2366 // and the following instructions are both ready.
2370 // Then schedule t2 = op first.
2377 // This creates more short live intervals.
2378 unsigned LDist = closestSucc(left);
2379 unsigned RDist = closestSucc(right);
2381 return LDist < RDist;
2383 // How many registers becomes live when the node is scheduled.
2384 unsigned LScratch = calcMaxScratches(left);
2385 unsigned RScratch = calcMaxScratches(right);
2386 if (LScratch != RScratch)
2387 return LScratch > RScratch;
2389 // Comparing latency against a call makes little sense unless the node
2390 // is register pressure-neutral.
2391 if ((left->isCall && RPriority > 0) || (right->isCall && LPriority > 0))
2392 return (left->NodeQueueId > right->NodeQueueId);
2394 // Do not compare latencies when one or both of the nodes are calls.
2395 if (!DisableSchedCycles &&
2396 !(left->isCall || right->isCall)) {
2397 int result = BUCompareLatency(left, right, false /*checkPref*/, SPQ);
2402 if (left->getHeight() != right->getHeight())
2403 return left->getHeight() > right->getHeight();
2405 if (left->getDepth() != right->getDepth())
2406 return left->getDepth() < right->getDepth();
2409 assert(left->NodeQueueId && right->NodeQueueId &&
2410 "NodeQueueId cannot be zero");
2411 return (left->NodeQueueId > right->NodeQueueId);
2415 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2416 if (int res = checkSpecialNodes(left, right))
2419 return BURRSort(left, right, SPQ);
2422 // Source order, otherwise bottom up.
2423 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2424 if (int res = checkSpecialNodes(left, right))
2427 unsigned LOrder = SPQ->getNodeOrdering(left);
2428 unsigned ROrder = SPQ->getNodeOrdering(right);
2430 // Prefer an ordering where the lower the non-zero order number, the higher
2432 if ((LOrder || ROrder) && LOrder != ROrder)
2433 return LOrder != 0 && (LOrder < ROrder || ROrder == 0);
2435 return BURRSort(left, right, SPQ);
2438 // If the time between now and when the instruction will be ready can cover
2439 // the spill code, then avoid adding it to the ready queue. This gives long
2440 // stalls highest priority and allows hoisting across calls. It should also
2441 // speed up processing the available queue.
2442 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2443 static const unsigned ReadyDelay = 3;
2445 if (SPQ->MayReduceRegPressure(SU)) return true;
2447 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false;
2449 if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay)
2450 != ScheduleHazardRecognizer::NoHazard)
2456 // Return true if right should be scheduled with higher priority than left.
2457 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2458 if (int res = checkSpecialNodes(left, right))
2461 if (left->isCall || right->isCall)
2462 // No way to compute latency of calls.
2463 return BURRSort(left, right, SPQ);
2465 bool LHigh = SPQ->HighRegPressure(left);
2466 bool RHigh = SPQ->HighRegPressure(right);
2467 // Avoid causing spills. If register pressure is high, schedule for
2468 // register pressure reduction.
2469 if (LHigh && !RHigh) {
2470 DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("
2471 << right->NodeNum << ")\n");
2474 else if (!LHigh && RHigh) {
2475 DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("
2476 << left->NodeNum << ")\n");
2479 if (!LHigh && !RHigh) {
2480 int result = BUCompareLatency(left, right, true /*checkPref*/, SPQ);
2484 return BURRSort(left, right, SPQ);
2487 // Schedule as many instructions in each cycle as possible. So don't make an
2488 // instruction available unless it is ready in the current cycle.
2489 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
2490 if (SU->getHeight() > CurCycle) return false;
2492 if (SPQ->getHazardRec()->getHazardType(SU, 0)
2493 != ScheduleHazardRecognizer::NoHazard)
2499 static bool canEnableCoalescing(SUnit *SU) {
2500 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
2501 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
2502 // CopyToReg should be close to its uses to facilitate coalescing and
2506 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
2507 Opc == TargetOpcode::SUBREG_TO_REG ||
2508 Opc == TargetOpcode::INSERT_SUBREG)
2509 // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
2510 // close to their uses to facilitate coalescing.
2513 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
2514 // If SU does not have a register def, schedule it close to its uses
2515 // because it does not lengthen any live ranges.
2521 // list-ilp is currently an experimental scheduler that allows various
2522 // heuristics to be enabled prior to the normal register reduction logic.
2523 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
2524 if (int res = checkSpecialNodes(left, right))
2527 if (left->isCall || right->isCall)
2528 // No way to compute latency of calls.
2529 return BURRSort(left, right, SPQ);
2531 unsigned LLiveUses = 0, RLiveUses = 0;
2532 int LPDiff = 0, RPDiff = 0;
2533 if (!DisableSchedRegPressure || !DisableSchedLiveUses) {
2534 LPDiff = SPQ->RegPressureDiff(left, LLiveUses);
2535 RPDiff = SPQ->RegPressureDiff(right, RLiveUses);
2537 if (!DisableSchedRegPressure && LPDiff != RPDiff) {
2538 DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff
2539 << " != SU(" << right->NodeNum << "): " << RPDiff << "\n");
2540 return LPDiff > RPDiff;
2543 if (!DisableSchedRegPressure && (LPDiff > 0 || RPDiff > 0)) {
2544 bool LReduce = canEnableCoalescing(left);
2545 bool RReduce = canEnableCoalescing(right);
2546 if (LReduce && !RReduce) return false;
2547 if (RReduce && !LReduce) return true;
2550 if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) {
2551 DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
2552 << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n");
2553 return LLiveUses < RLiveUses;
2556 if (!DisableSchedStalls) {
2557 bool LStall = BUHasStall(left, left->getHeight(), SPQ);
2558 bool RStall = BUHasStall(right, right->getHeight(), SPQ);
2559 if (LStall != RStall)
2560 return left->getHeight() > right->getHeight();
2563 if (!DisableSchedCriticalPath) {
2564 int spread = (int)left->getDepth() - (int)right->getDepth();
2565 if (std::abs(spread) > MaxReorderWindow) {
2566 DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
2567 << left->getDepth() << " != SU(" << right->NodeNum << "): "
2568 << right->getDepth() << "\n");
2569 return left->getDepth() < right->getDepth();
2573 if (!DisableSchedHeight && left->getHeight() != right->getHeight()) {
2574 int spread = (int)left->getHeight() - (int)right->getHeight();
2575 if (std::abs(spread) > MaxReorderWindow)
2576 return left->getHeight() > right->getHeight();
2579 return BURRSort(left, right, SPQ);
2582 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
2584 // Add pseudo dependency edges for two-address nodes.
2585 if (!Disable2AddrHack)
2586 AddPseudoTwoAddrDeps();
2587 // Reroute edges to nodes with multiple uses.
2588 if (!TracksRegPressure)
2589 PrescheduleNodesWithMultipleUses();
2590 // Calculate node priorities.
2591 CalculateSethiUllmanNumbers();
2593 // For single block loops, mark nodes that look like canonical IV increments.
2594 if (scheduleDAG->BB->isSuccessor(scheduleDAG->BB)) {
2595 for (unsigned i = 0, e = sunits.size(); i != e; ++i) {
2596 initVRegCycle(&sunits[i]);
2601 //===----------------------------------------------------------------------===//
2602 // Preschedule for Register Pressure
2603 //===----------------------------------------------------------------------===//
2605 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) {
2606 if (SU->isTwoAddress) {
2607 unsigned Opc = SU->getNode()->getMachineOpcode();
2608 const MCInstrDesc &MCID = TII->get(Opc);
2609 unsigned NumRes = MCID.getNumDefs();
2610 unsigned NumOps = MCID.getNumOperands() - NumRes;
2611 for (unsigned i = 0; i != NumOps; ++i) {
2612 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) {
2613 SDNode *DU = SU->getNode()->getOperand(i).getNode();
2614 if (DU->getNodeId() != -1 &&
2615 Op->OrigNode == &(*SUnits)[DU->getNodeId()])
2623 /// canClobberReachingPhysRegUse - True if SU would clobber one of it's
2624 /// successor's explicit physregs whose definition can reach DepSU.
2625 /// i.e. DepSU should not be scheduled above SU.
2626 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU,
2627 ScheduleDAGRRList *scheduleDAG,
2628 const TargetInstrInfo *TII,
2629 const TargetRegisterInfo *TRI) {
2630 const unsigned *ImpDefs
2631 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2635 for (SUnit::const_succ_iterator SI = SU->Succs.begin(), SE = SU->Succs.end();
2637 SUnit *SuccSU = SI->getSUnit();
2638 for (SUnit::const_pred_iterator PI = SuccSU->Preds.begin(),
2639 PE = SuccSU->Preds.end(); PI != PE; ++PI) {
2640 if (!PI->isAssignedRegDep())
2643 for (const unsigned *ImpDef = ImpDefs; *ImpDef; ++ImpDef) {
2644 // Return true if SU clobbers this physical register use and the
2645 // definition of the register reaches from DepSU. IsReachable queries a
2646 // topological forward sort of the DAG (following the successors).
2647 if (TRI->regsOverlap(*ImpDef, PI->getReg()) &&
2648 scheduleDAG->IsReachable(DepSU, PI->getSUnit()))
2656 /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
2657 /// physical register defs.
2658 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
2659 const TargetInstrInfo *TII,
2660 const TargetRegisterInfo *TRI) {
2661 SDNode *N = SuccSU->getNode();
2662 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2663 const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2664 assert(ImpDefs && "Caller should check hasPhysRegDefs");
2665 for (const SDNode *SUNode = SU->getNode(); SUNode;
2666 SUNode = SUNode->getGluedNode()) {
2667 if (!SUNode->isMachineOpcode())
2669 const unsigned *SUImpDefs =
2670 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
2673 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
2674 EVT VT = N->getValueType(i);
2675 if (VT == MVT::Glue || VT == MVT::Other)
2677 if (!N->hasAnyUseOfValue(i))
2679 unsigned Reg = ImpDefs[i - NumDefs];
2680 for (;*SUImpDefs; ++SUImpDefs) {
2681 unsigned SUReg = *SUImpDefs;
2682 if (TRI->regsOverlap(Reg, SUReg))
2690 /// PrescheduleNodesWithMultipleUses - Nodes with multiple uses
2691 /// are not handled well by the general register pressure reduction
2692 /// heuristics. When presented with code like this:
2701 /// the heuristics tend to push the store up, but since the
2702 /// operand of the store has another use (U), this would increase
2703 /// the length of that other use (the U->N edge).
2705 /// This function transforms code like the above to route U's
2706 /// dependence through the store when possible, like this:
2717 /// This results in the store being scheduled immediately
2718 /// after N, which shortens the U->N live range, reducing
2719 /// register pressure.
2721 void RegReductionPQBase::PrescheduleNodesWithMultipleUses() {
2722 // Visit all the nodes in topological order, working top-down.
2723 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
2724 SUnit *SU = &(*SUnits)[i];
2725 // For now, only look at nodes with no data successors, such as stores.
2726 // These are especially important, due to the heuristics in
2727 // getNodePriority for nodes with no data successors.
2728 if (SU->NumSuccs != 0)
2730 // For now, only look at nodes with exactly one data predecessor.
2731 if (SU->NumPreds != 1)
2733 // Avoid prescheduling copies to virtual registers, which don't behave
2734 // like other nodes from the perspective of scheduling heuristics.
2735 if (SDNode *N = SU->getNode())
2736 if (N->getOpcode() == ISD::CopyToReg &&
2737 TargetRegisterInfo::isVirtualRegister
2738 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2741 // Locate the single data predecessor.
2743 for (SUnit::const_pred_iterator II = SU->Preds.begin(),
2744 EE = SU->Preds.end(); II != EE; ++II)
2745 if (!II->isCtrl()) {
2746 PredSU = II->getSUnit();
2751 // Don't rewrite edges that carry physregs, because that requires additional
2752 // support infrastructure.
2753 if (PredSU->hasPhysRegDefs)
2755 // Short-circuit the case where SU is PredSU's only data successor.
2756 if (PredSU->NumSuccs == 1)
2758 // Avoid prescheduling to copies from virtual registers, which don't behave
2759 // like other nodes from the perspective of scheduling heuristics.
2760 if (SDNode *N = SU->getNode())
2761 if (N->getOpcode() == ISD::CopyFromReg &&
2762 TargetRegisterInfo::isVirtualRegister
2763 (cast<RegisterSDNode>(N->getOperand(1))->getReg()))
2766 // Perform checks on the successors of PredSU.
2767 for (SUnit::const_succ_iterator II = PredSU->Succs.begin(),
2768 EE = PredSU->Succs.end(); II != EE; ++II) {
2769 SUnit *PredSuccSU = II->getSUnit();
2770 if (PredSuccSU == SU) continue;
2771 // If PredSU has another successor with no data successors, for
2772 // now don't attempt to choose either over the other.
2773 if (PredSuccSU->NumSuccs == 0)
2774 goto outer_loop_continue;
2775 // Don't break physical register dependencies.
2776 if (SU->hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs)
2777 if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI))
2778 goto outer_loop_continue;
2779 // Don't introduce graph cycles.
2780 if (scheduleDAG->IsReachable(SU, PredSuccSU))
2781 goto outer_loop_continue;
2784 // Ok, the transformation is safe and the heuristics suggest it is
2785 // profitable. Update the graph.
2786 DEBUG(dbgs() << " Prescheduling SU #" << SU->NodeNum
2787 << " next to PredSU #" << PredSU->NodeNum
2788 << " to guide scheduling in the presence of multiple uses\n");
2789 for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
2790 SDep Edge = PredSU->Succs[i];
2791 assert(!Edge.isAssignedRegDep());
2792 SUnit *SuccSU = Edge.getSUnit();
2794 Edge.setSUnit(PredSU);
2795 scheduleDAG->RemovePred(SuccSU, Edge);
2796 scheduleDAG->AddPred(SU, Edge);
2798 scheduleDAG->AddPred(SuccSU, Edge);
2802 outer_loop_continue:;
2806 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
2807 /// it as a def&use operand. Add a pseudo control edge from it to the other
2808 /// node (if it won't create a cycle) so the two-address one will be scheduled
2809 /// first (lower in the schedule). If both nodes are two-address, favor the
2810 /// one that has a CopyToReg use (more likely to be a loop induction update).
2811 /// If both are two-address, but one is commutable while the other is not
2812 /// commutable, favor the one that's not commutable.
2813 void RegReductionPQBase::AddPseudoTwoAddrDeps() {
2814 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
2815 SUnit *SU = &(*SUnits)[i];
2816 if (!SU->isTwoAddress)
2819 SDNode *Node = SU->getNode();
2820 if (!Node || !Node->isMachineOpcode() || SU->getNode()->getGluedNode())
2823 bool isLiveOut = hasOnlyLiveOutUses(SU);
2824 unsigned Opc = Node->getMachineOpcode();
2825 const MCInstrDesc &MCID = TII->get(Opc);
2826 unsigned NumRes = MCID.getNumDefs();
2827 unsigned NumOps = MCID.getNumOperands() - NumRes;
2828 for (unsigned j = 0; j != NumOps; ++j) {
2829 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1)
2831 SDNode *DU = SU->getNode()->getOperand(j).getNode();
2832 if (DU->getNodeId() == -1)
2834 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
2835 if (!DUSU) continue;
2836 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
2837 E = DUSU->Succs.end(); I != E; ++I) {
2838 if (I->isCtrl()) continue;
2839 SUnit *SuccSU = I->getSUnit();
2842 // Be conservative. Ignore if nodes aren't at roughly the same
2843 // depth and height.
2844 if (SuccSU->getHeight() < SU->getHeight() &&
2845 (SU->getHeight() - SuccSU->getHeight()) > 1)
2847 // Skip past COPY_TO_REGCLASS nodes, so that the pseudo edge
2848 // constrains whatever is using the copy, instead of the copy
2849 // itself. In the case that the copy is coalesced, this
2850 // preserves the intent of the pseudo two-address heurietics.
2851 while (SuccSU->Succs.size() == 1 &&
2852 SuccSU->getNode()->isMachineOpcode() &&
2853 SuccSU->getNode()->getMachineOpcode() ==
2854 TargetOpcode::COPY_TO_REGCLASS)
2855 SuccSU = SuccSU->Succs.front().getSUnit();
2856 // Don't constrain non-instruction nodes.
2857 if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
2859 // Don't constrain nodes with physical register defs if the
2860 // predecessor can clobber them.
2861 if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) {
2862 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
2865 // Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG;
2866 // these may be coalesced away. We want them close to their uses.
2867 unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
2868 if (SuccOpc == TargetOpcode::EXTRACT_SUBREG ||
2869 SuccOpc == TargetOpcode::INSERT_SUBREG ||
2870 SuccOpc == TargetOpcode::SUBREG_TO_REG)
2872 if (!canClobberReachingPhysRegUse(SuccSU, SU, scheduleDAG, TII, TRI) &&
2873 (!canClobber(SuccSU, DUSU) ||
2874 (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) ||
2875 (!SU->isCommutable && SuccSU->isCommutable)) &&
2876 !scheduleDAG->IsReachable(SuccSU, SU)) {
2877 DEBUG(dbgs() << " Adding a pseudo-two-addr edge from SU #"
2878 << SU->NodeNum << " to SU #" << SuccSU->NodeNum << "\n");
2879 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/0,
2880 /*Reg=*/0, /*isNormalMemory=*/false,
2881 /*isMustAlias=*/false,
2882 /*isArtificial=*/true));
2889 //===----------------------------------------------------------------------===//
2890 // Public Constructor Functions
2891 //===----------------------------------------------------------------------===//
2893 llvm::ScheduleDAGSDNodes *
2894 llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
2895 CodeGenOpt::Level OptLevel) {
2896 const TargetMachine &TM = IS->TM;
2897 const TargetInstrInfo *TII = TM.getInstrInfo();
2898 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2900 BURegReductionPriorityQueue *PQ =
2901 new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
2902 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2903 PQ->setScheduleDAG(SD);
2907 llvm::ScheduleDAGSDNodes *
2908 llvm::createSourceListDAGScheduler(SelectionDAGISel *IS,
2909 CodeGenOpt::Level OptLevel) {
2910 const TargetMachine &TM = IS->TM;
2911 const TargetInstrInfo *TII = TM.getInstrInfo();
2912 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2914 SrcRegReductionPriorityQueue *PQ =
2915 new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
2916 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, PQ, OptLevel);
2917 PQ->setScheduleDAG(SD);
2921 llvm::ScheduleDAGSDNodes *
2922 llvm::createHybridListDAGScheduler(SelectionDAGISel *IS,
2923 CodeGenOpt::Level OptLevel) {
2924 const TargetMachine &TM = IS->TM;
2925 const TargetInstrInfo *TII = TM.getInstrInfo();
2926 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2927 const TargetLowering *TLI = &IS->getTargetLowering();
2929 HybridBURRPriorityQueue *PQ =
2930 new HybridBURRPriorityQueue(*IS->MF, true, TII, TRI, TLI);
2932 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
2933 PQ->setScheduleDAG(SD);
2937 llvm::ScheduleDAGSDNodes *
2938 llvm::createILPListDAGScheduler(SelectionDAGISel *IS,
2939 CodeGenOpt::Level OptLevel) {
2940 const TargetMachine &TM = IS->TM;
2941 const TargetInstrInfo *TII = TM.getInstrInfo();
2942 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
2943 const TargetLowering *TLI = &IS->getTargetLowering();
2945 ILPBURRPriorityQueue *PQ =
2946 new ILPBURRPriorityQueue(*IS->MF, true, TII, TRI, TLI);
2947 ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, PQ, OptLevel);
2948 PQ->setScheduleDAG(SD);