| 2012-03-09 |
Andrew Trick | misched interface: rename Begin/End to RegionBegin... |
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| 2012-03-07 |
Andrew Trick | misched prep: Expose the ScheduleDAGInstrs interface... |
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| 2012-03-07 |
Andrew Trick | misched prep: Comment the ScheduleDAGInstrs interface. |
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| 2012-03-07 |
Andrew Trick | misched prep: Cleanup ScheduleDAGInstrs interface. |
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| 2012-03-07 |
Andrew Trick | misched prep: rename InsertPos to End. |
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| 2012-03-07 |
Andrew Trick | misched preparation: rename core scheduler methods... |
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| 2012-03-07 |
Andrew Trick | misched preparation: clarify ScheduleDAG and ScheduleDA... |
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| 2012-03-07 |
Andrew Trick | misched preparation: modularize schedule emission. |
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| 2012-03-07 |
Andrew Trick | Cleanup in preparation for misched: Move DAG visualizat... |
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| 2012-03-04 |
Craig Topper | Use uint16_t to store register overlaps to reduce stati... |
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| 2012-02-24 |
Andrew Trick | PostRA sched: speed up physreg tracking by not abusing... |
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| 2012-02-23 |
Andrew Trick | misched: cleanup reaching def computation |
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| 2012-02-23 |
Andrew Trick | PostRASched: Convert physreg def/use tracking to Jakob... |
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| 2012-02-22 |
Jakob Stoklund Olesen | Don't compute latencies for regmask operands. |
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| 2012-02-22 |
Andrew Trick | misched: Use SparseSet for VRegDegs for constant time... |
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| 2012-02-22 |
Andrew Trick | Comment from code review |
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| 2012-02-22 |
Andrew Trick | misched: DAG builder should not track dependencies... |
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| 2012-02-22 |
Andrew Trick | Initialize SUnits before DAG building. |
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| 2012-02-21 |
Andrew Trick | Clear virtual registers after they are no longer refere... |
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| 2012-01-14 |
Andrew Trick | misched: Initial code for building an MI level scheduli... |
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| 2012-01-14 |
Andrew Trick | Move physreg dependency generation into aptly named... |
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| 2012-01-14 |
Andrew Trick | misched: Added ScheduleDAGInstrs::IsPostRA |
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| 2012-01-07 |
Evan Cheng | Added a late machine instruction copy propagation pass... |
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| 2012-01-05 |
Chandler Carruth | Remove an unused variable. |
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| 2012-01-05 |
Andrew Trick | Minor postra scheduler cleanup. It could result in... |
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| 2011-12-14 |
Evan Cheng | Model ARM predicated write as read-mod-write. e.g. |
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| 2011-12-14 |
Evan Cheng | Allow target to specify register output dependency... |
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| 2011-12-14 |
Evan Cheng | - Add MachineInstrBundle.h and MachineInstrBundle.cpp... |
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| 2011-12-07 |
Evan Cheng | Add bundle aware API for querying instruction propertie... |
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| 2011-12-06 |
Evan Cheng | First chunk of MachineInstr bundle support. |
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| 2011-12-02 |
Hal Finkel | make sure ScheduleDAGInstrs::EmitSchedule does not... |
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| 2011-10-07 |
Andrew Trick | PostRA scheduler fix. Clear stale loop dependencies. |
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| 2011-10-07 |
Andrew Trick | whitespace |
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| 2011-07-01 |
Evan Cheng | Rename TargetSubtarget to TargetSubtargetInfo for consi... |
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| 2011-06-29 |
Evan Cheng | Sink SubtargetFeature and TargetInstrItineraries (renam... |
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| 2011-06-28 |
Evan Cheng | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrD... |
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| 2011-06-02 |
Devang Patel | Remove dead code. |
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| 2011-06-02 |
Devang Patel | Update DBG_VALUEs while breaking anti dependencies. |
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| 2011-06-02 |
Devang Patel | During post RA scheduling, do not try to chase reg... |
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| 2011-05-06 |
Andrew Trick | Added an assertion, and updated a comment. |
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| 2011-05-05 |
Andrew Trick | ARM post RA scheduler compile time fix. |
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| 2011-05-05 |
Andrew Trick | whitespace |
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| 2011-04-15 |
Chris Lattner | Fix a ton of comment typos found by codespell. Patch by |
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| 2011-01-07 |
Evan Cheng | Do not model all INLINEASM instructions as having unmod... |
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| 2010-12-15 |
Dan Gohman | Move Value::getUnderlyingObject to be a standalone |
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| 2010-11-03 |
Evan Cheng | Two sets of changes. Sorry they are intermingled. |
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| 2010-10-27 |
Evan Cheng | Putting r117193 back except for the compile time cost... |
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| 2010-10-25 |
Evan Cheng | Neuter r117193 as it causes significant post-ra schedul... |
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| 2010-10-23 |
Evan Cheng | Properly model the latency of register defs which are... |
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| 2010-10-08 |
Evan Cheng | Avoid compiler warning: comparison between signed and... |
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| 2010-10-08 |
Evan Cheng | Fix operand latency computation in cases where the... |
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| 2010-10-06 |
Nick Lewycky | Remove unused variables. |
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| 2010-10-06 |
Evan Cheng | - Add TargetInstrInfo::getOperandLatency() to compute... |
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| 2010-09-29 |
Evan Cheng | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC... |
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| 2010-09-10 |
Evan Cheng | Teach if-converter to be more careful with predicating... |
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| 2010-07-24 |
Bob Wilson | Change ScheduleDAGInstrs::Defs and ::Uses to be variabl... |
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| 2010-07-15 |
Bill Wendling | Use std::vector instead of TargetRegisterInfo::FirstVir... |
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| 2010-05-19 |
Jim Grosbach | Fix the post-RA instruction scheduler to handle instruc... |
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| 2010-05-01 |
Dan Gohman | Get rid of the EdgeMapping map. Instead, just check... |
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| 2010-04-17 |
Dan Gohman | Fix -Wcast-qual warnings. |
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| 2010-03-22 |
Evan Cheng | Reduce indentation. |
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| 2010-03-22 |
Evan Cheng | 80 col violation. |
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| 2010-03-10 |
Dale Johannesen | Progress towards shepherding debug info through Selecti... |
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| 2010-02-16 |
Duncan Sands | There are two ways of checking for a given type, for... |
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| 2009-11-09 |
David Goodwin | Fix dependencies added to model memory aliasing for... |
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| 2009-11-05 |
David Goodwin | Correctly add chain dependencies around calls and unkno... |
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| 2009-11-03 |
David Goodwin | <rdar://problem/7352605>. When building schedule graph... |
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| 2009-11-02 |
David Goodwin | Chain dependencies used to enforce memory order should... |
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| 2009-10-26 |
Dan Gohman | When checking whether a def of an aliased register... |
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| 2009-10-18 |
Evan Cheng | Spill slots cannot alias. |
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| 2009-10-18 |
Evan Cheng | -Revert parts of 84326 and 84411. Distinquishing betwee... |
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| 2009-10-09 |
Dan Gohman | Factor out LiveIntervalAnalysis' code to determine... |
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| 2009-10-07 |
Dan Gohman | Replace TargetInstrInfo::isInvariantLoad and its target... |
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| 2009-09-25 |
Dan Gohman | Improve MachineMemOperand handling. |
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| 2009-09-18 |
Evan Cheng | Enhance EmitInstrWithCustomInserter() so target can... |
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| 2009-08-19 |
David Goodwin | Use the schedule itinerary operand use/def cycle inform... |
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| 2009-08-13 |
David Goodwin | Add callback to allow target to adjust latency of sched... |
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| 2009-08-10 |
David Goodwin | Post RA scheduler changes. Introduce a hazard recognize... |
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| 2009-08-07 |
Dan Gohman | Fix a typo in a comment. |
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| 2009-07-17 |
Dan Gohman | Eliminate yet another copy of getOpcode. |
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| 2009-07-13 |
Dan Gohman | Move isLCSSAForm, isLoopInvariant, getCanonicalInductio... |
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| 2009-02-11 |
Dan Gohman | When scheduling a block in parts, keep track of the... |
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| 2009-02-10 |
Dan Gohman | Factor out more code for computing register live-range... |
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| 2009-02-06 |
Dan Gohman | Move ScheduleDAGInstrs.h to be a private header. Front... |
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| 2009-01-30 |
Dan Gohman | Fix a post-RA scheduling dependency bug. |
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| 2009-01-16 |
Dan Gohman | Instead of adding dependence edges between terminator... |
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| 2009-01-15 |
Dan Gohman | Move a few containers out of ScheduleDAGInstrs::BuildSc... |
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| 2008-12-23 |
Dan Gohman | Clean up the atomic opcodes in SelectionDAG. |
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| 2008-12-23 |
Dan Gohman | Rename BuildSchedUnits to BuildSchedGraph, and refactor the |
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| 2008-12-23 |
Dan Gohman | Use isTerminator() instead of isBranch()||isReturn... |
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| 2008-12-16 |
Dan Gohman | Add initial support for back-scheduling address computa... |
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| 2008-12-16 |
Dan Gohman | Fix some register-alias-related bugs in the post-RA... |
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| 2008-12-16 |
Dan Gohman | Add a simple target-independent heuristic to allow... |
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| 2008-12-09 |
Dan Gohman | Rewrite the SDep class, and simplify some of the relate... |
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| 2008-12-08 |
Dan Gohman | Fix the top-level comments, and fix some 80-column... |
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| 2008-12-04 |
Dan Gohman | Add minimal support for disambiguating memory reference... |
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| 2008-11-24 |
Dan Gohman | Pass the isAntiDep argument. |
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| 2008-11-21 |
Dan Gohman | Correctly set the isCtrl flag for chain dependencies. |
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| 2008-11-21 |
Dan Gohman | Update comments. |
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| 2008-11-21 |
Dan Gohman | Set the isAntiDep flag in the MachineInstr scheduler. |
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