R600: Promote i64 loads to v2i32
[oota-llvm.git] / lib / Target / R600 / AMDGPUISelLowering.cpp
2014-07-02 Tom StellardR600: Promote i64 loads to v2i32
2014-07-02 Matt ArsenaultR600: Fix crashes when an illegal type load or store...
2014-06-30 Matt ArsenaultR600: Move mul combine to separate function
2014-06-27 Matt ArsenaultR600: Move load/store ReplaceNodeResults to common...
2014-06-26 Aaron BallmanSilencing a warning about isZExtFree hiding an inherite...
2014-06-26 Matt ArsenaultR600: Fix vector FMA
2014-06-24 Tom StellardR600: Promote i64 stores to v2i32
2014-06-24 Matt ArsenaultR600: Fix inconsistency in rsq instructions.
2014-06-24 Matt ArsenaultR600: Remove DIV_INF
2014-06-23 Matt ArsenaultR600/SI: Fix div_scale intrinsic.
2014-06-23 Matt ArsenaultR600: Remove AMDILISelLowering
2014-06-23 Matt ArsenaultR600: Select is not expensive.
2014-06-23 Matt ArsenaultR600: Move add/sub with overflow out of AMDILISelLowering
2014-06-23 Matt ArsenaultR600: Move more out of AMDILISelLowering
2014-06-23 Matt ArsenaultR600/SI: Handle i64 sub.
2014-06-23 Matt ArsenaultR600: Rename AMDIL file
2014-06-22 Jan VeselyR600: Use LowerSDIVREM for i64 node replace
2014-06-22 Jan VeselyR600: Implement custom SDIVREM.
2014-06-20 Tom StellardR600/SI: Add a pattern for f32 ftrunc
2014-06-20 Tom StellardR600: Expand vector flog2
2014-06-20 Tom StellardR600: Expand vector fexp2
2014-06-19 Matt ArsenaultR600/SI: Add intrinsics for various math instructions.
2014-06-18 Matt ArsenaultUse stdint macros for specifying size of constants
2014-06-18 Matt ArsenaultR600: Handle fnearbyint
2014-06-18 Matt ArsenaultUse LL suffix for literal that should be 64-bits.
2014-06-18 Jan VeselyR600: Expand vector fceil
2014-06-18 Matt ArsenaultWork around ridiculous warning.
2014-06-18 Matt ArsenaultR600/SI: Add intrinsics for brev instructions
2014-06-18 Matt ArsenaultR600: Implement f64 ftrunc, ffloor and fceil.
2014-06-18 Matt ArsenaultR600: Custom lower f64 frint for pre-CI
2014-06-17 Matt ArsenaultR600/SI: Match ctlz_zero_undef
2014-06-17 Tom StellardR600: Use LDS and vectors for private memory
2014-06-17 Tom StellardSelectionDAG: Expand i64 = FP_TO_SINT i32
2014-06-15 Matt ArsenaultFix copy paste error
2014-06-15 Matt ArsenaultR600: Remove a few more things from AMDILISelLowering
2014-06-15 Matt ArsenaultR600: Fix assert on vector sdiv
2014-06-15 Matt ArsenaultR600: Move / cleanup more leftover AMDIL stuff.
2014-06-15 Matt ArsenaultR600: Move division custom lowering out of AMDILISelLow...
2014-06-15 Matt ArsenaultR600: Report that integer division is expensive.
2014-06-14 Matt ArsenaultR600: Fix asserts related to constant initializers
2014-06-14 Matt ArsenaultR600: Use address space enum instead of value
2014-06-13 Matt ArsenaultR600: Cleanup some old AMDIL stuff.
2014-06-13 Matt ArsenaultR600/SI: Fix selection error on i64 rotl / rotr.
2014-06-12 Matt ArsenaultR600: Mostly remove remaining AMDIL intrinsics.
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 Rafael EspindolaTry to fix the msvc build.
2014-06-11 Matt ArsenaultUse cast instead of assert + dyn_cast
2014-06-11 Matt ArsenaultR600: Add helper functions.
2014-06-10 Matt ArsenaultR600: Use BCNT_INT for evergreen
2014-06-10 Matt ArsenaultR600/SI: Use bcnt instruction for ctpop
2014-06-10 Matt ArsenaultR600: Handle fcopysign
2014-06-09 Matt ArsenaultR600: Fix selection failure for vector bswap
2014-06-01 Matt ArsenaultR600: Set all float vector expands in the same place
2014-05-22 Matt ArsenaultR600: Try to convert BFE back to standard bit ops when...
2014-05-22 Matt ArsenaultR600: Add dag combine for BFE
2014-05-22 Matt ArsenaultR600: Implement ComputeNumSignBitsForTargetNode for BFE
2014-05-22 Matt ArsenaultR600: Implement computeMaskedBitsForTargetNode for BFE
2014-05-22 Matt ArsenaultR600: Add intrinsics for mad24
2014-05-21 Matt ArsenaultR600: Add comment describing problems with LowerConstan...
2014-05-21 Matt ArsenaultR600: Partially fix constant initializers for structs...
2014-05-21 Matt ArsenaultUse cast<> instead of unchecked dyn_cast
2014-05-15 Matt ArsenaultUse range for
2014-05-14 Jay FoadRename ComputeMaskedBits to computeKnownBits. "Masked...
2014-05-12 Matt ArsenaultR600: Add mul24 intrinsics
2014-05-11 Matt ArsenaultFix return before else
2014-05-09 Tom StellardR600: Expand i64 SELECT_CC
2014-05-09 Tom StellardR600: Move MIN/MAX matching from LowerOperation() to...
2014-05-08 Matt ArsenaultR600: Promote f64 vector load/stores to i64 for consistency
2014-05-05 Tom StellardR600: Expand i64 ISD:SUB
2014-05-02 Tom StellardR600: Expand vector sin and cos.
2014-05-02 Tom StellardR600: Expand TruncStore i64 -> {i16,i8}
2014-04-29 Tom StellardR600: optimize the UDIVREM 64 algorithm
2014-04-29 Tom StellardR600: Implement iterative algorithm for udivrem
2014-04-29 Tom StellardR600: Change UDIV/UREM to UDIVREM when legalizing types
2014-04-29 Tom StellardR600: remove unused variable
2014-04-28 Craig TopperConvert more SelectionDAG functions to use ArrayRef.
2014-04-27 Craig TopperConvert SelectionDAG::getMergeValues to use ArrayRef.
2014-04-26 Craig TopperConvert SelectionDAG::getNode methods to use ArrayRef...
2014-04-25 Matt ArsenaultR600: Fix function name printing in LowerCall
2014-04-25 Craig Topper[C++] Use 'nullptr'. Target edition.
2014-04-22 Matt ArsenaultR600: Emit error instead of unreachable on function...
2014-04-22 Matt ArsenaultR600: Change how vector truncating stores are packed.
2014-04-22 Matt ArsenaultR600: Make sign_extend_inreg legal.
2014-04-17 Tom StellardR600: Add comment clariying use of sext for result...
2014-04-16 Matt ArsenaultR600: Expand sign extension of vectors.
2014-04-15 Matt ArsenaultR600/SI: Fix loads of i1
2014-04-15 Nick LewyckyBreak PseudoSourceValue out of the Value hierarchy...
2014-04-11 Matt ArsenaultMove ExtractVectorElements to SelectionDAG.
2014-04-07 Tom StellardR600: Match 24-bit arithmetic patterns in a Target...
2014-04-07 Matt ArsenaultUse .data() instead of &x[0]
2014-03-31 Matt ArsenaultR600: Compute masked bits for min and max
2014-03-31 Matt ArsenaultR600: Add BFE, BFI, and BFM intrinsics to help with...
2014-03-31 Matt ArsenaultR600: Add target nodes for BFM and BFI
2014-03-27 Matt ArsenaultR600: Implement isZExtFree.
2014-03-27 Matt ArsenaultR600/SI: Fix unreachable with a sext_in_reg to an illeg...
2014-03-26 Matt ArsenaultR600: Add a testcase for sext_in_reg I missed.
2014-03-25 Matt ArsenaultR600: Move computeMaskedBitsForTargetNode out of AMDILI...
2014-03-24 Matt ArsenaultR600: Implement isNarrowingProfitable.
2014-03-17 Matt ArsenaultR600: Match sign_extend_inreg to BFE instructions
2014-03-15 Matt ArsenaultR600: Remove unnecessary attempt to zext a pointer.
next