1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDILIntrinsicInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 // Find a larger type to do a load / store of a vector with.
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
91 return EVT::getIntegerVT(Ctx, StoreSize);
93 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
97 // Type for a vector that will be loaded to.
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
101 return EVT::getIntegerVT(Ctx, 32);
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
107 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
109 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
111 // Initialize target lowering borrowed from AMDIL
114 // We need to custom lower some of the intrinsics
115 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
117 // Library functions. These default to Expand, but we have instructions
119 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
120 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
121 setOperationAction(ISD::FPOW, MVT::f32, Legal);
122 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
123 setOperationAction(ISD::FABS, MVT::f32, Legal);
124 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
125 setOperationAction(ISD::FRINT, MVT::f32, Legal);
126 setOperationAction(ISD::FROUND, MVT::f32, Legal);
127 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
129 // The hardware supports ROTR, but not ROTL
130 setOperationAction(ISD::ROTL, MVT::i32, Expand);
132 // Lower floating point store/load to integer store/load to reduce the number
133 // of patterns in tablegen.
134 setOperationAction(ISD::STORE, MVT::f32, Promote);
135 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
137 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
138 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
140 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
141 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
143 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
144 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
146 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
147 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
149 setOperationAction(ISD::STORE, MVT::f64, Promote);
150 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
152 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
153 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
155 // Custom lowering of vector stores is required for local address space
157 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
158 // XXX: Native v2i32 local address space stores are possible, but not
159 // currently implemented.
160 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
162 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
163 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
164 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
166 // XXX: This can be change to Custom, once ExpandVectorStores can
167 // handle 64-bit stores.
168 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
170 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
171 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
172 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
173 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
174 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
177 setOperationAction(ISD::LOAD, MVT::f32, Promote);
178 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
180 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
181 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
183 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
184 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
186 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
187 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
189 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
190 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
192 setOperationAction(ISD::LOAD, MVT::f64, Promote);
193 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
195 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
196 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
198 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
199 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
200 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
201 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
202 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
203 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
204 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
205 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
206 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
207 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
209 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
210 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
212 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
213 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
214 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
215 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
216 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
217 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
218 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
219 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
220 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
222 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
224 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
226 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
228 setOperationAction(ISD::MUL, MVT::i64, Expand);
229 setOperationAction(ISD::SUB, MVT::i64, Expand);
231 setOperationAction(ISD::UDIV, MVT::i32, Expand);
232 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
233 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
234 setOperationAction(ISD::UREM, MVT::i32, Expand);
236 if (!Subtarget->hasBFI()) {
237 // fcopysign can be done in a single instruction with BFI.
238 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
239 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
242 if (!Subtarget->hasBCNT(32))
243 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
245 if (!Subtarget->hasBCNT(64))
246 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
248 for (MVT VT : { MVT::i32, MVT::i64 }) {
249 setOperationAction(ISD::CTTZ, VT, Expand);
250 setOperationAction(ISD::CTLZ, VT, Expand);
253 static const MVT::SimpleValueType IntTypes[] = {
254 MVT::v2i32, MVT::v4i32
257 for (MVT VT : IntTypes) {
258 // Expand the following operations for the current type by default.
259 setOperationAction(ISD::ADD, VT, Expand);
260 setOperationAction(ISD::AND, VT, Expand);
261 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
262 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
263 setOperationAction(ISD::MUL, VT, Expand);
264 setOperationAction(ISD::OR, VT, Expand);
265 setOperationAction(ISD::SHL, VT, Expand);
266 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
267 setOperationAction(ISD::SRL, VT, Expand);
268 setOperationAction(ISD::SRA, VT, Expand);
269 setOperationAction(ISD::SUB, VT, Expand);
270 setOperationAction(ISD::UDIV, VT, Expand);
271 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
272 setOperationAction(ISD::UREM, VT, Expand);
273 setOperationAction(ISD::SELECT, VT, Expand);
274 setOperationAction(ISD::VSELECT, VT, Expand);
275 setOperationAction(ISD::XOR, VT, Expand);
276 setOperationAction(ISD::BSWAP, VT, Expand);
277 setOperationAction(ISD::CTPOP, VT, Expand);
278 setOperationAction(ISD::CTTZ, VT, Expand);
279 setOperationAction(ISD::CTLZ, VT, Expand);
282 static const MVT::SimpleValueType FloatTypes[] = {
283 MVT::v2f32, MVT::v4f32
286 for (MVT VT : FloatTypes) {
287 setOperationAction(ISD::FABS, VT, Expand);
288 setOperationAction(ISD::FADD, VT, Expand);
289 setOperationAction(ISD::FCOS, VT, Expand);
290 setOperationAction(ISD::FDIV, VT, Expand);
291 setOperationAction(ISD::FPOW, VT, Expand);
292 setOperationAction(ISD::FFLOOR, VT, Expand);
293 setOperationAction(ISD::FTRUNC, VT, Expand);
294 setOperationAction(ISD::FMUL, VT, Expand);
295 setOperationAction(ISD::FRINT, VT, Expand);
296 setOperationAction(ISD::FSQRT, VT, Expand);
297 setOperationAction(ISD::FSIN, VT, Expand);
298 setOperationAction(ISD::FSUB, VT, Expand);
299 setOperationAction(ISD::FNEG, VT, Expand);
300 setOperationAction(ISD::SELECT, VT, Expand);
301 setOperationAction(ISD::VSELECT, VT, Expand);
302 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
305 setTargetDAGCombine(ISD::MUL);
306 setTargetDAGCombine(ISD::SELECT_CC);
309 //===----------------------------------------------------------------------===//
310 // Target Information
311 //===----------------------------------------------------------------------===//
313 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
317 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
319 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
322 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
323 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
325 return ((LScalarSize <= CastScalarSize) ||
326 (CastScalarSize >= 32) ||
330 //===---------------------------------------------------------------------===//
332 //===---------------------------------------------------------------------===//
334 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
335 assert(VT.isFloatingPoint());
336 return VT == MVT::f32;
339 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
340 assert(VT.isFloatingPoint());
341 return VT == MVT::f32;
344 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
345 // Truncate is just accessing a subregister.
346 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
349 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
350 // Truncate is just accessing a subregister.
351 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
352 (Dest->getPrimitiveSizeInBits() % 32 == 0);
355 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
356 const DataLayout *DL = getDataLayout();
357 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
358 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
360 return SrcSize == 32 && DestSize == 64;
363 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
364 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
365 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
366 // this will enable reducing 64-bit operations the 32-bit, which is always
368 return Src == MVT::i32 && Dest == MVT::i64;
371 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
372 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
373 // limited number of native 64-bit operations. Shrinking an operation to fit
374 // in a single 32-bit register should always be helpful. As currently used,
375 // this is much less general than the name suggests, and is only used in
376 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
377 // not profitable, and may actually be harmful.
378 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
381 //===---------------------------------------------------------------------===//
382 // TargetLowering Callbacks
383 //===---------------------------------------------------------------------===//
385 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
386 const SmallVectorImpl<ISD::InputArg> &Ins) const {
388 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
391 SDValue AMDGPUTargetLowering::LowerReturn(
393 CallingConv::ID CallConv,
395 const SmallVectorImpl<ISD::OutputArg> &Outs,
396 const SmallVectorImpl<SDValue> &OutVals,
397 SDLoc DL, SelectionDAG &DAG) const {
398 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
401 //===---------------------------------------------------------------------===//
402 // Target specific lowering
403 //===---------------------------------------------------------------------===//
405 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
406 SmallVectorImpl<SDValue> &InVals) const {
407 SDValue Callee = CLI.Callee;
408 SelectionDAG &DAG = CLI.DAG;
410 const Function &Fn = *DAG.getMachineFunction().getFunction();
412 StringRef FuncName("<unknown>");
414 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
415 FuncName = G->getSymbol();
416 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
417 FuncName = G->getGlobal()->getName();
419 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
420 DAG.getContext()->diagnose(NoCalls);
424 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
426 switch (Op.getOpcode()) {
428 Op.getNode()->dump();
429 llvm_unreachable("Custom lowering code for this"
430 "instruction is not implemented yet!");
432 // AMDIL DAG lowering
433 case ISD::SDIV: return LowerSDIV(Op, DAG);
434 case ISD::SREM: return LowerSREM(Op, DAG);
435 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
436 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
437 // AMDGPU DAG lowering
438 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
439 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
440 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
441 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
442 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
443 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
448 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
449 SmallVectorImpl<SDValue> &Results,
450 SelectionDAG &DAG) const {
451 switch (N->getOpcode()) {
452 case ISD::SIGN_EXTEND_INREG:
453 // Different parts of legalization seem to interpret which type of
454 // sign_extend_inreg is the one to check for custom lowering. The extended
455 // from type is what really matters, but some places check for custom
456 // lowering of the result type. This results in trying to use
457 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
458 // nothing here and let the illegal result integer be handled normally.
461 SDValue Op = SDValue(N, 0);
463 EVT VT = Op.getValueType();
464 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
465 N->getOperand(0), N->getOperand(1));
466 Results.push_back(UDIVREM);
470 SDValue Op = SDValue(N, 0);
472 EVT VT = Op.getValueType();
473 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
474 N->getOperand(0), N->getOperand(1));
475 Results.push_back(UDIVREM.getValue(1));
479 SDValue Op = SDValue(N, 0);
481 EVT VT = Op.getValueType();
482 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
484 SDValue one = DAG.getConstant(1, HalfVT);
485 SDValue zero = DAG.getConstant(0, HalfVT);
488 SDValue LHS = N->getOperand(0);
489 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
490 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
492 SDValue RHS = N->getOperand(1);
493 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
494 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
496 // Get Speculative values
497 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
498 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
500 SDValue REM_Hi = zero;
501 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
503 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
504 SDValue DIV_Lo = zero;
506 const unsigned halfBitWidth = HalfVT.getSizeInBits();
508 for (unsigned i = 0; i < halfBitWidth; ++i) {
509 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
510 // Get Value of high bit
512 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
513 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
515 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
516 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
519 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
520 DAG.getConstant(halfBitWidth - 1, HalfVT));
521 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
522 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
524 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
525 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
528 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
530 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
531 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
533 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
537 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
539 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
540 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
541 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
544 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
545 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
546 Results.push_back(DIV);
547 Results.push_back(REM);
555 // FIXME: This implements accesses to initialized globals in the constant
556 // address space by copying them to private and accessing that. It does not
557 // properly handle illegal types or vectors. The private vector loads are not
558 // scalarized, and the illegal scalars hit an assertion. This technique will not
559 // work well with large initializers, and this should eventually be
560 // removed. Initialized globals should be placed into a data section that the
561 // runtime will load into a buffer before the kernel is executed. Uses of the
562 // global need to be replaced with a pointer loaded from an implicit kernel
563 // argument into this buffer holding the copy of the data, which will remove the
564 // need for any of this.
565 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
566 const GlobalValue *GV,
567 const SDValue &InitPtr,
569 SelectionDAG &DAG) const {
570 const DataLayout *TD = getTargetMachine().getDataLayout();
572 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
573 EVT VT = EVT::getEVT(CI->getType());
574 PointerType *PtrTy = PointerType::get(CI->getType(), 0);
575 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
576 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
577 TD->getPrefTypeAlignment(CI->getType()));
580 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
581 EVT VT = EVT::getEVT(CFP->getType());
582 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
583 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
584 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
585 TD->getPrefTypeAlignment(CFP->getType()));
588 Type *InitTy = Init->getType();
589 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
590 const StructLayout *SL = TD->getStructLayout(ST);
592 EVT PtrVT = InitPtr.getValueType();
593 SmallVector<SDValue, 8> Chains;
595 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
596 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
597 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
599 Constant *Elt = Init->getAggregateElement(I);
600 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
603 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
606 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
607 EVT PtrVT = InitPtr.getValueType();
609 unsigned NumElements;
610 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
611 NumElements = AT->getNumElements();
612 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
613 NumElements = VT->getNumElements();
615 llvm_unreachable("Unexpected type");
617 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
618 SmallVector<SDValue, 8> Chains;
619 for (unsigned i = 0; i < NumElements; ++i) {
620 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
621 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
623 Constant *Elt = Init->getAggregateElement(i);
624 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
627 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
631 llvm_unreachable("Unhandled constant initializer");
634 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
636 SelectionDAG &DAG) const {
638 const DataLayout *TD = getTargetMachine().getDataLayout();
639 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
640 const GlobalValue *GV = G->getGlobal();
642 switch (G->getAddressSpace()) {
643 default: llvm_unreachable("Global Address lowering not implemented for this "
645 case AMDGPUAS::LOCAL_ADDRESS: {
646 // XXX: What does the value of G->getOffset() mean?
647 assert(G->getOffset() == 0 &&
648 "Do not know what to do with an non-zero offset");
651 if (MFI->LocalMemoryObjects.count(GV) == 0) {
652 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
653 Offset = MFI->LDSSize;
654 MFI->LocalMemoryObjects[GV] = Offset;
655 // XXX: Account for alignment?
656 MFI->LDSSize += Size;
658 Offset = MFI->LocalMemoryObjects[GV];
661 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
663 case AMDGPUAS::CONSTANT_ADDRESS: {
664 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
665 Type *EltType = GV->getType()->getElementType();
666 unsigned Size = TD->getTypeAllocSize(EltType);
667 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
669 const GlobalVariable *Var = cast<GlobalVariable>(GV);
670 const Constant *Init = Var->getInitializer();
671 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
672 SDValue InitPtr = DAG.getFrameIndex(FI,
673 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
674 SmallVector<SDNode*, 8> WorkList;
676 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
677 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
678 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
680 WorkList.push_back(*I);
682 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
683 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
684 E = WorkList.end(); I != E; ++I) {
685 SmallVector<SDValue, 8> Ops;
686 Ops.push_back(Chain);
687 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
688 Ops.push_back((*I)->getOperand(i));
690 DAG.UpdateNodeOperands(*I, Ops);
692 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op),
693 getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
698 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
699 SelectionDAG &DAG) const {
700 SmallVector<SDValue, 8> Args;
701 SDValue A = Op.getOperand(0);
702 SDValue B = Op.getOperand(1);
704 DAG.ExtractVectorElements(A, Args);
705 DAG.ExtractVectorElements(B, Args);
707 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
710 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
711 SelectionDAG &DAG) const {
713 SmallVector<SDValue, 8> Args;
714 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
715 EVT VT = Op.getValueType();
716 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
717 VT.getVectorNumElements());
719 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
722 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
723 SelectionDAG &DAG) const {
725 MachineFunction &MF = DAG.getMachineFunction();
726 const AMDGPUFrameLowering *TFL =
727 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
729 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
731 unsigned FrameIndex = FIN->getIndex();
732 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
733 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
737 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
738 SelectionDAG &DAG) const {
739 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
741 EVT VT = Op.getValueType();
743 switch (IntrinsicID) {
745 case AMDGPUIntrinsic::AMDIL_abs:
746 return LowerIntrinsicIABS(Op, DAG);
747 case AMDGPUIntrinsic::AMDIL_exp:
748 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
749 case AMDGPUIntrinsic::AMDGPU_lrp:
750 return LowerIntrinsicLRP(Op, DAG);
751 case AMDGPUIntrinsic::AMDIL_fraction:
752 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
753 case AMDGPUIntrinsic::AMDIL_max:
754 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
756 case AMDGPUIntrinsic::AMDGPU_imax:
757 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
759 case AMDGPUIntrinsic::AMDGPU_umax:
760 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
762 case AMDGPUIntrinsic::AMDIL_min:
763 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
765 case AMDGPUIntrinsic::AMDGPU_imin:
766 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
768 case AMDGPUIntrinsic::AMDGPU_umin:
769 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
772 case AMDGPUIntrinsic::AMDGPU_umul24:
773 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
774 Op.getOperand(1), Op.getOperand(2));
776 case AMDGPUIntrinsic::AMDGPU_imul24:
777 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
778 Op.getOperand(1), Op.getOperand(2));
780 case AMDGPUIntrinsic::AMDGPU_umad24:
781 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
782 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
784 case AMDGPUIntrinsic::AMDGPU_imad24:
785 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
786 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
788 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
789 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
794 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
795 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
800 case AMDGPUIntrinsic::AMDGPU_bfi:
801 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
806 case AMDGPUIntrinsic::AMDGPU_bfm:
807 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
811 case AMDGPUIntrinsic::AMDIL_round_nearest:
812 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
816 ///IABS(a) = SMAX(sub(0, a), a)
817 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
818 SelectionDAG &DAG) const {
820 EVT VT = Op.getValueType();
821 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
824 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
827 /// Linear Interpolation
828 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
829 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
830 SelectionDAG &DAG) const {
832 EVT VT = Op.getValueType();
833 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
834 DAG.getConstantFP(1.0f, MVT::f32),
836 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
838 return DAG.getNode(ISD::FADD, DL, VT,
839 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
843 /// \brief Generate Min/Max node
844 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
845 SelectionDAG &DAG) const {
847 EVT VT = N->getValueType(0);
849 SDValue LHS = N->getOperand(0);
850 SDValue RHS = N->getOperand(1);
851 SDValue True = N->getOperand(2);
852 SDValue False = N->getOperand(3);
853 SDValue CC = N->getOperand(4);
855 if (VT != MVT::f32 ||
856 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
860 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
874 llvm_unreachable("Operation should already be optimised!");
881 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
882 return DAG.getNode(Opc, DL, VT, LHS, RHS);
890 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
891 return DAG.getNode(Opc, DL, VT, LHS, RHS);
893 case ISD::SETCC_INVALID:
894 llvm_unreachable("Invalid setcc condcode!");
899 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
900 SelectionDAG &DAG) const {
901 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
902 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
903 EVT EltVT = Op.getValueType().getVectorElementType();
904 EVT PtrVT = Load->getBasePtr().getValueType();
905 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
906 SmallVector<SDValue, 8> Loads;
909 for (unsigned i = 0, e = NumElts; i != e; ++i) {
910 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
911 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
912 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
913 Load->getChain(), Ptr,
914 MachinePointerInfo(Load->getMemOperand()->getValue()),
915 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
916 Load->getAlignment()));
918 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
921 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
922 SelectionDAG &DAG) const {
923 StoreSDNode *Store = cast<StoreSDNode>(Op);
924 EVT MemVT = Store->getMemoryVT();
925 unsigned MemBits = MemVT.getSizeInBits();
927 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
928 // truncating store into an i32 store.
929 // XXX: We could also handle optimize other vector bitwidths.
930 if (!MemVT.isVector() || MemBits > 32) {
935 SDValue Value = Store->getValue();
936 EVT VT = Value.getValueType();
937 EVT ElemVT = VT.getVectorElementType();
938 SDValue Ptr = Store->getBasePtr();
939 EVT MemEltVT = MemVT.getVectorElementType();
940 unsigned MemEltBits = MemEltVT.getSizeInBits();
941 unsigned MemNumElements = MemVT.getVectorNumElements();
942 unsigned PackedSize = MemVT.getStoreSizeInBits();
943 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
945 assert(Value.getValueType().getScalarSizeInBits() >= 32);
948 for (unsigned i = 0; i < MemNumElements; ++i) {
949 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
950 DAG.getConstant(i, MVT::i32));
951 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
952 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
954 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
955 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
960 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
964 if (PackedSize < 32) {
965 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
966 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
967 Store->getMemOperand()->getPointerInfo(),
969 Store->isNonTemporal(), Store->isVolatile(),
970 Store->getAlignment());
973 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
974 Store->getMemOperand()->getPointerInfo(),
975 Store->isVolatile(), Store->isNonTemporal(),
976 Store->getAlignment());
979 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
980 SelectionDAG &DAG) const {
981 StoreSDNode *Store = cast<StoreSDNode>(Op);
982 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
983 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
984 EVT PtrVT = Store->getBasePtr().getValueType();
985 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
988 SmallVector<SDValue, 8> Chains;
990 for (unsigned i = 0, e = NumElts; i != e; ++i) {
991 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
992 Store->getValue(), DAG.getConstant(i, MVT::i32));
993 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
995 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
997 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
998 MachinePointerInfo(Store->getMemOperand()->getValue()),
999 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
1000 Store->getAlignment()));
1002 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1005 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1007 LoadSDNode *Load = cast<LoadSDNode>(Op);
1008 ISD::LoadExtType ExtType = Load->getExtensionType();
1009 EVT VT = Op.getValueType();
1010 EVT MemVT = Load->getMemoryVT();
1012 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1013 // We can do the extload to 32-bits, and then need to separately extend to
1016 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1020 Load->getMemOperand());
1021 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
1024 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1025 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1026 // FIXME: Copied from PPC
1027 // First, load into 32 bits, then truncate to 1 bit.
1029 SDValue Chain = Load->getChain();
1030 SDValue BasePtr = Load->getBasePtr();
1031 MachineMemOperand *MMO = Load->getMemOperand();
1033 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1034 BasePtr, MVT::i8, MMO);
1035 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1038 // Lower loads constant address space global variable loads
1039 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1040 isa<GlobalVariable>(
1041 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
1043 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
1044 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1045 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1046 DAG.getConstant(2, MVT::i32));
1047 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1048 Load->getChain(), Ptr,
1049 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1052 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1053 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1057 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1058 DAG.getConstant(2, MVT::i32));
1059 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1060 Load->getChain(), Ptr,
1061 DAG.getTargetConstant(0, MVT::i32),
1063 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1065 DAG.getConstant(0x3, MVT::i32));
1066 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1067 DAG.getConstant(3, MVT::i32));
1069 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1071 EVT MemEltVT = MemVT.getScalarType();
1072 if (ExtType == ISD::SEXTLOAD) {
1073 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1074 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1077 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1080 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1082 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1083 if (Result.getNode()) {
1087 StoreSDNode *Store = cast<StoreSDNode>(Op);
1088 SDValue Chain = Store->getChain();
1089 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1090 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1091 Store->getValue().getValueType().isVector()) {
1092 return SplitVectorStore(Op, DAG);
1095 EVT MemVT = Store->getMemoryVT();
1096 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1097 MemVT.bitsLT(MVT::i32)) {
1099 if (Store->getMemoryVT() == MVT::i8) {
1101 } else if (Store->getMemoryVT() == MVT::i16) {
1104 SDValue BasePtr = Store->getBasePtr();
1105 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1106 DAG.getConstant(2, MVT::i32));
1107 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1108 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1110 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1111 DAG.getConstant(0x3, MVT::i32));
1113 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1114 DAG.getConstant(3, MVT::i32));
1116 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1119 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1121 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1122 MaskedValue, ShiftAmt);
1124 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1126 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1127 DAG.getConstant(0xffffffff, MVT::i32));
1128 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1130 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1131 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1132 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1137 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1138 SelectionDAG &DAG) const {
1140 EVT VT = Op.getValueType();
1142 SDValue Num = Op.getOperand(0);
1143 SDValue Den = Op.getOperand(1);
1145 // RCP = URECIP(Den) = 2^32 / Den + e
1146 // e is rounding error.
1147 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1149 // RCP_LO = umulo(RCP, Den) */
1150 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1152 // RCP_HI = mulhu (RCP, Den) */
1153 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1155 // NEG_RCP_LO = -RCP_LO
1156 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1159 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1160 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1163 // Calculate the rounding error from the URECIP instruction
1164 // E = mulhu(ABS_RCP_LO, RCP)
1165 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1167 // RCP_A_E = RCP + E
1168 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1170 // RCP_S_E = RCP - E
1171 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1173 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1174 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1177 // Quotient = mulhu(Tmp0, Num)
1178 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1180 // Num_S_Remainder = Quotient * Den
1181 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1183 // Remainder = Num - Num_S_Remainder
1184 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1186 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1187 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1188 DAG.getConstant(-1, VT),
1189 DAG.getConstant(0, VT),
1191 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1192 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1194 DAG.getConstant(-1, VT),
1195 DAG.getConstant(0, VT),
1197 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1198 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1201 // Calculate Division result:
1203 // Quotient_A_One = Quotient + 1
1204 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1205 DAG.getConstant(1, VT));
1207 // Quotient_S_One = Quotient - 1
1208 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1209 DAG.getConstant(1, VT));
1211 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1212 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1213 Quotient, Quotient_A_One, ISD::SETEQ);
1215 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1216 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1217 Quotient_S_One, Div, ISD::SETEQ);
1219 // Calculate Rem result:
1221 // Remainder_S_Den = Remainder - Den
1222 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1224 // Remainder_A_Den = Remainder + Den
1225 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1227 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1228 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1229 Remainder, Remainder_S_Den, ISD::SETEQ);
1231 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1232 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1233 Remainder_A_Den, Rem, ISD::SETEQ);
1238 return DAG.getMergeValues(Ops, DL);
1241 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1242 SelectionDAG &DAG) const {
1243 SDValue S0 = Op.getOperand(0);
1245 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1248 // f32 uint_to_fp i64
1249 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1250 DAG.getConstant(0, MVT::i32));
1251 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1252 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1253 DAG.getConstant(1, MVT::i32));
1254 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1255 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1256 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1257 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1261 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1263 SelectionDAG &DAG) const {
1264 MVT VT = Op.getSimpleValueType();
1266 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1267 // Shift left by 'Shift' bits.
1268 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1269 // Signed shift Right by 'Shift' bits.
1270 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1273 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1274 SelectionDAG &DAG) const {
1275 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1276 MVT VT = Op.getSimpleValueType();
1277 MVT ScalarVT = VT.getScalarType();
1282 SDValue Src = Op.getOperand(0);
1285 // TODO: Don't scalarize on Evergreen?
1286 unsigned NElts = VT.getVectorNumElements();
1287 SmallVector<SDValue, 8> Args;
1288 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1290 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1291 for (unsigned I = 0; I < NElts; ++I)
1292 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1294 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1297 //===----------------------------------------------------------------------===//
1298 // Custom DAG optimizations
1299 //===----------------------------------------------------------------------===//
1301 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1302 APInt KnownZero, KnownOne;
1303 EVT VT = Op.getValueType();
1304 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1306 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1309 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1310 EVT VT = Op.getValueType();
1312 // In order for this to be a signed 24-bit value, bit 23, must
1314 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1315 // as unsigned 24-bit values.
1316 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1319 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1321 SelectionDAG &DAG = DCI.DAG;
1322 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1323 EVT VT = Op.getValueType();
1325 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1326 APInt KnownZero, KnownOne;
1327 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1328 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1329 DCI.CommitTargetLoweringOpt(TLO);
1332 template <typename IntTy>
1333 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1334 uint32_t Offset, uint32_t Width) {
1335 if (Width + Offset < 32) {
1336 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1337 return DAG.getConstant(Result, MVT::i32);
1340 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1343 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1344 DAGCombinerInfo &DCI) const {
1345 SelectionDAG &DAG = DCI.DAG;
1348 switch(N->getOpcode()) {
1351 EVT VT = N->getValueType(0);
1352 SDValue N0 = N->getOperand(0);
1353 SDValue N1 = N->getOperand(1);
1356 // FIXME: Add support for 24-bit multiply with 64-bit output on SI.
1357 if (VT.isVector() || VT.getSizeInBits() > 32)
1360 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1361 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1362 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1363 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1364 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1365 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1366 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1367 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1372 // We need to use sext even for MUL_U24, because MUL_U24 is used
1373 // for signed multiply of 8 and 16-bit types.
1374 SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
1378 case AMDGPUISD::MUL_I24:
1379 case AMDGPUISD::MUL_U24: {
1380 SDValue N0 = N->getOperand(0);
1381 SDValue N1 = N->getOperand(1);
1382 simplifyI24(N0, DCI);
1383 simplifyI24(N1, DCI);
1386 case ISD::SELECT_CC: {
1387 return CombineMinMax(N, DAG);
1389 case AMDGPUISD::BFE_I32:
1390 case AMDGPUISD::BFE_U32: {
1391 assert(!N->getValueType(0).isVector() &&
1392 "Vector handling of BFE not implemented");
1393 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
1397 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
1399 return DAG.getConstant(0, MVT::i32);
1401 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
1405 SDValue BitsFrom = N->getOperand(0);
1406 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
1408 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
1410 if (OffsetVal == 0) {
1411 // This is already sign / zero extended, so try to fold away extra BFEs.
1412 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
1414 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
1415 if (OpSignBits >= SignBits)
1418 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
1420 // This is a sign_extend_inreg. Replace it to take advantage of existing
1421 // DAG Combines. If not eliminated, we will match back to BFE during
1424 // TODO: The sext_inreg of extended types ends, although we can could
1425 // handle them in a single BFE.
1426 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
1427 DAG.getValueType(SmallVT));
1430 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
1433 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1435 return constantFoldBFE<int32_t>(DAG,
1436 Val->getSExtValue(),
1441 return constantFoldBFE<uint32_t>(DAG,
1442 Val->getZExtValue(),
1447 APInt Demanded = APInt::getBitsSet(32,
1449 OffsetVal + WidthVal);
1451 if ((OffsetVal + WidthVal) >= 32) {
1452 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
1453 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1454 BitsFrom, ShiftVal);
1457 APInt KnownZero, KnownOne;
1458 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1459 !DCI.isBeforeLegalizeOps());
1460 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1461 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
1462 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
1463 DCI.CommitTargetLoweringOpt(TLO);
1472 //===----------------------------------------------------------------------===//
1474 //===----------------------------------------------------------------------===//
1476 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1479 const SmallVectorImpl<ISD::InputArg> &Ins,
1480 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1482 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1483 if (Ins[i].ArgVT == Ins[i].VT) {
1484 OrigIns.push_back(Ins[i]);
1489 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
1490 // Vector has been split into scalars.
1491 VT = Ins[i].ArgVT.getVectorElementType();
1492 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
1493 Ins[i].ArgVT.getVectorElementType() !=
1494 Ins[i].VT.getVectorElementType()) {
1495 // Vector elements have been promoted
1498 // Vector has been spilt into smaller vectors.
1502 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
1503 Ins[i].OrigArgIndex, Ins[i].PartOffset);
1504 OrigIns.push_back(Arg);
1508 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
1509 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1510 return CFP->isExactlyValue(1.0);
1512 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1513 return C->isAllOnesValue();
1518 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
1519 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1520 return CFP->getValueAPF().isZero();
1522 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1523 return C->isNullValue();
1528 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1529 const TargetRegisterClass *RC,
1530 unsigned Reg, EVT VT) const {
1531 MachineFunction &MF = DAG.getMachineFunction();
1532 MachineRegisterInfo &MRI = MF.getRegInfo();
1533 unsigned VirtualRegister;
1534 if (!MRI.isLiveIn(Reg)) {
1535 VirtualRegister = MRI.createVirtualRegister(RC);
1536 MRI.addLiveIn(Reg, VirtualRegister);
1538 VirtualRegister = MRI.getLiveInVirtReg(Reg);
1540 return DAG.getRegister(VirtualRegister, VT);
1543 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
1545 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
1547 default: return nullptr;
1549 NODE_NAME_CASE(CALL);
1550 NODE_NAME_CASE(UMUL);
1551 NODE_NAME_CASE(DIV_INF);
1552 NODE_NAME_CASE(RET_FLAG);
1553 NODE_NAME_CASE(BRANCH_COND);
1556 NODE_NAME_CASE(DWORDADDR)
1557 NODE_NAME_CASE(FRACT)
1558 NODE_NAME_CASE(FMAX)
1559 NODE_NAME_CASE(SMAX)
1560 NODE_NAME_CASE(UMAX)
1561 NODE_NAME_CASE(FMIN)
1562 NODE_NAME_CASE(SMIN)
1563 NODE_NAME_CASE(UMIN)
1564 NODE_NAME_CASE(BFE_U32)
1565 NODE_NAME_CASE(BFE_I32)
1568 NODE_NAME_CASE(MUL_U24)
1569 NODE_NAME_CASE(MUL_I24)
1570 NODE_NAME_CASE(MAD_U24)
1571 NODE_NAME_CASE(MAD_I24)
1572 NODE_NAME_CASE(URECIP)
1573 NODE_NAME_CASE(DOT4)
1574 NODE_NAME_CASE(EXPORT)
1575 NODE_NAME_CASE(CONST_ADDRESS)
1576 NODE_NAME_CASE(REGISTER_LOAD)
1577 NODE_NAME_CASE(REGISTER_STORE)
1578 NODE_NAME_CASE(LOAD_CONSTANT)
1579 NODE_NAME_CASE(LOAD_INPUT)
1580 NODE_NAME_CASE(SAMPLE)
1581 NODE_NAME_CASE(SAMPLEB)
1582 NODE_NAME_CASE(SAMPLED)
1583 NODE_NAME_CASE(SAMPLEL)
1584 NODE_NAME_CASE(STORE_MSKOR)
1585 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
1589 static void computeKnownBitsForMinMax(const SDValue Op0,
1593 const SelectionDAG &DAG,
1595 APInt Op0Zero, Op0One;
1596 APInt Op1Zero, Op1One;
1597 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
1598 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
1600 KnownZero = Op0Zero & Op1Zero;
1601 KnownOne = Op0One & Op1One;
1604 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
1608 const SelectionDAG &DAG,
1609 unsigned Depth) const {
1611 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
1615 unsigned Opc = Op.getOpcode();
1620 case ISD::INTRINSIC_WO_CHAIN: {
1621 // FIXME: The intrinsic should just use the node.
1622 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
1623 case AMDGPUIntrinsic::AMDGPU_imax:
1624 case AMDGPUIntrinsic::AMDGPU_umax:
1625 case AMDGPUIntrinsic::AMDGPU_imin:
1626 case AMDGPUIntrinsic::AMDGPU_umin:
1627 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
1628 KnownZero, KnownOne, DAG, Depth);
1636 case AMDGPUISD::SMAX:
1637 case AMDGPUISD::UMAX:
1638 case AMDGPUISD::SMIN:
1639 case AMDGPUISD::UMIN:
1640 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
1641 KnownZero, KnownOne, DAG, Depth);
1644 case AMDGPUISD::BFE_I32:
1645 case AMDGPUISD::BFE_U32: {
1646 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
1650 unsigned BitWidth = 32;
1651 uint32_t Width = CWidth->getZExtValue() & 0x1f;
1653 KnownZero = APInt::getAllOnesValue(BitWidth);
1654 KnownOne = APInt::getNullValue(BitWidth);
1658 // FIXME: This could do a lot more. If offset is 0, should be the same as
1659 // sign_extend_inreg implementation, but that involves duplicating it.
1660 if (Opc == AMDGPUISD::BFE_I32)
1661 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
1663 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
1670 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
1672 const SelectionDAG &DAG,
1673 unsigned Depth) const {
1674 switch (Op.getOpcode()) {
1675 case AMDGPUISD::BFE_I32: {
1676 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
1680 unsigned SignBits = 32 - Width->getZExtValue() + 1;
1681 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1682 if (!Offset || !Offset->isNullValue())
1685 // TODO: Could probably figure something out with non-0 offsets.
1686 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
1687 return std::max(SignBits, Op0SignBits);
1690 case AMDGPUISD::BFE_U32: {
1691 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
1692 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;