Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
[oota-llvm.git] / test / MC / Disassembler /
2013-07-31 Kevin EnderbyAdded the B9.3.19 SUBS PC, LR, #imm (Thumb2) system...
2013-07-31 Richard Sandiford[SystemZ] Add RISBLG and RISBHG instruction definitions
2013-07-31 Craig TopperChanged register names (and pointer keywords) to be...
2013-07-26 Akira Hatanaka[mips] Fix FP conditional move instructions to have...
2013-07-26 Akira Hatanaka[mips] Fix FP branch instructions to have explicit...
2013-07-26 Akira Hatanaka[mips] Print instructions "beq", "bne" and "or" using...
2013-07-25 Rafael EspindolaRemove the mblaze backend from llvm.
2013-07-25 Richard Sandiford[SystemZ] Add LOCR and LOCGR
2013-07-25 Richard Sandiford[SystemZ] Add LOC and LOCG
2013-07-25 Richard Sandiford[SystemZ] Add STOC and STOCG
2013-07-23 Rafael EspindolaAdd not so that these tests pass with pipefail enabled.
2013-07-23 Craig TopperDon't let x86 asm printer use the no operand movsd...
2013-07-22 Kevin EnderbyFix the move to/from accumulator register instructions...
2013-07-19 Richard Sandiford[SystemZ] Add tests for ALHSIK and ALGHSIK
2013-07-19 Richard Sandiford[SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
2013-07-19 Joey Gouly[ARMv8] Implement the NEON instructions VRINT{N, X...
2013-07-19 Richard Sandiford[SystemZ] Add AHIK and AGHIK
2013-07-19 Richard Sandiford[SystemZ] Add ARK, AGRK, SRK and SGRK
2013-07-19 Richard Sandiford[SystemZ] Add NGRK, OGRK and XGRK
2013-07-19 Richard Sandiford[SystemZ] Add NRK, ORK and XRK
2013-07-19 Richard Sandiford[SystemZ] Start adding z196 and zEC12 support
2013-07-19 Tim NorthoverARM: delete two tests now integrated into the larger...
2013-07-19 Tim NorthoverARM: remove invalid invalid tests
2013-07-19 Tim NorthoverImprove llvm-mc disassembler mode and refactor ARM...
2013-07-18 Joey Gouly[ARMv8] Add NEON instructions VCVT{A, N, P, M}.
2013-07-18 Joey GoulyAdd Thumb tests for the ARMv8 FP instructions that...
2013-07-17 Joey GoulyAdd the tests that I forgot to 'svn add' with my previo...
2013-07-16 Richard Sandiford[SystemZ] Add MC support for R[NOX]SBG
2013-07-11 Richard Sandiford[SystemZ] Allow 8-bit operands to RISBG
2013-07-09 Joey GoulyAdd MC assembly/disassembly support for VRINT{A, N...
2013-07-09 Joey GoulyAdd MC assembly/disassembly support for VRINT{Z, X...
2013-07-09 Joey GoulyAdd MC assembly/disassembly support for VCVT{A, N,...
2013-07-06 Joey GoulyAdd MC support for the v8fp instructions: vmaxnm and...
2013-07-04 Joey GoulyAdd support for MC assembling and disassembling of...
2013-07-04 Joey GoulyAdd a V8FP instruction 'vcvt{b,t}' to convert between...
2013-07-03 Mihai PopaThis corrects the implementation of Thumb ADR instruct...
2013-07-01 Akira Hatanaka[mips] Increase the number of floating point control...
2013-06-26 Chad Rosier[Mips Disassembler] Have the DecodeCCRRegisterClass...
2013-06-26 Amaury de la VieuvilleARM: operands should be explicit when disassembled
2013-06-24 Amaury de la VieuvilleARM: check predicate bits for thumb instructions
2013-06-24 Amaury de la VieuvilleARM: rGPR is meant to be unpredictable, not undefined
2013-06-24 Amaury de la VieuvilleARM: fix thumb1 nop decoding
2013-06-24 Amaury de la VieuvilleARM: fix IT decoding
2013-06-24 Amaury de la VieuvilleARM: enable decoding of pc-relative PLD/PLI
2013-06-20 Kevin EnderbyUpdate the X86 disassembler to use xacquire and xreleas...
2013-06-20 Joey GoulyThis reverts r155000.
2013-06-18 Amaury de la VieuvilleARM: add operands pre-writeback variants when needed
2013-06-18 Amaury de la VieuvilleARM: fix thumb literal loads decoding
2013-06-18 Amaury de la VieuvilleARM: thumb stores cannot use PC as dest register
2013-06-14 Amaury de la VieuvilleARM: fix thumb coprocessor instruction with pre-writeba...
2013-06-13 Amaury de la VieuvilleARM: fix B decoding
2013-06-11 Mihai PopaThis patch adds support for FPINST/FPINST2 as operands...
2013-06-11 Amaury de la VieuvilleARM: Enforce decoding rules for VLDn instructions
2013-06-11 Amaury de la VieuvilleARM: Fix STREX/LDREX reecoding
2013-06-10 Amaury de la VieuvilleARM: ISB cannot be passed the same options as DMB
2013-06-08 Amaury de la VieuvilleARM: fix VMOVvnf32 decoding when ambiguous with VCVT
2013-06-08 Amaury de la VieuvilleARM: enforce SRS decoding constraints
2013-06-08 Amaury de la VieuvilleARM: fix CPS decoding when ambiguous with QADD
2013-06-08 Amaury de la VieuvilleARM: fix VCVT decoding
2013-06-05 Mihai PopaThis is a simple patch that changes RRX and RRXS to...
2013-05-31 Tim NorthoverARM: add fstmx and fldmx instructions for assembly
2013-05-31 Tim NorthoverARM: fix VEXT encoding corner case
2013-05-29 Richard Sandiford[SystemZ] Immediate compare-and-branch support
2013-05-28 Richard Sandiford[SystemZ] Register compare-and-branch support
2013-05-20 Mihai PopaVSTn instructions have a number of encoding constraints...
2013-05-20 Mihai PopaQ registers are encoded in fields of the same length...
2013-05-15 Richard Sandiford[SystemZ] Make use of SUBTRACT HALFWORD
2013-05-15 Richard Sandiford[SystemZ] Consolidate disassembler tests for valid...
2013-05-14 Richard Sandiford[SystemZ] Add disassembler support
2013-05-13 Mihai PopaThe purpose of the patch is to fix the syntax of ARM...
2013-05-05 Richard Osborne[XCore] Add LDAPB instructions.
2013-05-05 Richard Osborne[XCore] Add BLRB instructions.
2013-04-30 Mihai Popas tightens up the encoding description for ARM post...
2013-04-26 Quentin ColombetARM: Fix encoding of hint instruction for Thumb.
2013-04-19 Tim NorthoverARM: Permit "sp" in ARM variant of STREXD instructions
2013-04-19 Tim NorthoverARM: permit "sp" in ARM variants of MOVW/MOVT instructions
2013-04-18 Akira Hatanaka[mips] DSP-ASE move from HI/LO register instructions.
2013-04-14 Nico RieckUse object file specific section type for initial text...
2013-04-12 Quentin ColombetARM: Correct printing of pre-indexed operands.
2013-04-11 Michael LiaoAdd CLAC/STAC instruction encoding/decoding support
2013-04-10 Kay Tiong Khoofixed xsave, xsaveopt, xrstor mnemonics with intel...
2013-04-10 Tim NorthoverARM: Make "SMC" instructions conditional on new TrustZo...
2013-04-04 Richard Osborne[XCore] Add bru instruction.
2013-04-04 Richard Osborne[XCore] The RRegs register class is a superset of GRRegs.
2013-04-03 Richard Osborne[XCore] Check disassembly of the st8 instruction.
2013-04-03 Richard Osborne[XCore] Update disassembler test to improve coverage...
2013-04-03 Tim NorthoverAArch64: implement ETMv4 trace system registers.
2013-03-28 Gordon KeiserFix issue with disassembler decoding CBZ/CBNZ immediate...
2013-03-28 Tim NorthoverAArch64: implement GICv3 system registers
2013-03-26 Joe AbbeyPatch by Gordon Keiser!
2013-03-25 Dave Zarzyckix86 -- disassemble the REP/REPNE prefix when needed
2013-03-11 Kevin EnderbyFixes disassembler crashes on 2013 Haswell RTM instruct...
2013-02-28 Tim NorthoverAArch64: remove post-encoder method from FCMP (immediat...
2013-02-22 Kristof BeylsMake ARMAsmPrinter generate the correct alignment speci...
2013-02-17 Richard Osborne[XCore] Add missing 2r instructions.
2013-02-17 Richard Osborne[XCore] Add TSETR instruction.
2013-02-17 Richard Osborne[XCore] Add missing u10 / lu10 instructions.
2013-02-17 Richard Osborne[XCore] Add missing u6 / lu6 instructions.
2013-02-14 Kay Tiong Khoodeath to extra whitespace
2013-02-14 Kay Tiong Khooadded basic support for Intel ADX instructions
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