ARM: fix VMOVvnf32 decoding when ambiguous with VCVT

Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 08853cb3bb5942a9d029342a09b332953fd511b5..6f15a3d60b7958a02769b87653292080e7bc147b 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4470,11 +4470,13 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
   unsigned imm = fieldFromInstruction(Insn, 16, 6);
   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+  unsigned op = fieldFromInstruction(Insn, 5, 1);
 
   DecodeStatus S = MCDisassembler::Success;
 
   // VMOVv2f32 is ambiguous with these decodings.
   if (!(imm & 0x38) && cmode == 0xF) {
+    if (op == 1) return MCDisassembler::Fail;
     Inst.setOpcode(ARM::VMOVv2f32);
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }
@@ -4498,11 +4500,13 @@ static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
   unsigned imm = fieldFromInstruction(Insn, 16, 6);
   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+  unsigned op = fieldFromInstruction(Insn, 5, 1);
 
   DecodeStatus S = MCDisassembler::Success;
 
   // VMOVv4f32 is ambiguous with these decodings.
   if (!(imm & 0x38) && cmode == 0xF) {
+    if (op == 1) return MCDisassembler::Fail;
     Inst.setOpcode(ARM::VMOVv4f32);
     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
   }

diff --git a/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt b/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
new file mode 100644 (file)
index 0000000..9d6cd5c
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
@@ -0,0 +1,7 @@
+# VMOV cmode=0b1111 op=1
+# RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# VMOV cmode=0b1111 op=1
+# RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding