[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg

function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 4af67037e970ad75b1cef0458143aea6a3dae270..b6b265cd1ed12a24d83519e22bfff907e638efe5 100644 (file)
--- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -405,7 +405,10 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
                                            unsigned RegNo,
                                            uint64_t Address,
                                            const void *Decoder) {
-  Inst.addOperand(MCOperand::CreateReg(RegNo));
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
+  Inst.addOperand(MCOperand::CreateReg(Reg));
   return MCDisassembler::Success;
 }
 

diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt
index ef8bf71bd3a6dd19f2be4400f6edf33a858ff93c..5c2d5ca4768e7ba16dd99ec4af2582e7c3eb74c9 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32.txt
+++ b/test/MC/Disassembler/Mips/mips32.txt
@@ -158,8 +158,8 @@
 # CHECK: ceil.w.s $f6, $f7
 0x46 0x00 0x39 0x8e
 
-# CHECK: cfc1  $6, $7
-0x44 0x46 0x38 0x00
+# CHECK: cfc1  $6, $fcc0
+0x44 0x46 0x08 0x00
 
 # CHECK: clo  $6, $7
 0x70 0xe6 0x30 0x21
@@ -167,8 +167,8 @@
 # CHECK: clz  $6, $7
 0x70 0xe6 0x30 0x20
 
-# CHECK: ctc1  $6, $7
-0x44 0xc6 0x38 0x00
+# CHECK: ctc1  $6, $fcc0
+0x44 0xc6 0x08 0x00
 
 # CHECK: cvt.d.s $f6, $f7
 0x46 0x00 0x39 0xa1

diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt
index a0885a4bfe853bdefc492559b6a99a6c9522a1aa..f0553c68f88c4704b0e10597661d7f7039ce0593 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32_le.txt
+++ b/test/MC/Disassembler/Mips/mips32_le.txt
@@ -158,8 +158,8 @@
 # CHECK: ceil.w.s $f6, $f7
 0x8e 0x39 0x00 0x46
 
-# CHECK: cfc1  $6, $7
-0x00 0x38 0x46 0x44
+# CHECK: cfc1  $6, $fcc0
+0x00 0x08 0x46 0x44
 
 # CHECK: clo  $6, $7
 0x21 0x30 0xe6 0x70
@@ -167,8 +167,8 @@
 # CHECK: clz  $6, $7
 0x20 0x30 0xe6 0x70
 
-# CHECK: ctc1  $6, $7
-0x00 0x38 0xc6 0x44
+# CHECK: ctc1  $6, $fcc0
+0x00 0x08 0xc6 0x44
 
 # CHECK: cvt.d.s $f6, $f7
 0xa1 0x39 0x00 0x46

diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt
index 991eaa6cc97fe3eddf6bfa4f592dd1de2eb85c60..ac20e411c1f49aaa5f9d89aaf1f8f7b4b8528748 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32r2.txt
+++ b/test/MC/Disassembler/Mips/mips32r2.txt
@@ -158,8 +158,8 @@
 # CHECK: ceil.w.s $f6, $f7
 0x46 0x00 0x39 0x8e
 
-# CHECK: cfc1  $6, $7
-0x44 0x46 0x38 0x00
+# CHECK: cfc1  $6, $fcc0
+0x44 0x46 0x08 0x00
 
 # CHECK: clo  $6, $7
 0x70 0xe6 0x30 0x21
@@ -167,8 +167,8 @@
 # CHECK: clz  $6, $7
 0x70 0xe6 0x30 0x20
 
-# CHECK: ctc1  $6, $7
-0x44 0xc6 0x38 0x00
+# CHECK: ctc1  $6, $fcc0
+0x44 0xc6 0x08 0x00
 
 # CHECK: cvt.d.s $f6, $f7
 0x46 0x00 0x39 0xa1

diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt
index 10c293821c9dd22aae2e9f3ba816042ad9c84ed8..a9131a35f8c0e434a5ab0c21c0527c1ac8bf58ba 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32r2_le.txt
+++ b/test/MC/Disassembler/Mips/mips32r2_le.txt
@@ -158,8 +158,8 @@
 # CHECK: ceil.w.s $f6, $f7
 0x8e 0x39 0x00 0x46
 
-# CHECK: cfc1  $6, $7
-0x00 0x38 0x46 0x44
+# CHECK: cfc1  $6, $fcc0
+0x00 0x08 0x46 0x44
 
 # CHECK: clo  $6, $7
 0x21 0x30 0xe6 0x70
@@ -167,8 +167,8 @@
 # CHECK: clz  $6, $7
 0x20 0x30 0xe6 0x70
 
-# CHECK: ctc1  $6, $7
-0x00 0x38 0xc6 0x44
+# CHECK: ctc1  $6, $fcc0
+0x00 0x08 0xc6 0x44
 
 # CHECK: cvt.d.s $f6, $f7
 0xa1 0x39 0x00 0x46