imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
if (Inst.getOpcode() == ARM::MOVTi16)
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
# CHECK: mov r3, #7
# CHECK: mov r4, #4080
# CHECK: mov r5, #16711680
+# CHECK: mov sp, #35
# CHECK: movw r6, #65535
# CHECK: movw r9, #65535
+# CHECK: movw sp, #1193
# CHECK: movs r3, #7
# CHECK: moveq r4, #4080
# CHECK: movseq r5, #16711680
0x07 0x30 0xa0 0xe3
0xff 0x4e 0xa0 0xe3
0xff 0x58 0xa0 0xe3
+0x23 0xd0 0xa0 0xe3
0xff 0x6f 0x0f 0xe3
0xff 0x9f 0x0f 0xe3
+0xa9 0xd4 0x00 0xe3
0x07 0x30 0xb0 0xe3
0xff 0x4e 0xa0 0x03
0xff 0x58 0xb0 0x03
#------------------------------------------------------------------------------
# CHECK: movt r3, #7
# CHECK: movt r6, #65535
+# CHECK: movt sp, #3397
# CHECK: movteq r4, #4080
0x07 0x30 0x40 0xe3
0xff 0x6f 0x4f 0xe3
+0x45 0xdd 0x40 0xe3
0xf0 0x4f 0x40 0x03