AArch64: fix vector-immediate BIC/ORR on big-endian devices.
[oota-llvm.git] / test / CodeGen /
2014-09-04 Tim NorthoverAArch64: fix vector-immediate BIC/ORR on big-endian...
2014-09-04 Tim NorthoverAArch64: fix big-endian immediate materialisation
2014-09-04 Chandler Carruth[x86] Teach the new v4i32 shuffle lowering some more...
2014-09-04 Juergen RibutzkaRevert r216803 "[MachineSinking] Clear kill flag of...
2014-09-04 Juergen Ributzka[FastISel][AArch64] Add target-specific lowering for...
2014-09-04 Chandler Carruth[x86] Teach the new vector shuffle lowering about the...
2014-09-03 Matt ArsenaultR600/SI: Try to keep i32 mul on SALU
2014-09-03 Chandler Carruth[x86] Teach the new vector shuffle lowering about the...
2014-09-03 Chandler Carruth[x86] Add an SSE4.1 mode to this test.
2014-09-03 Chandler Carruth[x86] Make this test check everything for both SSE2...
2014-09-03 Lang HamesAdd a regression test to sanity check the PBQP allocator.
2014-09-03 Tom StellardR600/SI: Add a pattern for i64 and in a branch
2014-09-03 Renato GolinCheck-label a bit more specific
2014-09-03 Alexander PotapenkoFix PR20800: correctly calculate the offset of the...
2014-09-03 Juergen RibutzkaReapply r216805 "[MachineCombiner][AArch64] Use the...
2014-09-03 Juergen Ributzka[FastISel][AArch64] Add target-dependent instruction...
2014-09-02 Renato GolinMissing test from r216989
2014-09-02 Renato GolinOnly emit movw on ARMv6T2+
2014-09-02 Juergen Ributzka[FastISel][AArch64] Use the target-dependent selection...
2014-09-02 Robin Morisset[X86] Allow atomic operations using immediates to avoid...
2014-09-02 Matt ArsenaultR600/SI: Relax some ordering in tests.
2014-09-02 Matt ArsenaultR600/SI: Fix hardcoded register numbers in test
2014-09-02 Matt ArsenaultR600/SI: Add failing testcase.
2014-09-02 Matt ArsenaultFix interference caused by fmul 2, x -> fadd x, x
2014-09-02 Reid KlecknerCodeGen: Handle va_start in the entry block
2014-09-02 Hal FinkelEnable splitting indexing from loads with TargetConstants
2014-09-02 Rafael EspindolaReplace -use-init-array with -use-ctors.
2014-09-02 David XuMerge Extend and Shift into a UBFX
2014-09-02 Hal FinkelRevert "Revert '[DAGCombiner] Split up an indexed load...
2014-09-01 Jingyue WuFix a typo in comments in r216862, NFC
2014-09-01 Tilmann Scheller[ARM] Add Thumb-2 code size optimization regression...
2014-09-01 Tilmann SchellerARM] Add Thumb-2 code size optimization regression...
2014-09-01 Jingyue Wu[MachineSink] Use the real post dominator tree
2014-08-30 Juergen RibutzkaRevert r216805 "[MachineCombiner][AArch64] Use the...
2014-08-29 Juergen Ributzka[MachineCombiner][AArch64] Use the correct register...
2014-08-29 Juergen Ributzka[FastISel][AArch64] Use the correct register class...
2014-08-29 Juergen Ributzka[MachineSinking] Clear kill flag of all operands at...
2014-08-29 Robin MorissetFix typos in comments, NFC
2014-08-29 Reid Klecknermusttail: Forward regparms of variadic functions on...
2014-08-29 Reid KlecknerVerifier: Don't reject varargs callee cleanup functions
2014-08-29 Louis GerbargRemove spurious mask operations from AArch64 add->compa...
2014-08-29 Reid KlecknerX86: Fix conflict over ESI between base register and...
2014-08-29 Juergen Ributzka[FastISel][AArch64] Fix an incorrect kill flag due...
2014-08-29 Tilmann Scheller[ARM] Add Thumb-2 code size optimization test for ASR...
2014-08-29 Tilmann Scheller[ARM] Add Thumb-2 code size optimization test for ASR...
2014-08-29 Matt ArsenaultR600/SI: Use mad for fsub + fmul
2014-08-29 Tim NorthoverAArch64: only try to get operand of a known node.
2014-08-29 Jingyue Wu[NVPTX] Make the alignment an explicit argument to...
2014-08-29 Tilmann Scheller[ARM] Make Thumb-2 code size optimization test more...
2014-08-29 Tilmann Scheller[ARM] Add a first test for the Thumb-2 code size optimi...
2014-08-29 Tim NorthoverAArch64: skip select/setcc combine in complex case.
2014-08-29 Robert Khasanov[SKX] Enable lowering of integer CMP operations.
2014-08-29 Job NoormanDo not assume the value passed to memset is an i32.
2014-08-29 Jiangning Liu[AArch64] Fix some failures exposed by value type v4f16...
2014-08-29 Juergen Ributzka[FastISel][AArch64] Don't fold instructions that are...
2014-08-28 Jim GrosbachAArch64: More correctly constrain target vector extend...
2014-08-28 Rafael EspindolaOn MachO, don't put non-private constants in mergeable...
2014-08-28 Sanjay PatelFix a logic bug in x86 vector codegen: sext (zext ...
2014-08-28 David XuGenerate CMN when comparing a short int with minus
2014-08-28 Chandler Carruth[x86] Clean up some tests to use FileCheck and combine...
2014-08-28 Juergen Ributzka[FastISel] Undo phi node updates when falling-back...
2014-08-28 Juergen Ributzka[FastISel]
2014-08-27 Juergen RibutzkaRevert "[FastISel][AArch64] Don't fold instructions...
2014-08-27 Juergen Ributzka[FastISel][AArch64] Don't fold instructions too aggress...
2014-08-27 Juergen Ributzka[FastISel][AArch64] Fix simplify address when the addre...
2014-08-27 Juergen Ributzka[FastISel][AArch64] Use the zero register for stores.
2014-08-27 Oliver StannardTeach the AArch64 backend about v4f16 and v8f16
2014-08-27 Chandler Carruth[x86] Fix a regression introduced with r213897 for...
2014-08-27 Chandler Carruth[SDAG] Re-instate r215611 with a fix to a pesky X86...
2014-08-27 Elena DemikhovskyAVX-512: Added intrinsic for VMOVSS store form with...
2014-08-27 Juergen Ributzka[FastISel][AArch64] Fix address simplification.
2014-08-27 Juergen Ributzka[FastISel][AArch64] Fold Sign-/Zero-Extend into the...
2014-08-26 Yi KongARM: Add patterns for dbg
2014-08-25 Chad Rosier[AArch32] Add patterns for VCVT{A,N,P,M}.
2014-08-23 Hal Finkel[PowerPC] Add support for dcbtst and icbt (prefetch)
2014-08-23 Chad RosierRevert "ARM: improve RTABI 4.2 conformance on Linux"
2014-08-23 Chandler Carruth[x86] Start fixing a really subtle and terrible form...
2014-08-23 Nick LewyckyRevert r215611 because it caused the infinite loop...
2014-08-22 Reid KlecknerARM / x86_64 varargs: Don't save regparms in prologue...
2014-08-22 Tom StellardR600/SI: Use READ2/WRITE2 instructions for 64-bit mem...
2014-08-22 Tom StellardR600/SI: Use a ComplexPattern for DS loads and stores
2014-08-22 Quentin Colombet[ARM] Move the implementation of the target hooks relat...
2014-08-22 Sasa Stankovic[mips] Don't use odd-numbered float registers for doubl...
2014-08-21 Juergen Ributzka[FastISel][AArch64] Add support for variable shift.
2014-08-21 Juergen Ributzka[FastISel][AArch64] Use the correct register class...
2014-08-21 Tom StellardR600/SI: Teach moveToVALU how to handle more S_LOAD_...
2014-08-21 Tom StellardR600/SI: Make sure SCRATCH_WAVE_OFFSET is added as...
2014-08-21 Quentin Colombet[AArch64] Run a peephole pass right after AdvSIMD pass.
2014-08-21 Moritz RothThumb1 load/store optimizer: Improve code to materializ...
2014-08-21 Juergen Ributzka[FastISel][AArch64] Remove redundant test.
2014-08-21 Jonathan RoelofsAdd a thread-model knob for lowering atomics on baremet...
2014-08-21 Benjamin KramerDAGCombiner: Make concat_vector combine safe for EVTs...
2014-08-21 Oliver Stannard[ARM] Enable DP copy, load and store instructions for...
2014-08-21 Robert Khasanov[x86] Added _addcarry_ and _subborrow_ intrinsics
2014-08-21 Robert Khasanov[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64...
2014-08-21 Jiangning LiuRevert r216066, "Optimize ZERO_EXTEND and SIGN_EXTEND...
2014-08-21 Quentin Colombet[PeepholeOptimizer] Take advantage of the isInsertSubre...
2014-08-20 Jonathan RoelofsLower thumbv4t & thumbv5 lo->lo copies through a push...
2014-08-20 Sanjay PatelDon't prevent a vselect of constants from becoming...
2014-08-20 Duncan P. N. Exon... X86: Add missing triples from r216119
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