[ARM] Add Thumb-2 code size optimization test for ASR (immediate).
authorTilmann Scheller <t.scheller@samsung.com>
Fri, 29 Aug 2014 17:02:28 +0000 (17:02 +0000)
committerTilmann Scheller <t.scheller@samsung.com>
Fri, 29 Aug 2014 17:02:28 +0000 (17:02 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216744 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/ARM/thumb2-size-opt.ll

index 4fbafb9745e3ee6086ea717fd0ad829ad9151237..bc7e6ef9e1aa72fb41c923fe7cab4acc3594af56 100644 (file)
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding -t2-reduce-limit2=0 %s | FileCheck %s
+; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding -t2-reduce-limit=0 -t2-reduce-limit2=0 %s | FileCheck %s
 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding %s | FileCheck %s --check-prefix=CHECK-OPT
 
 define i32 @and(i32 %a, i32 %b) nounwind readnone {
@@ -10,3 +10,11 @@ entry:
   ret i32 %and
 }
 
+define i32 @asr-imm(i32 %a) nounwind readnone {
+; CHECK-LABEL: "asr-imm":
+; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
+; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
+entry:
+  %shr = ashr i32 %a, 13
+  ret i32 %shr
+}