Teach the AArch64 backend about v4f16 and v8f16
authorOliver Stannard <oliver.stannard@arm.com>
Wed, 27 Aug 2014 16:16:04 +0000 (16:16 +0000)
committerOliver Stannard <oliver.stannard@arm.com>
Wed, 27 Aug 2014 16:16:04 +0000 (16:16 +0000)
commit5e487f8dc7fa666fd0b2102eb12c899b642bb52e
treeee7bfd0bc6954fafeec0eabc5fbdaadc99e98686
parentb8c95a89e61ee4e8dc8431ca4ffa323c80cded36
Teach the AArch64 backend about v4f16 and v8f16

This teaches the AArch64 backend to deal with the operations required
to deal with the operations on v4f16 and v8f16 which are exposed by
NEON intrinsics, plus the add, sub, mul and div operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216555 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
include/llvm/CodeGen/MachineValueType.h
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
lib/Target/AArch64/AArch64CallingConvention.td
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/AArch64/AArch64InstrFormats.td
lib/Target/AArch64/AArch64InstrInfo.td
lib/Target/AArch64/AArch64RegisterInfo.td
test/CodeGen/AArch64/arm64-aapcs.ll
test/CodeGen/AArch64/fp16-instructions.ll
test/CodeGen/AArch64/fp16-v4-instructions.ll [new file with mode: 0644]
test/CodeGen/AArch64/fp16-v8-instructions.ll [new file with mode: 0644]
test/CodeGen/AArch64/fp16-vector-bitcast.ll [new file with mode: 0644]
test/CodeGen/AArch64/fp16-vector-load-store.ll [new file with mode: 0644]
test/CodeGen/AArch64/fp16-vector-shuffle.ll [new file with mode: 0644]