Do not reserve space for the ColdEdges and NormalEdges vectors.
[oota-llvm.git] / lib / Target /
2013-05-24 Richard Sandiford[SystemZ] Improve AsmParser handling of invalid instruc...
2013-05-24 Richard Sandiford[SystemZ] Improve AsmParser register parsing
2013-05-24 Benjamin KramerRemove the Copied parameter from MemoryObject::readBytes.
2013-05-24 Ahmed BougachaMC: Disassembled CFG reconstruction.
2013-05-24 Ahmed BougachaAdd MCSymbolizer for symbolic/annotated disassembly.
2013-05-23 Ulrich Weigand[PowerPC] Remove symbolLo/symbolHi instruction operand...
2013-05-23 Ulrich Weigand[PowerPC] Clean up generation of ha16() / lo16() markers
2013-05-23 Tim NorthoverARM: implement @llvm.readcyclecounter intrinsic
2013-05-23 Tim NorthoverARM: Add Performance Monitor Extensions feature
2013-05-23 Tom StellardR600: Fix R600ControlFlowFinalizer not considering...
2013-05-23 Benjamin KramerMove passes from namespace llvm into anonymous namespac...
2013-05-23 Benjamin KramerMore symbols that should be static.
2013-05-23 Benjamin KramerHexagon: Make helper functions static.
2013-05-23 Benjamin KramerR600: Hide symbols of implementation details.
2013-05-23 Aaron BallmanSetting the default value (fixes CRT assertions about...
2013-05-23 Rafael EspindolaFix 32 bit build in c++11 mode.
2013-05-23 Rafael EspindolaFix a leak on the r600 backend.
2013-05-23 Rafael Espindolaclang-format this file.
2013-05-22 Chad RosierSimplify logic now that r182490 is in place. No functi...
2013-05-22 Bill SchmidtChange some PowerPC PatLeaf definitions to ImmLeaf...
2013-05-22 Nadav RotemX86: Fix a bug in EltsFromConsecutiveLoads. We can...
2013-05-22 Benjamin KramerX86: When expanding PCMPGTQ to PCMPGTD we always want...
2013-05-22 Rafael EspindolaFix use after free (pr16103).
2013-05-22 Rafael EspindolaCheck that a function starts with llvm. before using...
2013-05-22 Richard Sandiford[SystemZ] Rename PSW to CC
2013-05-22 Richard Sandiford[SystemZ] Fix thinko in long branch pass
2013-05-22 David MajnemerX86: Remove test instructions proceeding shift by immed...
2013-05-22 NAKAMURA TakumiR600ISelLowering.cpp: Avoid "using namespace Intrinsic...
2013-05-22 NAKAMURA TakumiR600: Whitespace and untabify.
2013-05-22 Owen AndersonCreate an FPOW SDNode opcode def in the target independ...
2013-05-22 Rafael EspindolaAttempt to fix the mingw32 bot.
2013-05-22 Rafael Espindolas/u_int32_t/uint32_t/
2013-05-22 Rafael EspindolaFix warning in non-assert build.
2013-05-21 Reed KotlerMips16 does not use register scavenger from TargetRegis...
2013-05-21 Akira Hatanaka[mips] Rename option to make it compatible with gcc.
2013-05-21 Akira Hatanaka[mips] Add instruction selection patterns for blez...
2013-05-21 Justin Holewinski[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic
2013-05-21 Jyotsna VermaHexagon: SelectionDAG should not use MVT::Other to...
2013-05-21 Hal FinkelFix PPC branch selection for counter-based branches
2013-05-21 Elena Demikhovskyremoved commented lines
2013-05-21 Elena DemikhovskyRemoved SSEPacked domain from all forms (AVX, SSE,...
2013-05-21 Benjamin KramerX86: When emulating unsigned PCMPGTQ with PCMPGTD,...
2013-05-21 Richard SandifordFix indentation
2013-05-21 Reed KotlerAdd some additional functions to the list of helper...
2013-05-20 Hal FinkelRename LoopSimplify.h to LoopUtils.h
2013-05-20 Akira Hatanaka[mips] Add (setne $lhs, 0) instruction selection pattern.
2013-05-20 Akira Hatanaka[mips] Trap on integer division by zero.
2013-05-20 Hal FinkelRemove copied preheader insertion logic from PPCCTRLoops
2013-05-20 Justin Holewinski[NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter...
2013-05-20 Justin Holewinski[NVPTX] Add programmatic interface to NVVMReflect pass
2013-05-20 Hal FinkelRename PPC MTCTRse to MTCTRloop
2013-05-20 Hal FinkelAdd a PPCCTRLoops verification pass
2013-05-20 Benjamin KramerR600: Fix bug detected by GCC warning.
2013-05-20 Tom StellardR600/SI: Use a multiclass for MUBUF_Load_Helper
2013-05-20 Tom StellardR600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
2013-05-20 Tom StellardR600/SI: Add pattern for rotr
2013-05-20 Tom StellardR600: Swap the legality of rotl and rotr
2013-05-20 Tom StellardR600/SI: Add patterns for 64-bit shift operations
2013-05-20 Tom StellardR600/SI: Use the same names for VOP3 operands and encod...
2013-05-20 Tom StellardR600/SI: Make fitsRegClass() operands const
2013-05-20 Mihai PopaVSTn instructions have a number of encoding constraints...
2013-05-20 Mihai PopaQ registers are encoded in fields of the same length...
2013-05-20 Richard Sandiford[SystemZ] Add long branch pass
2013-05-20 Justin Holewinski[NVPTX] Add GenericToNVVM IR converter to better handle...
2013-05-20 Justin Holewinski[NVPTX] Fix i1 kernel parameters and global variables...
2013-05-20 Stepan DyatkovskiyPR15868 fix.
2013-05-20 Jakob Stoklund OlesenAlso expand 64-bit bitcasts.
2013-05-20 Jakob Stoklund OlesenImplement spill and fill of I64Regs.
2013-05-20 Jakob Stoklund OlesenMark i64 SETCC as expand so it is turned into a SELECT_CC.
2013-05-19 Benjamin KramerReplace some bit operations with simpler ones. No funct...
2013-05-19 Jakob Stoklund OlesenDon't use %g0 to materialize 0 directly.
2013-05-19 Jakob Stoklund OlesenSelect i64 values with %icc conditions.
2013-05-19 Jakob Stoklund OlesenAdd floating point selects on %xcc predicates.
2013-05-19 Jakob Stoklund OlesenImplement SPselectfcc for i64 operands.
2013-05-19 Venkatraman Govind... [Sparc] Rearrange integer registers' allocation order...
2013-05-19 Jakob Stoklund OlesenHandle i64 FrameIndex nodes in SPARC v9 mode.
2013-05-18 Hal FinkelCheck InlineAsm clobbers in PPCCTRLoops
2013-05-18 Tim NorthoverAArch64: add CMake dependency to fix very parallel...
2013-05-18 David MajnemerX86: Bad peephole interaction between adc, MOV32r0
2013-05-18 Matt ArsenaultAdd LLVMContext argument to getSetCCResultType
2013-05-17 JF BastienSupport unaligned load/store on more ARM targets
2013-05-17 Rafael EspindolaFix the build in c++11 mode.
2013-05-17 Vincent LejeuneR600: Lower int_load_input to copyFromReg instead of...
2013-05-17 Vincent LejeuneR600: Use bottom up scheduling algorithm
2013-05-17 Vincent LejeuneR600: Use depth first scheduling algorithm
2013-05-17 Vincent LejeuneR600: Replace big texture opcode switch in scheduler...
2013-05-17 Vincent LejeuneR600: Relax some vector constraints on Dot4.
2013-05-17 Vincent LejeuneR600: Improve texture handling
2013-05-17 Vincent LejeuneR600: Rename 128 bit registers.
2013-05-17 Vincent LejeuneR600: Some factorization
2013-05-17 Vincent LejeuneR600: Factorize Fetch size limit inside AMDGPUSubTarget
2013-05-17 Vincent LejeuneR600: prettier dump of clamp
2013-05-17 Tom StellardR600: Fix encoding for R600 family GPUs
2013-05-17 Tom StellardR600: Pass MCSubtargetInfo reference to R600CodeEmitter
2013-05-17 Venkatraman Govind... [Sparc] Implements hasReservedCallFrame and hasFP.
2013-05-17 Benjamin KramerX86: Make shuffle -> shift conversion more aggressive...
2013-05-17 Ulrich Weigand[PowerPC] Fix hi/lo encoding in old-style code emitter
2013-05-17 Ulrich Weigand[PowerPC] Merge/rename PPC fixup types
2013-05-17 Ulrich Weigand[PowerPC] Fix processing of ha16/lo16 fixups
2013-05-17 Benjamin KramerDon't cast away constness.
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