R600: Factorize Fetch size limit inside AMDGPUSubTarget

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182122 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp
index a7e1d7b6d54c04a5027305c455862d8c81398773..6bfe17bbae9728a46a43ce68c895624ade32c417 100644 (file)
--- a/lib/Target/R600/AMDGPUSubtarget.cpp
+++ b/lib/Target/R600/AMDGPUSubtarget.cpp
@@ -37,6 +37,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
   ParseSubtargetFeatures(GPU, FS);
   DevName = GPU;
   Device = AMDGPUDeviceInfo::getDeviceFromName(DevName, this, Is64bit);
+  TexVTXClauseSize = (Device->getGeneration() >= AMDGPUDeviceInfo::HD4XXX)?16:8;
 }
 
 AMDGPUSubtarget::~AMDGPUSubtarget() {
@@ -57,6 +58,10 @@ bool
 AMDGPUSubtarget::hasVertexCache() const {
   return HasVertexCache;
 }
+short
+AMDGPUSubtarget::getTexVTXClauseSize() const {
+  return TexVTXClauseSize;
+}
 bool
 AMDGPUSubtarget::isTargetELF() const {
   return false;

diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h
index b6501a456283ac38f8e17721d0b1095b2b08db46..b9531bdcf57e468d1100d6f50e5fabcdf4b5d4bf 100644 (file)
--- a/lib/Target/R600/AMDGPUSubtarget.h
+++ b/lib/Target/R600/AMDGPUSubtarget.h
@@ -37,6 +37,7 @@ private:
   bool DumpCode;
   bool R600ALUInst;
   bool HasVertexCache;
+  short TexVTXClauseSize;
 
   InstrItineraryData InstrItins;
 
@@ -50,6 +51,7 @@ public:
   bool isOverride(AMDGPUDeviceInfo::Caps) const;
   bool is64bit() const;
   bool hasVertexCache() const;
+  short getTexVTXClauseSize() const;
 
   // Helper functions to simplify if statements
   bool isTargetELF() const;

diff --git a/lib/Target/R600/R600ControlFlowFinalizer.cpp b/lib/Target/R600/R600ControlFlowFinalizer.cpp
index cdda3dab8dab779a9fb7f05fd77a9b38cad09643..f1e07326e27dccd42aca622d5e9c1906948934ba 100644 (file)
--- a/lib/Target/R600/R600ControlFlowFinalizer.cpp
+++ b/lib/Target/R600/R600ControlFlowFinalizer.cpp
@@ -148,7 +148,7 @@ private:
     for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
       if (IsTrivialInst(I))
         continue;
-      if (AluInstCount > MaxFetchInst)
+      if (AluInstCount >= MaxFetchInst)
         break;
       if ((IsTex && !TII->usesTextureCache(I)) ||
           (!IsTex && !TII->usesVertexCache(I)))
@@ -316,10 +316,7 @@ public:
     TRI(TII->getRegisterInfo()),
     ST(tm.getSubtarget<AMDGPUSubtarget>()) {
       const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
-      if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD4XXX)
-        MaxFetchInst = 8;
-      else
-        MaxFetchInst = 16;
+      MaxFetchInst = ST.getTexVTXClauseSize();
   }
 
   virtual bool runOnMachineFunction(MachineFunction &MF) {

diff --git a/lib/Target/R600/R600MachineScheduler.cpp b/lib/Target/R600/R600MachineScheduler.cpp
index a777142a9e70401e1ba7ba50056d8c744d01662a..c6709a8dc380931c7f958d509fa8582d2d5f4e7d 100644 (file)
--- a/lib/Target/R600/R600MachineScheduler.cpp
+++ b/lib/Target/R600/R600MachineScheduler.cpp
@@ -41,11 +41,7 @@ void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
 
 
   const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
-  if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD5XXX) {
-    InstKindLimit[IDFetch] = 7; // 8 minus 1 for security
-  } else {
-    InstKindLimit[IDFetch] = 15; // 16 minus 1 for security
-  }
+  InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
 }
 
 void R600SchedStrategy::MoveUnits(ReadyQueue *QSrc, ReadyQueue *QDst)
@@ -67,9 +63,9 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
 
   // check if we might want to switch current clause type
   bool AllowSwitchToAlu = (CurInstKind == IDOther) ||
-      (CurEmitted > InstKindLimit[CurInstKind]) ||
+      (CurEmitted >= InstKindLimit[CurInstKind]) ||
       (Available[CurInstKind]->empty());
-  bool AllowSwitchFromAlu = (CurEmitted > InstKindLimit[CurInstKind]) &&
+  bool AllowSwitchFromAlu = (CurEmitted >= InstKindLimit[CurInstKind]) &&
       (!Available[IDFetch]->empty() || !Available[IDOther]->empty());
 
   if ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
@@ -77,7 +73,7 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
     // try to pick ALU
     SU = pickAlu();
     if (SU) {
-      if (CurEmitted >  InstKindLimit[IDAlu])
+      if (CurEmitted >= InstKindLimit[IDAlu])
         CurEmitted = 0;
       NextInstKind = IDAlu;
     }