[mips] Add instruction selection patterns for blez and bgez.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 391b23e4016d05bdbc85fa2f3a00ce8f0091c3f0..df717fe2d2e49587ff9e64646ce79eb8f6ebb8d9 100644 (file)
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -294,6 +294,11 @@ def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
                   ZERO_64>;
 
+def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
+              (BLEZ64 i64:$lhs, bb:$dst)>;
+def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
+              (BGEZ64 i64:$lhs, bb:$dst)>;
+
 // setcc patterns
 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index f37a93e8877ae5412e86fabfb7a3b271deb287f4..3febc81f00a1054b7bb0b802594dfaaddef9402c 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1277,6 +1277,11 @@ def : MipsPat<(brcond RC:$cond, bb:$dst),
 
 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
 
+def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
+              (BLEZ i32:$lhs, bb:$dst)>;
+def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
+              (BGEZ i32:$lhs, bb:$dst)>;
+
 // setcc patterns
 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
                      Instruction SLTuOp, Register ZEROReg> {

diff --git a/test/CodeGen/Mips/blez_bgez.ll b/test/CodeGen/Mips/blez_bgez.ll
new file mode 100644 (file)
index 0000000..52765af
--- /dev/null
+++ b/test/CodeGen/Mips/blez_bgez.ll
@@ -0,0 +1,36 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
+
+; CHECK: test_blez:
+; CHECK: blez ${{[0-9]+}}, $BB
+
+define void @test_blez(i32 %a) {
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @foo1()
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+declare void @foo1()
+
+; CHECK: test_bgez:
+; CHECK: bgez ${{[0-9]+}}, $BB
+
+define void @test_bgez(i32 %a) {
+entry:
+  %cmp = icmp slt i32 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @foo1()
+  br label %if.end
+
+if.end:
+  ret void
+}

diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll
index 2deb037c9c3906077f8502697f9abe50e6f28bcb..d076f74e56dfff44ad0c92de204f50ca925e6fe2 100644 (file)
--- a/test/CodeGen/Mips/brdelayslot.ll
+++ b/test/CodeGen/Mips/brdelayslot.ll
@@ -131,7 +131,7 @@ declare void @foo11()
 ; filled.
 ;
 ; SUCCBB:      succbbs_loop1:
-; SUCCBB:      bne ${{[0-9]+}}, $zero, $BB
+; SUCCBB:      blez $5, $BB
 ; SUCCBB-NEXT: addiu
 ; SUCCBB:      bne ${{[0-9]+}}, $zero, $BB
 ; SUCCBB-NEXT: addiu