[mips] Add (setne $lhs, 0) instruction selection pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index f7d21ce4d35ab2886180ad487496473d04f4958a..f37a93e8877ae5412e86fabfb7a3b271deb287f4 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1282,6 +1282,8 @@ multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
                      Instruction SLTuOp, Register ZEROReg> {
   def : MipsPat<(seteq RC:$lhs, 0),
                 (SLTiuOp RC:$lhs, 1)>;
+  def : MipsPat<(setne RC:$lhs, 0),
+                (SLTuOp ZEROReg, RC:$lhs)>;
   def : MipsPat<(seteq RC:$lhs, RC:$rhs),
                 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
   def : MipsPat<(setne RC:$lhs, RC:$rhs),

diff --git a/test/CodeGen/Mips/setcc-se.ll b/test/CodeGen/Mips/setcc-se.ll
index 6679536164b50b4bd318a496987ce204b89471dc..03af91386082242cc697b7fb2277312b970a498c 100644 (file)
--- a/test/CodeGen/Mips/setcc-se.ll
+++ b/test/CodeGen/Mips/setcc-se.ll
@@ -9,3 +9,13 @@ entry:
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
+
+; CHECK: setne0:
+; CHECK: sltu ${{[0-9]+}}, $zero, $4
+
+define i32 @setne0(i32 %a) {
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}