"mov$cond %xcc, $i, $rd",
[(set i32:$rd,
(SPselectxcc simm11:$i, i32:$f, imm:$cond))]>;
+def FMOVS_XCC : Pseudo<(outs FPRegs:$rd),
+ (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
+ "fmovs$cond %xcc, $rs2, $rd",
+ [(set f32:$rd,
+ (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
+def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd),
+ (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
+ "fmovd$cond %xcc, $rs2, $rd",
+ [(set f64:$rd,
+ (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
} // Uses, Constraints
def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
%rv = select i1 %tobool, i64 %a, i64 %b
ret i64 %rv
}
+
+; CHECK: selectf32_xcc
+; CHECK: subcc %i0, %i1
+; CHECK: fmovsg %xcc, %f5, %f7
+; CHECK: fmovs %f7, %f1
+define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
+entry:
+ %tobool = icmp sgt i64 %x, %y
+ %rv = select i1 %tobool, float %a, float %b
+ ret float %rv
+}
+
+; CHECK: selectf64_xcc
+; CHECK: subcc %i0, %i1
+; CHECK: fmovdg %xcc, %f4, %f6
+; CHECK: fmovd %f6, %f0
+define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
+entry:
+ %tobool = icmp sgt i64 %x, %y
+ %rv = select i1 %tobool, double %a, double %b
+ ret double %rv
+}