R600/SI: Add verifier check for immediates in register operands.
[oota-llvm.git] / lib / Target / R600 / SIInstructions.td
2014-07-02 Tom StellardR600/SI: Add verifier check for immediates in register...
2014-06-24 Tom StellardR600/SI: Use a ComplexPattern for MUBUF stores
2014-06-24 Tom StellardR600: Promote i64 stores to v2i32
2014-06-24 Matt ArsenaultR600: Fix inconsistency in rsq instructions.
2014-06-24 Matt ArsenaultR600/SI: Move pattern to instruction definition
2014-06-23 Matt ArsenaultR600/SI: Fix div_scale intrinsic.
2014-06-20 Tom StellardR600/SI: Add patterns for ctpop inside a branch
2014-06-20 Tom StellardR600/SI: Add a pattern for f32 ftrunc
2014-06-20 Tom StellardR600/SI: Add a VALU pattern for i64 xor
2014-06-19 Matt ArsenaultR600/SI: Add intrinsics for various math instructions.
2014-06-18 Marek OlsakR600/SI: add gather4 and getlod intrinsics (v3)
2014-06-18 Matt ArsenaultR600/SI: Add intrinsics for brev instructions
2014-06-18 Matt ArsenaultR600/SI: Comparisons set vcc.
2014-06-17 Matt ArsenaultR600/SI: Match cttz_zero_undef
2014-06-17 Matt ArsenaultR600/SI: Match ctlz_zero_undef
2014-06-17 Tom StellardR600: Use LDS and vectors for private memory
2014-06-17 Tom StellardR600/SI: Add a pattern for llvm.AMDGPU.barrier.global
2014-06-13 Tom StellardR600: Remove AMDIL instruction and register definitions
2014-06-12 Matt ArsenaultR600: Mostly remove remaining AMDIL intrinsics.
2014-06-12 Matt ArsenaultR600/SI: Use a register set to -1 for data0 on ds_inc...
2014-06-11 Matt ArsenaultR600/SI: Fix bitcast between v2i32 and f64
2014-06-11 Matt ArsenaultR600/SI: Update place using old subtarget predicate
2014-06-11 Matt ArsenaultR600/SI: Add common 64-bit LDS atomics
2014-06-11 Matt ArsenaultR600/SI: Add instruction definitions for 64-bit LDS...
2014-06-11 Matt ArsenaultR600/SI: Add 32-bit LDS atomic cmpxchg
2014-06-11 Matt ArsenaultR600/SI: Use LDS atomic inc / dec
2014-06-11 Matt ArsenaultR600/SI: Add other LDS atomic operations
2014-06-11 Matt ArsenaultR600/SI: Add instruction definitions for more LDS ops
2014-06-11 Matt ArsenaultR600/SI: Fix backwards names for local atomic instructions.
2014-06-11 Matt ArsenaultR600/SI: Refactor local atomics.
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 Matt ArsenaultR600/SI: Fix selection failure on scalar_to_vector
2014-06-10 Tom StellardR600/SI: Fix a crash when spilling SGPRs
2014-06-10 Matt ArsenaultR600/SI: Implement i64 ctpop
2014-06-10 Matt ArsenaultR600/SI: Use bcnt instruction for ctpop
2014-06-10 Matt ArsenaultR600: Handle fcopysign
2014-06-10 Matt ArsenaultR600/SI: Handle sign_extend and zero_extend to i64...
2014-06-09 Matt ArsenaultR600/SI: Rename VOP3 helper class to be more general
2014-06-09 Matt ArsenaultR600/SI: Keep 64-bit not on SALU
2014-06-05 Matt ArsenaultR600/SI: Match rsq instructions
2014-05-31 Matt ArsenaultR600/SI: Remove redundant patterns
2014-05-31 Matt ArsenaultR600/SI: Fix [s|u]int_to_fp for i1
2014-05-29 Matt ArsenaultR600/SI: Fix pattern variable names.
2014-05-22 Matt ArsenaultR600: Add intrinsics for mad24
2014-05-22 Matt ArsenaultR600/SI: Move instruction pattern to instruction definition
2014-05-22 Matt ArsenaultR600/SI: Match fp_to_uint / uint_to_fp for f64
2014-05-16 Tom StellardR600/SI: Refactor the VOP3_32 tablegen class
2014-05-16 Tom StellardR600/SI: Add a PredicateControl class for managing...
2014-05-16 Tom StellardR600/SI: Move tablegen patterns away from instruction...
2014-05-16 Tom StellardR600/SI: Remove unused instruction
2014-05-16 Tom StellardR600/SI: Promote f32 SELECT to i32
2014-05-16 Tom StellardR600/SI: Remove duplicate pattern
2014-05-15 Tom StellardR600/SI: Stop using VSrc_* as the default register...
2014-05-15 Tom StellardR600/SI: Use VALU instructions for i1 ops
2014-05-10 Vincent LejeuneR600/SI: Prettier display of input modifiers
2014-05-10 Vincent LejeuneR600/SI: Use pseudo instruction for fabs/clamp/fneg
2014-05-09 Tom StellardR600/SI: Fix SMRD pattern for offsets > 32 bits
2014-05-02 Tom StellardR600/SI: Only create one instruction when spilling...
2014-04-30 Tom StellardR600/SI: Use VALU instructions for copying i1 values
2014-04-29 Tom StellardR600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
2014-04-29 Tom StellardR600/SI: Only select SALU instructions in the entry...
2014-04-22 Tom StellardR600/SI: Reorganize SIInstructions.td
2014-04-22 Matt ArsenaultR600: Make sign_extend_inreg legal.
2014-04-18 Matt ArsenaultR600/SI: Match sign_extend_inreg to s_sext_i32_i8 and...
2014-04-17 Tom StellardR600/SI: Stop using i128 as the resource descriptor...
2014-04-17 Matt ArsenaultR600/SI: f64 frint is legal on CI
2014-04-11 Matt ArsenaultR600/SI: Refactor SOPC classes slightly.
2014-04-09 Matt ArsenaultR600/SI: Match not instruction.
2014-04-07 Tom StellardR600: Match 24-bit arithmetic patterns in a Target...
2014-04-03 Tom StellardR600/SI: Lower 64-bit immediates using REG_SEQUENCE
2014-03-31 Matt ArsenaultR600/SI: Remove leftover pattern splitting 64-bit ors.
2014-03-31 Matt ArsenaultR600: Add target nodes for BFM and BFI
2014-03-31 Tom StellardR600/SI: Lower i64 SELECT by bitcasting to a vector...
2014-03-24 Matt ArsenaultR600/SI: Fix 64-bit bit ops that require the VALU.
2014-03-24 Tom StellardR600/SI: Promote fp64 SELECT to i64
2014-03-21 Matt ArsenaultR600/SI: Move instruction patterns to scalar versions.
2014-03-19 Matt ArsenaultR600/SI: Add unused LDS 2 form instructions.
2014-03-19 Matt ArsenaultR600/SI: Add support for 64-bit LDS writes
2014-03-19 Matt ArsenaultR600/SI: Add support for 64-bit LDS loads.
2014-03-19 Matt ArsenaultR600/SI: Match i16 immediate offset of LDS instructions.
2014-03-19 Matt ArsenaultR600/SI: Merge offset0 and offset1 fields for single...
2014-03-17 Matt ArsenaultR600: Match sign_extend_inreg to BFE instructions
2014-03-17 Tom StellardR600/SI: Use correct dest register class for V_READFIRS...
2014-03-07 Tom StellardR600/SI: Using SGPRs is illegal for instructions that...
2014-02-27 Michel DanzerR600/SI: Optimize SI_KILL for constant operands
2014-02-24 Matt ArsenaultR600/SI - Add new CI arithmetic instructions.
2014-02-13 Tom StellardR600/SI: Expand all v8[if]32 operations
2014-02-13 Tom StellardR600/SI: Add a pattern for i32 anyext
2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Reg+Imm offsets
2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Imm offsets
2014-02-06 Tom StellardR600/SI: Add a MUBUF load pattern for Reg+Imm offsets
2014-02-06 Tom StellardR600/SI: Use immediates offsets for SMRD instructions...
2014-02-05 Michel DanzerR600/SI: Add pattern for zero-extending i1 to i32
2014-02-04 Michel DanzerR600/SI: Fix fneg for 0.0
2014-02-02 Matt ArsenaultR600/SI: Fix insertelement with dynamic indices.
2014-01-28 Michel DanzerR600/SI: Add pattern for truncating i32 to i1
2014-01-27 Michel DanzerR600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
2014-01-27 Michel DanzerR600/SI: Add intrinsic for S_SENDMSG instruction
2013-12-19 Matt ArsenaultR600/SI: Make private pointers be 32-bit.
2013-12-16 Matt ArsenaultFix typo in instruction name.
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