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Taints the non-acquire RMW's store address with the load part
[oota-llvm.git]
/
lib
/
Target
/
R600
/ R600InstrInfo.cpp
2015-06-13
Tom Stellard
R600 -> AMDGPU rename
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2015-06-11
Ahmed Bougacha
[CodeGen] ArrayRef'ize cond/pred in various TII APIs...
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2015-03-11
Eric Christopher
Remove the need to cache the subtarget in the R600...
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2015-03-02
Jan Vesely
R600: Use c++11 style for loop
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2014-10-09
Eric Christopher
Remove unused argument to CreateTargetScheduleState...
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2014-10-03
Benjamin Kramer
Eliminate some deep std::vector copies. NFC.
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2014-08-05
Eric Christopher
Have MachineFunction cache a pointer to the subtarget...
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2014-08-04
Eric Christopher
Remove the TargetMachine forwards for TargetSubtargetIn...
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2014-07-20
Matt Arsenault
R600: Remove unused function
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2014-07-13
Matt Arsenault
R600: Make ShaderType private
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2014-06-17
Tom Stellard
R600: Use LDS and vectors for private memory
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2014-06-13
Tom Stellard
R600: Remove AMDIL instruction and register definitions
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2014-06-13
Tom Stellard
R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine...
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2014-06-13
Tom Stellard
R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
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2014-04-25
Craig Topper
[C++] Use 'nullptr'. Target edition.
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2014-04-22
Chandler Carruth
[cleanup] Lift using directives, DEBUG_TYPE definitions...
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2014-03-02
Benjamin Kramer
[C++11] Replace llvm::next and llvm::prior with std...
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2014-01-23
Tom Stellard
R600: Remove successive JUMP in AnalyzeBranch when...
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2013-11-22
Tom Stellard
R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()
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2013-11-19
Juergen Ributzka
[weak vtables] Remove a bunch of weak vtables
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2013-11-18
Alexey Samsonov
Revert r194865 and r194874.
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2013-11-16
Vincent Lejeune
R600: Make dot_4 instructions predicable
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2013-11-15
Juergen Ributzka
[weak vtables] Remove a bunch of weak vtables
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2013-11-15
Tom Stellard
R600: Fix scheduling of instructions that use the LDS...
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2013-11-13
Tom Stellard
R600/SI: Add support for private address space load...
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2013-10-22
Tom Stellard
R600: Simplify handling of private address space
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2013-10-22
Tom Stellard
R600: Remove unused InstrInfo::getMovImmInstr() function
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2013-10-01
Vincent Lejeune
R600: add a pass that merges clauses.
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2013-10-01
Vincent Lejeune
R600: Enable -verify-machineinstrs in some tests.
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2013-09-30
Arnold Schwaighofer
IfConverter: Use TargetSchedule for instruction latencies
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2013-09-12
Tom Stellard
R600: Don't use trans slot for instructions that read...
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2013-09-04
Vincent Lejeune
R600: Use shared op optimization when checking cycle...
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2013-09-04
Vincent Lejeune
R600: Non vector only instruction can be scheduled...
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2013-09-04
Vincent Lejeune
R600: Use SchedModel enum for is{Trans,Vector}Only...
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2013-08-26
Tom Stellard
R600: Add support for i8 and i16 local memory stores
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2013-08-16
Tom Stellard
R600: Add IsExport bit to TableGen instruction definitions
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2013-08-01
Tom Stellard
R600: Add 64-bit float load/store support
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2013-07-31
Tom Stellard
Revert "R600: Non vector only instruction can be schedu...
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2013-07-31
Tom Stellard
Revert "R600: Use SchedModel enum for is{Trans,Vector...
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2013-07-31
Vincent Lejeune
R600: Avoid more than 4 literals in the same instructio...
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2013-07-31
Vincent Lejeune
R600: Non vector only instruction can be scheduled...
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2013-07-31
Vincent Lejeune
R600: Use SchedModel enum for is{Trans,Vector}Only...
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2013-07-23
Tom Stellard
R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISe...
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2013-07-14
Craig Topper
Use SmallVectorImpl& instead of SmallVector to avoid...
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2013-07-10
Aaron Ballman
Replacing an empty switch with its moral equivalent...
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2013-07-09
Vincent Lejeune
R600: Do not predicated basic block with multiple alu...
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2013-06-30
Vincent Lejeune
R600: Fix an unitialized variable in R600InstrInfo.cpp
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2013-06-29
Benjamin Kramer
R600: Unbreak GCC build.
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2013-06-29
Vincent Lejeune
R600: Support schedule and packetization of trans-only...
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2013-06-29
Vincent Lejeune
R600: Bank Swizzle now display SCL equivalent
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2013-06-28
Tom Stellard
R600: Add local memory support via LDS
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2013-06-28
Tom Stellard
R600: Add support for GROUP_BARRIER instruction
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2013-06-28
Tom Stellard
R600: Add ALUInst bit to tablegen definitions v2
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2013-06-25
Tom Stellard
R600: Use new getNamedOperandIdx function generated...
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2013-06-17
Vincent Lejeune
R600: PV stores Reg id, not index
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2013-06-07
Tom Stellard
R600: Rework subtarget info and remove AMDILDevice...
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-06-05
Tom Stellard
R600: Make sure to schedule AR register uses and defs...
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2013-06-04
Vincent Lejeune
R600: Const/Neg/Abs can be folded to dot4
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2013-05-23
Benjamin Kramer
Move passes from namespace llvm into anonymous namespac...
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2013-05-17
Vincent Lejeune
R600: Relax some vector constraints on Dot4.
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2013-05-17
Vincent Lejeune
R600: Some factorization
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2013-05-06
Tom Stellard
R600: Remove dead code from the CodeEmitter v2
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2013-04-30
Vincent Lejeune
R600: Always use texture cache for compute shaders
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2013-04-30
Vincent Lejeune
R600: Packetize instructions
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2013-04-30
Vincent Lejeune
R600: Rework Scheduling to handle difference between...
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2013-04-30
Vincent Lejeune
R600: Add a Bank Swizzle operand
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2013-04-30
Vincent Lejeune
R600: Add FetchInst bit to instruction defs to denote...
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2013-04-03
Vincent Lejeune
R600: Factorize maximum alu per clause in a single...
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2013-03-14
Vincent Lejeune
R600: Factorize code handling Const Read Port limitation
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2013-03-11
Vincent Lejeune
R600: Fix JUMP handling so that MachineInstr verificati...
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2013-03-05
Vincent Lejeune
R600: Do not predicate vector op
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2013-02-06
Tom Stellard
R600: Support for indirect addressing v4
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2013-02-05
Tom Stellard
R600: improve inputs/interpolation handling
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2013-01-23
Tom Stellard
R600: rework handling of the constants
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2013-01-02
Chandler Carruth
Resort the #include lines in include/... and lib/....
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2012-12-20
NAKAMURA Takumi
Target/R600: Update MIB according to r170588.
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2012-12-13
Tom Stellard
Fix warnings with -DNDEBUG
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2012-12-11
Tom Stellard
Add R600 backend
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