R600: Add 64-bit float load/store support
authorTom Stellard <thomas.stellard@amd.com>
Thu, 1 Aug 2013 15:23:42 +0000 (15:23 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Thu, 1 Aug 2013 15:23:42 +0000 (15:23 +0000)
commit692ee102ebef535d311c35d53457028083e5c5be
tree5966632bb87e4120a27dadfce4187535429a4275
parent98b357e1cd0d41108e6011725dad6a6dbf208a38
R600: Add 64-bit float load/store support

* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
  - Mark vec2 operations as expand.  The addition of a vec2 register
    class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
23 files changed:
lib/Target/R600/AMDGPUCallingConv.td
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
lib/Target/R600/AMDGPUISelLowering.cpp
lib/Target/R600/R600ControlFlowFinalizer.cpp
lib/Target/R600/R600ISelLowering.cpp
lib/Target/R600/R600InstrInfo.cpp
lib/Target/R600/R600Instructions.td
lib/Target/R600/R600RegisterInfo.td
test/CodeGen/R600/64bit-kernel-args.ll
test/CodeGen/R600/build_vector.ll [new file with mode: 0644]
test/CodeGen/R600/fadd.ll
test/CodeGen/R600/fdiv.ll
test/CodeGen/R600/fmul.ll
test/CodeGen/R600/fp_to_sint.ll
test/CodeGen/R600/fp_to_uint.ll
test/CodeGen/R600/fsub.ll
test/CodeGen/R600/load.ll
test/CodeGen/R600/load.vec.ll
test/CodeGen/R600/setcc.ll
test/CodeGen/R600/sint_to_fp.ll
test/CodeGen/R600/store.ll
test/CodeGen/R600/sub.ll
test/CodeGen/R600/uint_to_fp.ll