Don't cache the instruction and register info from the TargetMachine, because
authorBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 20:28:55 +0000 (20:28 +0000)
committerBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 20:28:55 +0000 (20:28 +0000)
commitb5632b5b456db647b42239cbd4d8b58c82290c4e
tree4662bb108ed60bf4d5a2692aa7bc82d19342620e
parentce961477be78b3945e6ec4b7e22066f237a89846
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
21 files changed:
lib/Target/R600/AMDGPUIndirectAddressing.cpp
lib/Target/R600/AMDGPUInstrInfo.cpp
lib/Target/R600/AMDGPURegisterInfo.cpp
lib/Target/R600/AMDGPURegisterInfo.h
lib/Target/R600/AMDILCFGStructurizer.cpp
lib/Target/R600/R600ControlFlowFinalizer.cpp
lib/Target/R600/R600EmitClauseMarkers.cpp
lib/Target/R600/R600ExpandSpecialInstrs.cpp
lib/Target/R600/R600ISelLowering.cpp
lib/Target/R600/R600ISelLowering.h
lib/Target/R600/R600InstrInfo.cpp
lib/Target/R600/R600OptimizeVectorRegisters.cpp
lib/Target/R600/R600RegisterInfo.cpp
lib/Target/R600/R600RegisterInfo.h
lib/Target/R600/SIISelLowering.cpp
lib/Target/R600/SIISelLowering.h
lib/Target/R600/SIInsertWaits.cpp
lib/Target/R600/SIInstrInfo.cpp
lib/Target/R600/SILowerControlFlow.cpp
lib/Target/R600/SIRegisterInfo.cpp
lib/Target/R600/SIRegisterInfo.h