R600: Non vector only instruction can be scheduled on trans unit
authorVincent Lejeune <vljn@ovi.com>
Wed, 4 Sep 2013 19:53:46 +0000 (19:53 +0000)
committerVincent Lejeune <vljn@ovi.com>
Wed, 4 Sep 2013 19:53:46 +0000 (19:53 +0000)
commitbb25a01d232257b134f1f6a5810116cbb04b95b1
treec8372c60ee26e9325086cf932b4a20633f3f9487
parentb3df27d4402d8c8fc81d5acec812035360806cdc
R600: Non vector only instruction can be scheduled on trans unit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
28 files changed:
lib/Target/R600/R600InstrInfo.cpp
lib/Target/R600/R600MachineScheduler.cpp
lib/Target/R600/R600MachineScheduler.h
lib/Target/R600/R600Packetizer.cpp
test/CodeGen/R600/and.ll
test/CodeGen/R600/fadd.ll
test/CodeGen/R600/fcmp-cnd.ll
test/CodeGen/R600/fcmp.ll
test/CodeGen/R600/fdiv.ll
test/CodeGen/R600/fmul.ll
test/CodeGen/R600/fneg.ll
test/CodeGen/R600/fp_to_sint.ll
test/CodeGen/R600/fp_to_uint.ll
test/CodeGen/R600/fsub.ll
test/CodeGen/R600/icmp-select-sete-reverse-args.ll
test/CodeGen/R600/literals.ll
test/CodeGen/R600/llvm.AMDGPU.trunc.ll
test/CodeGen/R600/rotr.ll
test/CodeGen/R600/selectcc-cnd.ll
test/CodeGen/R600/selectcc-cnde-int.ll
test/CodeGen/R600/set-dx10.ll
test/CodeGen/R600/store.ll
test/CodeGen/R600/sub.ll
test/CodeGen/R600/unsupported-cc.ll
test/CodeGen/R600/vselect.ll
test/CodeGen/R600/work-item-intrinsics.ll
test/CodeGen/R600/wrong-transalu-pos-fix.ll [new file with mode: 0644]
test/CodeGen/R600/xor.ll