Test commit: Remove trailing whitespace.
[oota-llvm.git] / test / CodeGen / R600 /
2014-03-07 Tom StellardR600/SI: Using SGPRs is illegal for instructions that...
2014-03-07 Tom StellardR600/SI: Custom lower i1 stores
2014-03-06 Matt ArsenaultR600: Fix extloads from i8 / i16 to i64.
2014-03-06 Matt ArsenaultR600/SI: Expand selects on vectors.
2014-03-01 Matt ArsenaultR600: Add failing control flow tests.
2014-02-28 Tom StellardR600/SI: Expand all v16[if]32 operations
2014-02-27 Michel DanzerR600/SI: Optimize SI_KILL for constant operands
2014-02-27 Michel DanzerR600/SI: Allow SI_KILL for geometry shaders
2014-02-25 Tom StellardR600/SI: Custom select 64-bit ADD
2014-02-24 Matt ArsenaultR600/SI - Add new CI arithmetic instructions.
2014-02-22 Quentin Colombet[CodeGenPrepare] Fix the check of the legality of an...
2014-02-16 Nico RieckFix more broken CHECK lines
2014-02-14 Quentin Colombet[CodeGenPrepare][AddressingModeMatcher] Give up on...
2014-02-14 Tom StellardTargetLowering: n * r where n > 2 should be an illegal...
2014-02-13 Tom StellardR600/SI: Expand all v8[if]32 operations
2014-02-13 Tom StellardR600/SI: Add a pattern for i32 anyext
2014-02-13 Tom StellardR600/SI: Completely Disable TypeRewriter on compute
2014-02-13 Tom StellardR600/SI: Split global vector loads with more than 4...
2014-02-13 Tom StellardR600/SI: Add ShaderType attribute to some tests
2014-02-11 Matt ArsenaultR600/SI: Fix assertion on infinite loops.
2014-02-10 Tom StellardR600/SI: Initialize M0 and emit S_WQM_B64 whenever...
2014-02-07 Matt ArsenaultR600/SI: Add failing test for 3 x i64 vectors.
2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Reg+Imm offsets
2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Imm offsets
2014-02-06 Tom StellardR600/SI: Add a MUBUF load pattern for Reg+Imm offsets
2014-02-06 Tom StellardR600/SI: Use immediates offsets for SMRD instructions...
2014-02-05 Michel DanzerR600/SI: Add pattern for zero-extending i1 to i32
2014-02-04 Tom StellardR600/SI: Custom lower i64 ISD::SELECT
2014-02-04 Tom StellardR600: Enable vector fpow.
2014-02-04 Michel DanzerR600/SI: Fix fneg for 0.0
2014-02-02 Matt ArsenaultAdd some xfailed R600 tests for 64-bit private accesses.
2014-02-02 Matt ArsenaultR600/SI: Fix insertelement with dynamic indices.
2014-01-28 Michel DanzerR600/SI: Add pattern for truncating i32 to i1
2014-01-27 Michel DanzerR600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
2014-01-27 Michel DanzerR600/SI: Add intrinsic for S_SENDMSG instruction
2014-01-23 Tom StellardR600: Disable the BFE pattern
2014-01-23 Tom StellardR600: Correctly handle vertex fetch clauses the precede...
2014-01-23 Tom StellardR600: Unconditionally unroll loops that contain GEPs...
2014-01-23 Tom StellardR600: Recommit 199842: Add work-around for the CF stack...
2014-01-22 Tom StellardRevert "R600: Add work-around for the CF stack entry...
2014-01-22 Tom StellardR600: Add work-around for the CF stack entry HW bug
2014-01-22 Tom StellardR600: Refactor stack size calculation
2014-01-22 Tom StellardR600: MOVA is vector only
2014-01-22 Tom StellardR600: Take alignment into account when calculating...
2014-01-22 Tom StellardR600: Add support for global addresses with constant...
2014-01-22 Tom StellardR600: Begin private memory at the second GPR.
2014-01-22 Tom StellardR600/SI: Add support for i8 and i16 private loads/stores
2014-01-11 Benjamin KramerFix broken CHECK lines.
2013-12-20 Tom StellardR600: Allow ftrunc
2013-12-19 NAKAMURA TakumiAdd REQUIRES:asserts to 3 tests in llvm/test/CodeGen...
2013-12-19 Matt ArsenaultR600/SI: Make private pointers be 32-bit.
2013-12-14 Matt ArsenaultR600/SI: Minor improvements to test.
2013-12-10 Matt ArsenaultR600/SI: Add i64 cmp tests
2013-12-10 Vincent LejeuneR600: Fix an infinite loop when trying to reorganize...
2013-12-10 Vincent LejeuneR600: Fix input modifiers lost for Cayman
2013-12-07 Vincent LejeuneAdd a RequireStructuredCFG Field to TargetMachine.
2013-12-05 Matt ArsenaultR600/SI: Add comments for number of used registers.
2013-12-02 Vincent LejeuneR600: Workaround for cayman loop bug
2013-11-27 Tom StellardR600: Expand vector FABS
2013-11-27 Tom StellardR600/SI: Implement spilling of SGPRs v5
2013-11-27 Tom StellardR600/SI: Use SGPR_32 register class for 32-bit SMRD...
2013-11-27 Tom StellardR600: Add support for ISD::FROUND
2013-11-22 Tom StellardR600/SI: Fixing handling of condition codes
2013-11-22 Tom StellardSelectionDAG: Optimize expansion of vec_type = BITCAST...
2013-11-18 Matt ArsenaultR600/SI: Fix moveToVALU when the first operand is VSrc.
2013-11-18 Matt ArsenaultR600/SI: Fix multiple SGPR reads when using VCC.
2013-11-18 Matt ArsenaultR600/SI: Implement add i64, but do not yet enable.
2013-11-18 Matt ArsenaultR600/SI: Move patterns to match add / sub to scalar...
2013-11-18 Tom StellardR600: Enable the IR structurizer by default
2013-11-18 Tom StellardR600: Fix a crash in the AMDILCFGStrucurizer
2013-11-18 Tom StellardR600/SI: Fix illegal VGPR->SGPR copy inside of loop
2013-11-18 Tom StellardR600/SI: Fix another case of illegal VGPR->SGPR copy
2013-11-17 Matt ArsenaultUse right address space pointer size
2013-11-16 Matt ArsenaultFix assert on unaligned access to global with different...
2013-11-16 Matt ArsenaultFix codegen for null different sized pointer.
2013-11-16 Vincent LejeuneR600: Make dot_4 instructions predicable
2013-11-15 Tom StellardR600/SI: Add VReg_96 register class to SIRegisterInfo...
2013-11-15 Matt ArsenaultAdd target hook to prevent folding some bitcasted loads.
2013-11-15 Tom StellardR600: Fix scheduling of instructions that use the LDS...
2013-11-14 Matt ArsenaultR600/SI: Add testcase for problem I ran into
2013-11-13 Tom StellardR600/SI: Add support for private address space load...
2013-11-13 Tom StellardR600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 Matt ArsenaultR600: Fix selection failure on EXTLOAD
2013-11-12 Matt ArsenaultR600/SI: Change formatting of printed registers.
2013-11-11 Matt ArsenaultR600/SI: Add test that fails due to requiring i64 mul...
2013-11-11 Vincent LejeuneR600: Use function inputs to represent data stored...
2013-11-06 Vincent LejeuneR600: Fix LowerUDIVREM
2013-10-30 Matt ArsenaultFix CodeGen for unaligned loads with address spaces
2013-10-30 Tom StellardR600: Custom lower f32 = uint_to_fp i64
2013-10-29 Tom StellardR600/SI: Add compute support for CI v2
2013-10-29 Tom StellardR600: Expand vector FSQRT ops
2013-10-23 Tom StellardR600/SI: fix MIMG writemask adjustement
2013-10-23 Tom StellardR600: Fix handling of vector kernel arguments
2013-10-23 Tom StellardR600/SI: Add support for i64 bitwise or
2013-10-23 Tom StellardR600/SI: Use S_LOAD_DWORD instructions for v8i32 and...
2013-10-22 Tom StellardR600: Simplify handling of private address space
2013-10-21 Matt ArsenaultFix CodeGen for vectors of pointers with address spaces.
2013-10-21 Matt ArsenaultFix CodeGen for different size address space GEPs
2013-10-16 Tom StellardR600: Fix a crash in the AMDILCFGStructurizer
2013-10-13 Vincent LejeuneR600: improve dump of S_WAITCNT
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