R600/SI: Use SGPR_32 register class for 32-bit SMRD outputs
authorTom Stellard <thomas.stellard@amd.com>
Wed, 27 Nov 2013 21:23:29 +0000 (21:23 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Wed, 27 Nov 2013 21:23:29 +0000 (21:23 +0000)
commit0cbf94373364faa79e3e30ed96d00fe42c4fd7f6
treedb192fb6e596b2770ea5cc512feca43020e2ac77
parent496dbfe7b9fd0ad986b425e5b1543fefb1812b8e
R600/SI: Use SGPR_32 register class for 32-bit SMRD outputs

Writing to the M0 register from an SMRD instruction hangs the GPU, so
we need to use the SGPR_32 register class, which does not include M0.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195879 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/SIInstructions.td
test/CodeGen/R600/si-sgpr-spill.ll [new file with mode: 0644]