R600/SI: Prefer SALU instructions for bit shift operations
authorTom Stellard <thomas.stellard@amd.com>
Wed, 13 Nov 2013 23:36:37 +0000 (23:36 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Wed, 13 Nov 2013 23:36:37 +0000 (23:36 +0000)
commitb52bf6a3b31596a309f4b12884522e9b4a344654
tree60294ecd3670543e55b24aca1a4507c391649203
parenteef8b8c35c585d941fb14c66df3cebc46b33f776
R600/SI: Prefer SALU instructions for bit shift operations

All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.

This patch includes some fixes from Matt Arsenault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
17 files changed:
lib/Target/R600/SIDefines.h
lib/Target/R600/SIFixSGPRCopies.cpp
lib/Target/R600/SIInstrFormats.td
lib/Target/R600/SIInstrInfo.cpp
lib/Target/R600/SIInstrInfo.h
lib/Target/R600/SIInstrInfo.td
lib/Target/R600/SIInstructions.td
lib/Target/R600/SIRegisterInfo.cpp
lib/Target/R600/SIRegisterInfo.h
test/CodeGen/R600/fneg.ll
test/CodeGen/R600/load.ll
test/CodeGen/R600/lshl.ll
test/CodeGen/R600/lshr.ll
test/CodeGen/R600/mad_uint24.ll
test/CodeGen/R600/mul_uint24.ll
test/CodeGen/R600/sra.ll
test/CodeGen/R600/trunc.ll