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(parent: 695de76) | patch
R600/SI: Fixing handling of condition codes
authorTom Stellard <thomas.stellard@amd.com>
Fri, 22 Nov 2013 23:07:58 +0000 (23:07 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Fri, 22 Nov 2013 23:07:58 +0000 (23:07 +0000)
commit0f3982734058d9039d986e9d1dd3a879ff3512f0
treeaf772a39274b3bf23567b7b493058f58da04b7a9tree | snapshot
parent695de7692c26f5cb57eb67edb6b9ccf6d0ddafa2commit | diff
R600/SI: Fixing handling of condition codes

We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195514 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/AMDGPUInstructions.td diff | blob | history
lib/Target/R600/R600Instructions.td diff | blob | history
lib/Target/R600/SIISelLowering.cpp diff | blob | history
lib/Target/R600/SIInstructions.td diff | blob | history
test/CodeGen/R600/setcc.ll diff | blob | history
test/CodeGen/R600/setcc64.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors