[PowerPC] Implement combineRepeatedFPDivisors
[oota-llvm.git] / lib / Target /
2014-11-24 Hal Finkel[PowerPC] Implement combineRepeatedFPDivisors
2014-11-24 Chad Rosier[AArch64] Fix clobber computation in A57LoadBalancing...
2014-11-24 Colin LeMahieuRemoving unused variable.
2014-11-24 Ulrich Weigand[PowerPC] Fix PR 21652 - copy st_other bits on symbol...
2014-11-24 Colin LeMahieu[Hexagon] Adding asrh instruction, removing unused...
2014-11-24 Colin LeMahieu[Hexagon] Adding aslh instruction.
2014-11-24 Colin LeMahieu[Hexagon] Adding zxth instruction.
2014-11-24 Colin LeMahieu[Hexagon] Adding zxtb instruction.
2014-11-24 Jozef Kolek[mips][microMIPS] Fix JRADDIUSP instruction
2014-11-24 Jozef Kolek[mips][microMIPS] Implement LBU16, LHU16, LW16, SB16...
2014-11-24 Jozef Kolek[mips][microMIPS] Implement 16-bit instructions registe...
2014-11-24 Aaron BallmanRemoving a variable that is initialized but never read...
2014-11-24 Jozef Kolek[mips][microMIPS] Implement disassembler support for...
2014-11-24 Andrea Di Biagio[X86] Improved target specific combine on VSELECT dag...
2014-11-23 Michael Kuperstein[X86] Fixes bug in build_vector v4x32 lowering
2014-11-23 Craig TopperAdd missing override keywords.
2014-11-23 Elena DemikhovskyMasked Vector Load and Store Intrinsics.
2014-11-23 Matt ArsenaultR600: Fix extloads of i1 on R600/Evergreen
2014-11-23 Matt ArsenaultR600: Fix assert on copy of an i1 on pre-SI
2014-11-22 Simon PilgrimTidied up target triple OS detection. NFC
2014-11-22 Chandler Carruth[x86] Teach the vector shuffle yet another step of...
2014-11-21 Joerg SonnenbergerFix transformation of add with pc argument to adr for...
2014-11-21 Tom StellardR600/SI: Add an s_mov_b32 to patterns which use the...
2014-11-21 Tom StellardR600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
2014-11-21 Tom StellardR600/SI: Add SIFoldOperands pass
2014-11-21 Jozef Kolek[mips][microMIPS] This patch implements functionality...
2014-11-21 Tom StellardR600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializable
2014-11-21 Colin LeMahieu[Hexagon] Adding sxth instruction.
2014-11-21 Colin LeMahieu[Hexagon] Adding sxtb instruction. Renaming some ident...
2014-11-21 Colin LeMahieu[Hexagon] Removing SUB_rr and replacing with A2_sub.
2014-11-21 Sanjay PatelAdd a feature flag for slow 32-byte unaligned memory...
2014-11-21 Chandler Carruth[x86] Restructure the checking patterns for v16 and...
2014-11-21 Chandler Carruth[x86] Make the previous logic significantly less conser...
2014-11-21 Chandler Carruth[x86] Teach the x86 vector shuffle lowering to detect...
2014-11-21 Alexey Volkov[X86] For Silvermont CPU use 16-bit division instead...
2014-11-21 NAKAMURA TakumiAdd LLVMScalarOpts to LLVMPowerPCCodeGen.
2014-11-21 Hao LiuDAGCombiner: Allow the DAGCombiner to combine multiple...
2014-11-21 Craig TopperRemove a bunch of unnecessary typecasts to 'const Targe...
2014-11-21 Hal Finkel[PPC] Use SeparateConstOffsetFromGEP
2014-11-21 Quentin Colombet[X86] Do not custom lower UINT_TO_FP when the target...
2014-11-20 Reid KlecknerFix more instances of -Wsentinel on Windows with s...
2014-11-20 Reid KlecknerAdd out of line virtual destructors to all LLVMTargetMa...
2014-11-20 Mehdi AminiUpdate Makefile following directory removal in r222466
2014-11-20 Colin LeMahieu[Hexagon] [NFC] Merging InstPrinter directory in to...
2014-11-20 Saleem AbdulrasoolX86: use the correct alloca symbol for Windows Itanium
2014-11-20 Jyoti Allur[ELF] Prevent ARM ELF object writer from generating...
2014-11-20 Craig TopperFix a typo in a comment.
2014-11-19 Colin LeMahieu[Hexagon] Adding A2_xor instruction with IR selection...
2014-11-19 Colin LeMahieu[Hexagon] Adding A2_or instruction with IR selection...
2014-11-19 Andrea Di Biagio[X86] Improved lowering of v4x32 build_vector dag nodes.
2014-11-19 Tom StellardR600/SI: Make SIInstrInfo::isOperandLegal() more strict
2014-11-19 Zoran Jovanovic[mips][micromips] Implement SWM32 and LWM32 instructions
2014-11-19 Jozef Kolek[mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instru...
2014-11-19 Jozef Kolek[mips][microMIPS] Implement CodeGen support for 16...
2014-11-19 Jozef Kolek[mips][microMIPS] Implement CodeGen support for ADDIUS5...
2014-11-19 Jozef Kolek[mips][microMIPS] Implement LWXS instruction.
2014-11-19 Jozef Kolek[mips][microMIPS] Implement SDBBP and RDHWR instructions.
2014-11-19 Simon Pilgrim[X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2
2014-11-19 David BlaikieUpdate SetVector to rely on the underlying set's insert...
2014-11-19 Hao Liu[AArch64] Disable useAA for Cortex-A57.
2014-11-19 Hao Liu[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE...
2014-11-19 David BlaikieRemove StringMap::GetOrCreateValue in favor of StringMa...
2014-11-19 Weiming Zhao[Aarch64] Customer lowering of CTPOP to SIMD should...
2014-11-19 Matt ArsenaultR600/SI: Implement areMemAccessesTriviallyDisjoint
2014-11-18 Matt ArsenaultR600/SI: Set hasSideEffects = 0 on load and store instr...
2014-11-18 Simon Pilgrim[X86][AVX] 256-bit vector stack unaligned load/stores...
2014-11-18 Colin LeMahieu[Hexagon] Adding A2_and instruction.
2014-11-18 Chad Rosier[FastISel][AArch64] Also allow folding of sign-/zero...
2014-11-18 Chad Rosier[FastISel][AArch64] Also allow folding of sign-/zero...
2014-11-18 Colin LeMahieu[Hexagon] Adding A2_sub instruction
2014-11-18 Juergen Ributzka[FastISel][AArch64] Follow-up fix for "Fix shift-immedi...
2014-11-18 Matt ArsenaultR600/SI: Move SIFixSGPRCopies to inst selector passes
2014-11-18 Juergen Ributzka[AArch64] Don't optimize all compare instructions.
2014-11-18 Tom StellardR600/SI: Make sure resource descriptors are always...
2014-11-18 Colin LeMahieu[Hexagon] Converting from ADD_rr to A2_add which has...
2014-11-18 Juergen Ributzka[FastISel][AArch64] Fix shift-immediate emission for...
2014-11-18 Jozef KolekTest commit to verify that commit access works.
2014-11-17 Reid KlecknerRevert "ADT: correctly report isMSVCEnvironment for...
2014-11-17 Saleem AbdulrasoolADT: correctly report isMSVCEnvironment for windows...
2014-11-17 Matt ArsenaultR600/SI: Don't copy flags when extracting subreg
2014-11-17 Matt ArsenaultR600/SI: Assume SIFixSGPRCopies makes changes
2014-11-17 Alexey Volkov[X86] Use ADD/SUB instead of INC/DEC for Haswell and...
2014-11-17 Oliver Stannard[Thumb1] Re-write emitThumbRegPlusImmediate
2014-11-16 Craig TopperConvert some EVTs to MVTs where only a SimpleValueType...
2014-11-16 Craig Topper[x86] Remove two redundant isel patterns. They equivale...
2014-11-15 Simon Pilgrim[X86][SSE] Improve legal SHUFP and PSHUFD shuffle matching
2014-11-15 Matt ArsenaultR600: Permute operands when selecting legacy min/max
2014-11-15 Tom StellardR600: Fix 64-bit integer division
2014-11-15 Tom StellardR600: Factor i64 UDIVREM lowering into its own fuction
2014-11-14 Reid KlecknerRename EH related stuff to be more precise
2014-11-14 Tim NorthoverARM: refactor .cfi_def_cfa_offset emission.
2014-11-14 Tim NorthoverARM: correctly calculate the offset of FP in its push.
2014-11-14 Tom StellardR600/SI: Mark s_movk_i32 as rematerializable
2014-11-14 Tom StellardR600/SI: Fix spilling of m0 register
2014-11-14 Matt ArsenaultR600/SI: Combine min3/max3 instructions
2014-11-14 Matt ArsenaultR600/SI: Fix verifier error from a branch on IMPLICIT_DEF
2014-11-14 Matt ArsenaultFix unused variable warning without asserts
2014-11-14 Matt ArsenaultR600/SI: Match integer min / max instructions
2014-11-14 Matt ArsenaultR600/SI: Use S_BFE_I64 for 64-bit sext_inreg
2014-11-14 Cameron McInally[AVX512] Add 512b masked integer shift by immediate...
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