-//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file performs vector type splitting and scalarization for LegalizeTypes.
-// Scalarization is the act of changing a computation in an illegal one-element
-// vector type to be a computation in its scalar element type. For example,
-// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
-// as a base case when scalarizing vector arithmetic like <4 x f32>, which
-// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
-// types.
-// Splitting is the act of changing a computation in an invalid vector type to
-// be a computation in two vectors of half the size. For example, implementing
-// <128 x f32> operations in terms of two <64 x f32> operations.
-//
-//===----------------------------------------------------------------------===//
-
-#include "LegalizeTypes.h"
-#include "llvm/IR/DataLayout.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-#define DEBUG_TYPE "legalize-types"
-
-//===----------------------------------------------------------------------===//
-// Result Vector Scalarization: <1 x ty> -> ty.
-//===----------------------------------------------------------------------===//
-
-void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
- DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n");
- SDValue R = SDValue();
-
- switch (N->getOpcode()) {
- default:
-#ifndef NDEBUG
- dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n";
-#endif
- report_fatal_error("Do not know how to scalarize the result of this "
- "operator!\n");
-
- case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
- case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
- case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
- case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
- case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
- case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
- case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
- case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
- case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
- case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
- case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
- case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
- case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
- case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
- case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
- case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
- case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
- case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
- case ISD::ANY_EXTEND:
- case ISD::BSWAP:
- case ISD::CTLZ:
- case ISD::CTLZ_ZERO_UNDEF:
- case ISD::CTPOP:
- case ISD::CTTZ:
- case ISD::CTTZ_ZERO_UNDEF:
- case ISD::FABS:
- case ISD::FCEIL:
- case ISD::FCOS:
- case ISD::FEXP:
- case ISD::FEXP2:
- case ISD::FFLOOR:
- case ISD::FLOG:
- case ISD::FLOG10:
- case ISD::FLOG2:
- case ISD::FNEARBYINT:
- case ISD::FNEG:
- case ISD::FP_EXTEND:
- case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT:
- case ISD::FRINT:
- case ISD::FROUND:
- case ISD::FSIN:
- case ISD::FSQRT:
- case ISD::FTRUNC:
- case ISD::SIGN_EXTEND:
- case ISD::SINT_TO_FP:
- case ISD::TRUNCATE:
- case ISD::UINT_TO_FP:
- case ISD::ZERO_EXTEND:
- R = ScalarizeVecRes_UnaryOp(N);
- break;
-
- case ISD::ADD:
- case ISD::AND:
- case ISD::FADD:
- case ISD::FCOPYSIGN:
- case ISD::FDIV:
- case ISD::FMUL:
- case ISD::FMINNUM:
- case ISD::FMAXNUM:
-
- case ISD::FPOW:
- case ISD::FREM:
- case ISD::FSUB:
- case ISD::MUL:
- case ISD::OR:
- case ISD::SDIV:
- case ISD::SREM:
- case ISD::SUB:
- case ISD::UDIV:
- case ISD::UREM:
- case ISD::XOR:
- case ISD::SHL:
- case ISD::SRA:
- case ISD::SRL:
- R = ScalarizeVecRes_BinOp(N);
- break;
- case ISD::FMA:
- R = ScalarizeVecRes_TernaryOp(N);
- break;
- }
-
- // If R is null, the sub-method took care of registering the result.
- if (R.getNode())
- SetScalarizedVector(SDValue(N, ResNo), R);
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
- SDValue LHS = GetScalarizedVector(N->getOperand(0));
- SDValue RHS = GetScalarizedVector(N->getOperand(1));
- return DAG.getNode(N->getOpcode(), SDLoc(N),
- LHS.getValueType(), LHS, RHS);
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
- SDValue Op0 = GetScalarizedVector(N->getOperand(0));
- SDValue Op1 = GetScalarizedVector(N->getOperand(1));
- SDValue Op2 = GetScalarizedVector(N->getOperand(2));
- return DAG.getNode(N->getOpcode(), SDLoc(N),
- Op0.getValueType(), Op0, Op1, Op2);
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
- unsigned ResNo) {
- SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
- return GetScalarizedVector(Op);
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
- EVT NewVT = N->getValueType(0).getVectorElementType();
- return DAG.getNode(ISD::BITCAST, SDLoc(N),
- NewVT, N->getOperand(0));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
- EVT EltVT = N->getValueType(0).getVectorElementType();
- SDValue InOp = N->getOperand(0);
- // The BUILD_VECTOR operands may be of wider element types and
- // we may need to truncate them back to the requested return type.
- if (EltVT.isInteger())
- return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
- return InOp;
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
- EVT NewVT = N->getValueType(0).getVectorElementType();
- SDValue Op0 = GetScalarizedVector(N->getOperand(0));
- return DAG.getConvertRndSat(NewVT, SDLoc(N),
- Op0, DAG.getValueType(NewVT),
- DAG.getValueType(Op0.getValueType()),
- N->getOperand(3),
- N->getOperand(4),
- cast<CvtRndSatSDNode>(N)->getCvtCode());
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
- N->getValueType(0).getVectorElementType(),
- N->getOperand(0), N->getOperand(1));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
- EVT NewVT = N->getValueType(0).getVectorElementType();
- SDValue Op = GetScalarizedVector(N->getOperand(0));
- return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
- NewVT, Op, N->getOperand(1));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
- SDValue Op = GetScalarizedVector(N->getOperand(0));
- return DAG.getNode(ISD::FPOWI, SDLoc(N),
- Op.getValueType(), Op, N->getOperand(1));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
- // The value to insert may have a wider type than the vector element type,
- // so be sure to truncate it to the element type if necessary.
- SDValue Op = N->getOperand(1);
- EVT EltVT = N->getValueType(0).getVectorElementType();
- if (Op.getValueType() != EltVT)
- // FIXME: Can this happen for floating point types?
- Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
- return Op;
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
- assert(N->isUnindexed() && "Indexed vector load?");
-
- SDValue Result = DAG.getLoad(ISD::UNINDEXED,
- N->getExtensionType(),
- N->getValueType(0).getVectorElementType(),
- SDLoc(N),
- N->getChain(), N->getBasePtr(),
- DAG.getUNDEF(N->getBasePtr().getValueType()),
- N->getPointerInfo(),
- N->getMemoryVT().getVectorElementType(),
- N->isVolatile(), N->isNonTemporal(),
- N->isInvariant(), N->getOriginalAlignment(),
- N->getAAInfo());
-
- // Legalized the chain result - switch anything that used the old chain to
- // use the new one.
- ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
- return Result;
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
- // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
- EVT DestVT = N->getValueType(0).getVectorElementType();
- SDValue Op = N->getOperand(0);
- EVT OpVT = Op.getValueType();
- SDLoc DL(N);
- // The result needs scalarizing, but it's not a given that the source does.
- // This is a workaround for targets where it's impossible to scalarize the
- // result of a conversion, because the source type is legal.
- // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
- // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
- // legal and was not scalarized.
- // See the similar logic in ScalarizeVecRes_VSETCC
- if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
- Op = GetScalarizedVector(Op);
- } else {
- EVT VT = OpVT.getVectorElementType();
- Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- }
- return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
- EVT EltVT = N->getValueType(0).getVectorElementType();
- EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
- SDValue LHS = GetScalarizedVector(N->getOperand(0));
- return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
- LHS, DAG.getValueType(ExtVT));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
- // If the operand is wider than the vector element type then it is implicitly
- // truncated. Make that explicit here.
- EVT EltVT = N->getValueType(0).getVectorElementType();
- SDValue InOp = N->getOperand(0);
- if (InOp.getValueType() != EltVT)
- return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
- return InOp;
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
- SDValue Cond = GetScalarizedVector(N->getOperand(0));
- SDValue LHS = GetScalarizedVector(N->getOperand(1));
- TargetLowering::BooleanContent ScalarBool =
- TLI.getBooleanContents(false, false);
- TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
-
- // If integer and float booleans have different contents then we can't
- // reliably optimize in all cases. There is a full explanation for this in
- // DAGCombiner::visitSELECT() where the same issue affects folding
- // (select C, 0, 1) to (xor C, 1).
- if (TLI.getBooleanContents(false, false) !=
- TLI.getBooleanContents(false, true)) {
- // At least try the common case where the boolean is generated by a
- // comparison.
- if (Cond->getOpcode() == ISD::SETCC) {
- EVT OpVT = Cond->getOperand(0)->getValueType(0);
- ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
- VecBool = TLI.getBooleanContents(OpVT);
- } else
- ScalarBool = TargetLowering::UndefinedBooleanContent;
- }
-
- if (ScalarBool != VecBool) {
- EVT CondVT = Cond.getValueType();
- switch (ScalarBool) {
- case TargetLowering::UndefinedBooleanContent:
- break;
- case TargetLowering::ZeroOrOneBooleanContent:
- assert(VecBool == TargetLowering::UndefinedBooleanContent ||
- VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
- // Vector read from all ones, scalar expects a single 1 so mask.
- Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
- Cond, DAG.getConstant(1, CondVT));
- break;
- case TargetLowering::ZeroOrNegativeOneBooleanContent:
- assert(VecBool == TargetLowering::UndefinedBooleanContent ||
- VecBool == TargetLowering::ZeroOrOneBooleanContent);
- // Vector reads from a one, scalar from all ones so sign extend.
- Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
- Cond, DAG.getValueType(MVT::i1));
- break;
- }
- }
-
- return DAG.getSelect(SDLoc(N),
- LHS.getValueType(), Cond, LHS,
- GetScalarizedVector(N->getOperand(2)));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
- SDValue LHS = GetScalarizedVector(N->getOperand(1));
- return DAG.getSelect(SDLoc(N),
- LHS.getValueType(), N->getOperand(0), LHS,
- GetScalarizedVector(N->getOperand(2)));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
- SDValue LHS = GetScalarizedVector(N->getOperand(2));
- return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
- N->getOperand(0), N->getOperand(1),
- LHS, GetScalarizedVector(N->getOperand(3)),
- N->getOperand(4));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
- assert(N->getValueType(0).isVector() ==
- N->getOperand(0).getValueType().isVector() &&
- "Scalar/Vector type mismatch");
-
- if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
-
- SDValue LHS = GetScalarizedVector(N->getOperand(0));
- SDValue RHS = GetScalarizedVector(N->getOperand(1));
- SDLoc DL(N);
-
- // Turn it into a scalar SETCC.
- return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
- return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
- // Figure out if the scalar is the LHS or RHS and return it.
- SDValue Arg = N->getOperand(2).getOperand(0);
- if (Arg.getOpcode() == ISD::UNDEF)
- return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
- unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
- return GetScalarizedVector(N->getOperand(Op));
-}
-
-SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
- assert(N->getValueType(0).isVector() &&
- N->getOperand(0).getValueType().isVector() &&
- "Operand types must be vectors");
- SDValue LHS = N->getOperand(0);
- SDValue RHS = N->getOperand(1);
- EVT OpVT = LHS.getValueType();
- EVT NVT = N->getValueType(0).getVectorElementType();
- SDLoc DL(N);
-
- // The result needs scalarizing, but it's not a given that the source does.
- if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
- LHS = GetScalarizedVector(LHS);
- RHS = GetScalarizedVector(RHS);
- } else {
- EVT VT = OpVT.getVectorElementType();
- LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- }
-
- // Turn it into a scalar SETCC.
- SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
- N->getOperand(2));
- // Vectors may have a different boolean contents to scalars. Promote the
- // value appropriately.
- ISD::NodeType ExtendCode =
- TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
- return DAG.getNode(ExtendCode, DL, NVT, Res);
-}
-
-
-//===----------------------------------------------------------------------===//
-// Operand Vector Scalarization <1 x ty> -> ty.
-//===----------------------------------------------------------------------===//
-
-bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
- DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n");
- SDValue Res = SDValue();
-
- if (!Res.getNode()) {
- switch (N->getOpcode()) {
- default:
-#ifndef NDEBUG
- dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n";
-#endif
- llvm_unreachable("Do not know how to scalarize this operator's operand!");
- case ISD::BITCAST:
- Res = ScalarizeVecOp_BITCAST(N);
- break;
- case ISD::ANY_EXTEND:
- case ISD::ZERO_EXTEND:
- case ISD::SIGN_EXTEND:
- case ISD::TRUNCATE:
- case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT:
- case ISD::SINT_TO_FP:
- case ISD::UINT_TO_FP:
- Res = ScalarizeVecOp_UnaryOp(N);
- break;
- case ISD::CONCAT_VECTORS:
- Res = ScalarizeVecOp_CONCAT_VECTORS(N);
- break;
- case ISD::EXTRACT_VECTOR_ELT:
- Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
- break;
- case ISD::VSELECT:
- Res = ScalarizeVecOp_VSELECT(N);
- break;
- case ISD::STORE:
- Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
- break;
- case ISD::FP_ROUND:
- Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
- break;
- }
- }
-
- // If the result is null, the sub-method took care of registering results etc.
- if (!Res.getNode()) return false;
-
- // If the result is N, the sub-method updated N in place. Tell the legalizer
- // core about this.
- if (Res.getNode() == N)
- return true;
-
- assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
- "Invalid operand expansion");
-
- ReplaceValueWith(SDValue(N, 0), Res);
- return false;
-}
-
-/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
-/// to be scalarized, it must be <1 x ty>. Convert the element instead.
-SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
- SDValue Elt = GetScalarizedVector(N->getOperand(0));
- return DAG.getNode(ISD::BITCAST, SDLoc(N),
- N->getValueType(0), Elt);
-}
-
-/// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
-/// scalarized, it must be <1 x ty>. Do the operation on the element instead.
-SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
- assert(N->getValueType(0).getVectorNumElements() == 1 &&
- "Unexpected vector type!");
- SDValue Elt = GetScalarizedVector(N->getOperand(0));
- SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
- N->getValueType(0).getScalarType(), Elt);
- // Revectorize the result so the types line up with what the uses of this
- // expression expect.
- return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
-}
-
-/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
-/// use a BUILD_VECTOR instead.
-SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
- SmallVector<SDValue, 8> Ops(N->getNumOperands());
- for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
- Ops[i] = GetScalarizedVector(N->getOperand(i));
- return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
-}
-
-/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
-/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
-/// index.
-SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
- SDValue Res = GetScalarizedVector(N->getOperand(0));
- if (Res.getValueType() != N->getValueType(0))
- Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
- Res);
- return Res;
-}
-
-
-/// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
-/// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
-/// (still with vector output type since that was acceptable if we got here).
-SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
- SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
- EVT VT = N->getValueType(0);
-
- return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
- N->getOperand(2));
-}
-
-/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
-/// scalarized, it must be <1 x ty>. Just store the element.
-SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
- assert(N->isUnindexed() && "Indexed store of one-element vector?");
- assert(OpNo == 1 && "Do not know how to scalarize this operand!");
- SDLoc dl(N);
-
- if (N->isTruncatingStore())
- return DAG.getTruncStore(N->getChain(), dl,
- GetScalarizedVector(N->getOperand(1)),
- N->getBasePtr(), N->getPointerInfo(),
- N->getMemoryVT().getVectorElementType(),
- N->isVolatile(), N->isNonTemporal(),
- N->getAlignment(), N->getAAInfo());
-
- return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
- N->getBasePtr(), N->getPointerInfo(),
- N->isVolatile(), N->isNonTemporal(),
- N->getOriginalAlignment(), N->getAAInfo());
-}
-
-/// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
-/// to be scalarized, it must be <1 x ty>. Convert the element instead.
-SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
- SDValue Elt = GetScalarizedVector(N->getOperand(0));
- SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
- N->getValueType(0).getVectorElementType(), Elt,
- N->getOperand(1));
- return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
-}
-
-//===----------------------------------------------------------------------===//
-// Result Vector Splitting
-//===----------------------------------------------------------------------===//
-
-/// SplitVectorResult - This method is called when the specified result of the
-/// specified node is found to need vector splitting. At this point, the node
-/// may also have invalid operands or may have other results that need
-/// legalization, we just know that (at least) one result needs vector
-/// splitting.
-void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
- DEBUG(dbgs() << "Split node result: ";
- N->dump(&DAG);
- dbgs() << "\n");
- SDValue Lo, Hi;
-
- // See if the target wants to custom expand this node.
- if (CustomLowerNode(N, N->getValueType(ResNo), true))
- return;
-
- switch (N->getOpcode()) {
- default:
-#ifndef NDEBUG
- dbgs() << "SplitVectorResult #" << ResNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n";
-#endif
- report_fatal_error("Do not know how to split the result of this "
- "operator!\n");
-
- case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
- case ISD::VSELECT:
- case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
- case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
- case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
- case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
- case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
- case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
- case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
- case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
- case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
- case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
- case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
- case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
- case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
- case ISD::LOAD:
- SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
- break;
- case ISD::SETCC:
- SplitVecRes_SETCC(N, Lo, Hi);
- break;
- case ISD::VECTOR_SHUFFLE:
- SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
- break;
-
- case ISD::BSWAP:
- case ISD::CONVERT_RNDSAT:
- case ISD::CTLZ:
- case ISD::CTTZ:
- case ISD::CTLZ_ZERO_UNDEF:
- case ISD::CTTZ_ZERO_UNDEF:
- case ISD::CTPOP:
- case ISD::FABS:
- case ISD::FCEIL:
- case ISD::FCOS:
- case ISD::FEXP:
- case ISD::FEXP2:
- case ISD::FFLOOR:
- case ISD::FLOG:
- case ISD::FLOG10:
- case ISD::FLOG2:
- case ISD::FNEARBYINT:
- case ISD::FNEG:
- case ISD::FP_EXTEND:
- case ISD::FP_ROUND:
- case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT:
- case ISD::FRINT:
- case ISD::FROUND:
- case ISD::FSIN:
- case ISD::FSQRT:
- case ISD::FTRUNC:
- case ISD::SINT_TO_FP:
- case ISD::TRUNCATE:
- case ISD::UINT_TO_FP:
- SplitVecRes_UnaryOp(N, Lo, Hi);
- break;
-
- case ISD::ANY_EXTEND:
- case ISD::SIGN_EXTEND:
- case ISD::ZERO_EXTEND:
- SplitVecRes_ExtendOp(N, Lo, Hi);
- break;
-
- case ISD::ADD:
- case ISD::SUB:
- case ISD::MUL:
- case ISD::FADD:
- case ISD::FCOPYSIGN:
- case ISD::FSUB:
- case ISD::FMUL:
- case ISD::FMINNUM:
- case ISD::FMAXNUM:
- case ISD::SDIV:
- case ISD::UDIV:
- case ISD::FDIV:
- case ISD::FPOW:
- case ISD::AND:
- case ISD::OR:
- case ISD::XOR:
- case ISD::SHL:
- case ISD::SRA:
- case ISD::SRL:
- case ISD::UREM:
- case ISD::SREM:
- case ISD::FREM:
- SplitVecRes_BinOp(N, Lo, Hi);
- break;
- case ISD::FMA:
- SplitVecRes_TernaryOp(N, Lo, Hi);
- break;
- }
-
- // If Lo/Hi is null, the sub-method took care of registering results etc.
- if (Lo.getNode())
- SetSplitVector(SDValue(N, ResNo), Lo, Hi);
-}
-
-void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- SDValue LHSLo, LHSHi;
- GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
- SDValue RHSLo, RHSHi;
- GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
- SDLoc dl(N);
-
- Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
- Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
-}
-
-void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- SDValue Op0Lo, Op0Hi;
- GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
- SDValue Op1Lo, Op1Hi;
- GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
- SDValue Op2Lo, Op2Hi;
- GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
- SDLoc dl(N);
-
- Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
- Op0Lo, Op1Lo, Op2Lo);
- Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
- Op0Hi, Op1Hi, Op2Hi);
-}
-
-void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- // We know the result is a vector. The input may be either a vector or a
- // scalar value.
- EVT LoVT, HiVT;
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
- SDLoc dl(N);
-
- SDValue InOp = N->getOperand(0);
- EVT InVT = InOp.getValueType();
-
- // Handle some special cases efficiently.
- switch (getTypeAction(InVT)) {
- case TargetLowering::TypeLegal:
- case TargetLowering::TypePromoteInteger:
- case TargetLowering::TypeSoftenFloat:
- case TargetLowering::TypeScalarizeVector:
- case TargetLowering::TypeWidenVector:
- break;
- case TargetLowering::TypeExpandInteger:
- case TargetLowering::TypeExpandFloat:
- // A scalar to vector conversion, where the scalar needs expansion.
- // If the vector is being split in two then we can just convert the
- // expanded pieces.
- if (LoVT == HiVT) {
- GetExpandedOp(InOp, Lo, Hi);
- if (TLI.isBigEndian())
- std::swap(Lo, Hi);
- Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
- Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
- return;
- }
- break;
- case TargetLowering::TypeSplitVector:
- // If the input is a vector that needs to be split, convert each split
- // piece of the input now.
- GetSplitVector(InOp, Lo, Hi);
- Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
- Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
- return;
- }
-
- // In the general case, convert the input to an integer and split it by hand.
- EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
- EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
- if (TLI.isBigEndian())
- std::swap(LoIntVT, HiIntVT);
-
- SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
-
- if (TLI.isBigEndian())
- std::swap(Lo, Hi);
- Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
- Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
-}
-
-void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- EVT LoVT, HiVT;
- SDLoc dl(N);
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
- unsigned LoNumElts = LoVT.getVectorNumElements();
- SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
- Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
-
- SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
- Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
-}
-
-void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
- SDLoc dl(N);
- unsigned NumSubvectors = N->getNumOperands() / 2;
- if (NumSubvectors == 1) {
- Lo = N->getOperand(0);
- Hi = N->getOperand(1);
- return;
- }
-
- EVT LoVT, HiVT;
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
-
- SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
- Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
-
- SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
- Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
-}
-
-void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- SDValue Vec = N->getOperand(0);
- SDValue Idx = N->getOperand(1);
- SDLoc dl(N);
-
- EVT LoVT, HiVT;
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
-
- Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
- uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
- Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
- DAG.getConstant(IdxVal + LoVT.getVectorNumElements(),
- TLI.getVectorIdxTy()));
-}
-
-void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- SDValue Vec = N->getOperand(0);
- SDValue SubVec = N->getOperand(1);
- SDValue Idx = N->getOperand(2);
- SDLoc dl(N);
- GetSplitVector(Vec, Lo, Hi);
-
- // Spill the vector to the stack.
- EVT VecVT = Vec.getValueType();
- EVT SubVecVT = VecVT.getVectorElementType();
- SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
- SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
- MachinePointerInfo(), false, false, 0);
-
- // Store the new subvector into the specified index.
- SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
- Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
- unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
- Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
- false, false, 0);
-
- // Load the Lo part from the stack slot.
- Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
- false, false, false, 0);
-
- // Increment the pointer to the other part.
- unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
- StackPtr =
- DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
- DAG.getConstant(IncrementSize, StackPtr.getValueType()));
-
- // Load the Hi part from the stack slot.
- Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
- false, false, false, MinAlign(Alignment, IncrementSize));
-}
-
-void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- SDLoc dl(N);
- GetSplitVector(N->getOperand(0), Lo, Hi);
- Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
- Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
-}
-
-void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- SDValue LHSLo, LHSHi;
- GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
- SDLoc dl(N);
-
- EVT LoVT, HiVT;
- std::tie(LoVT, HiVT) =
- DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
-
- Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
- DAG.getValueType(LoVT));
- Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
- DAG.getValueType(HiVT));
-}
-
-void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- SDValue Vec = N->getOperand(0);
- SDValue Elt = N->getOperand(1);
- SDValue Idx = N->getOperand(2);
- SDLoc dl(N);
- GetSplitVector(Vec, Lo, Hi);
-
- if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
- unsigned IdxVal = CIdx->getZExtValue();
- unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
- if (IdxVal < LoNumElts)
- Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
- Lo.getValueType(), Lo, Elt, Idx);
- else
- Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
- DAG.getConstant(IdxVal - LoNumElts,
- TLI.getVectorIdxTy()));
- return;
- }
-
- // See if the target wants to custom expand this node.
- if (CustomLowerNode(N, N->getValueType(0), true))
- return;
-
- // Spill the vector to the stack.
- EVT VecVT = Vec.getValueType();
- EVT EltVT = VecVT.getVectorElementType();
- SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
- SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
- MachinePointerInfo(), false, false, 0);
-
- // Store the new element. This may be larger than the vector element type,
- // so use a truncating store.
- SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
- Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
- unsigned Alignment =
- TLI.getDataLayout()->getPrefTypeAlignment(VecType);
- Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
- false, false, 0);
-
- // Load the Lo part from the stack slot.
- Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
- false, false, false, 0);
-
- // Increment the pointer to the other part.
- unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
- StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
- DAG.getConstant(IncrementSize, StackPtr.getValueType()));
-
- // Load the Hi part from the stack slot.
- Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
- false, false, false, MinAlign(Alignment, IncrementSize));
-}
-
-void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- EVT LoVT, HiVT;
- SDLoc dl(N);
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
- Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
- Hi = DAG.getUNDEF(HiVT);
-}
-
-void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
- SDValue &Hi) {
- assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
- EVT LoVT, HiVT;
- SDLoc dl(LD);
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
-
- ISD::LoadExtType ExtType = LD->getExtensionType();
- SDValue Ch = LD->getChain();
- SDValue Ptr = LD->getBasePtr();
- SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
- EVT MemoryVT = LD->getMemoryVT();
- unsigned Alignment = LD->getOriginalAlignment();
- bool isVolatile = LD->isVolatile();
- bool isNonTemporal = LD->isNonTemporal();
- bool isInvariant = LD->isInvariant();
- AAMDNodes AAInfo = LD->getAAInfo();
-
- EVT LoMemVT, HiMemVT;
- std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
-
- Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
- LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
- isInvariant, Alignment, AAInfo);
-
- unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
- Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
- DAG.getConstant(IncrementSize, Ptr.getValueType()));
- Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
- LD->getPointerInfo().getWithOffset(IncrementSize),
- HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
- AAInfo);
-
- // Build a factor node to remember that this load is independent of the
- // other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
- Hi.getValue(1));
-
- // Legalized the chain result - switch anything that used the old chain to
- // use the new one.
- ReplaceValueWith(SDValue(LD, 1), Ch);
-}
-
-void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
- assert(N->getValueType(0).isVector() &&
- N->getOperand(0).getValueType().isVector() &&
- "Operand types must be vectors");
-
- EVT LoVT, HiVT;
- SDLoc DL(N);
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
-
- // Split the input.
- SDValue LL, LH, RL, RH;
- std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
- std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
-
- Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
- Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
-}
-
-void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- // Get the dest types - they may not match the input types, e.g. int_to_fp.
- EVT LoVT, HiVT;
- SDLoc dl(N);
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
-
- // If the input also splits, handle it directly for a compile time speedup.
- // Otherwise split it by hand.
- EVT InVT = N->getOperand(0).getValueType();
- if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
- GetSplitVector(N->getOperand(0), Lo, Hi);
- else
- std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
-
- if (N->getOpcode() == ISD::FP_ROUND) {
- Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
- Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
- } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
- SDValue DTyOpLo = DAG.getValueType(LoVT);
- SDValue DTyOpHi = DAG.getValueType(HiVT);
- SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
- SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
- SDValue RndOp = N->getOperand(3);
- SDValue SatOp = N->getOperand(4);
- ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
- Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
- CvtCode);
- Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
- CvtCode);
- } else {
- Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
- Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
- }
-}
-
-void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
- SDLoc dl(N);
- EVT SrcVT = N->getOperand(0).getValueType();
- EVT DestVT = N->getValueType(0);
- EVT LoVT, HiVT;
- std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
-
- // We can do better than a generic split operation if the extend is doing
- // more than just doubling the width of the elements and the following are
- // true:
- // - The number of vector elements is even,
- // - the source type is legal,
- // - the type of a split source is illegal,
- // - the type of an extended (by doubling element size) source is legal, and
- // - the type of that extended source when split is legal.
- //
- // This won't necessarily completely legalize the operation, but it will
- // more effectively move in the right direction and prevent falling down
- // to scalarization in many cases due to the input vector being split too
- // far.
- unsigned NumElements = SrcVT.getVectorNumElements();
- if ((NumElements & 1) == 0 &&
- SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
- LLVMContext &Ctx = *DAG.getContext();
- EVT NewSrcVT = EVT::getVectorVT(
- Ctx, EVT::getIntegerVT(
- Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
- NumElements);
- EVT SplitSrcVT =
- EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
- EVT SplitLoVT, SplitHiVT;
- std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
- if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
- TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
- DEBUG(dbgs() << "Split vector extend via incremental extend:";
- N->dump(&DAG); dbgs() << "\n");
- // Extend the source vector by one step.
- SDValue NewSrc =
- DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
- // Get the low and high halves of the new, extended one step, vector.
- std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
- // Extend those vector halves the rest of the way.
- Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
- Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
- return;
- }
- }
- // Fall back to the generic unary operator splitting otherwise.
- SplitVecRes_UnaryOp(N, Lo, Hi);
-}
-
-void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
- SDValue &Lo, SDValue &Hi) {
- // The low and high parts of the original input give four input vectors.
- SDValue Inputs[4];
- SDLoc dl(N);
- GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
- GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
- EVT NewVT = Inputs[0].getValueType();
- unsigned NewElts = NewVT.getVectorNumElements();
-
- // If Lo or Hi uses elements from at most two of the four input vectors, then
- // express it as a vector shuffle of those two inputs. Otherwise extract the
- // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
- SmallVector<int, 16> Ops;
- for (unsigned High = 0; High < 2; ++High) {
- SDValue &Output = High ? Hi : Lo;
-
- // Build a shuffle mask for the output, discovering on the fly which
- // input vectors to use as shuffle operands (recorded in InputUsed).
- // If building a suitable shuffle vector proves too hard, then bail
- // out with useBuildVector set.
- unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
- unsigned FirstMaskIdx = High * NewElts;
- bool useBuildVector = false;
- for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
- // The mask element. This indexes into the input.
- int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
-
- // The input vector this mask element indexes into.
- unsigned Input = (unsigned)Idx / NewElts;
-
- if (Input >= array_lengthof(Inputs)) {
- // The mask element does not index into any input vector.
- Ops.push_back(-1);
- continue;
- }
-
- // Turn the index into an offset from the start of the input vector.
- Idx -= Input * NewElts;
-
- // Find or create a shuffle vector operand to hold this input.
- unsigned OpNo;
- for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
- if (InputUsed[OpNo] == Input) {
- // This input vector is already an operand.
- break;
- } else if (InputUsed[OpNo] == -1U) {
- // Create a new operand for this input vector.
- InputUsed[OpNo] = Input;
- break;
- }
- }
-
- if (OpNo >= array_lengthof(InputUsed)) {
- // More than two input vectors used! Give up on trying to create a
- // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
- useBuildVector = true;
- break;
- }
-
- // Add the mask index for the new shuffle vector.
- Ops.push_back(Idx + OpNo * NewElts);
- }
-
- if (useBuildVector) {
- EVT EltVT = NewVT.getVectorElementType();
- SmallVector<SDValue, 16> SVOps;
-
- // Extract the input elements by hand.
- for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
- // The mask element. This indexes into the input.
- int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
-
- // The input vector this mask element indexes into.
- unsigned Input = (unsigned)Idx / NewElts;
-
- if (Input >= array_lengthof(Inputs)) {
- // The mask element is "undef" or indexes off the end of the input.
- SVOps.push_back(DAG.getUNDEF(EltVT));
- continue;
- }
-
- // Turn the index into an offset from the start of the input vector.
- Idx -= Input * NewElts;
-
- // Extract the vector element by hand.
- SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
- Inputs[Input], DAG.getConstant(Idx,
- TLI.getVectorIdxTy())));
- }
-
- // Construct the Lo/Hi output using a BUILD_VECTOR.
- Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
- } else if (InputUsed[0] == -1U) {
- // No input vectors were used! The result is undefined.
- Output = DAG.getUNDEF(NewVT);
- } else {
- SDValue Op0 = Inputs[InputUsed[0]];
- // If only one input was used, use an undefined vector for the other.
- SDValue Op1 = InputUsed[1] == -1U ?
- DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
- // At least one input vector was used. Create a new shuffle vector.
- Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
- }
-
- Ops.clear();
- }
-}
-
-
-//===----------------------------------------------------------------------===//
-// Operand Vector Splitting
-//===----------------------------------------------------------------------===//
-
-/// SplitVectorOperand - This method is called when the specified operand of the
-/// specified node is found to need vector splitting. At this point, all of the
-/// result types of the node are known to be legal, but other operands of the
-/// node may need legalization as well as the specified one.
-bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
- DEBUG(dbgs() << "Split node operand: ";
- N->dump(&DAG);
- dbgs() << "\n");
- SDValue Res = SDValue();
-
- // See if the target wants to custom split this node.
- if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
- return false;
-
- if (!Res.getNode()) {
- switch (N->getOpcode()) {
- default:
-#ifndef NDEBUG
- dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n";
-#endif
- report_fatal_error("Do not know how to split this operator's "
- "operand!\n");
-
- case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
- case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
- case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
- case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
- case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
- case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break;
- case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
- case ISD::STORE:
- Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
- break;
- case ISD::VSELECT:
- Res = SplitVecOp_VSELECT(N, OpNo);
- break;
- case ISD::CTTZ:
- case ISD::CTLZ:
- case ISD::CTPOP:
- case ISD::FP_EXTEND:
- case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT:
- case ISD::SINT_TO_FP:
- case ISD::UINT_TO_FP:
- case ISD::FTRUNC:
- case ISD::SIGN_EXTEND:
- case ISD::ZERO_EXTEND:
- case ISD::ANY_EXTEND:
- Res = SplitVecOp_UnaryOp(N);
- break;
- }
- }
-
- // If the result is null, the sub-method took care of registering results etc.
- if (!Res.getNode()) return false;
-
- // If the result is N, the sub-method updated N in place. Tell the legalizer
- // core about this.
- if (Res.getNode() == N)
- return true;
-
- assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
- "Invalid operand expansion");
-
- ReplaceValueWith(SDValue(N, 0), Res);
- return false;
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
- // The only possibility for an illegal operand is the mask, since result type
- // legalization would have handled this node already otherwise.
- assert(OpNo == 0 && "Illegal operand must be mask");
-
- SDValue Mask = N->getOperand(0);
- SDValue Src0 = N->getOperand(1);
- SDValue Src1 = N->getOperand(2);
- EVT Src0VT = Src0.getValueType();
- SDLoc DL(N);
- assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
-
- SDValue Lo, Hi;
- GetSplitVector(N->getOperand(0), Lo, Hi);
- assert(Lo.getValueType() == Hi.getValueType() &&
- "Lo and Hi have differing types");
-
- EVT LoOpVT, HiOpVT;
- std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
- assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
-
- SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
- std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
- std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
- std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
-
- SDValue LoSelect =
- DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
- SDValue HiSelect =
- DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
-
- return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
- // The result has a legal vector type, but the input needs splitting.
- EVT ResVT = N->getValueType(0);
- SDValue Lo, Hi;
- SDLoc dl(N);
- GetSplitVector(N->getOperand(0), Lo, Hi);
- EVT InVT = Lo.getValueType();
-
- EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
- InVT.getVectorNumElements());
-
- Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
- Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
-
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
- // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
- // end up being split all the way down to individual components. Convert the
- // split pieces into integers and reassemble.
- SDValue Lo, Hi;
- GetSplitVector(N->getOperand(0), Lo, Hi);
- Lo = BitConvertToInteger(Lo);
- Hi = BitConvertToInteger(Hi);
-
- if (TLI.isBigEndian())
- std::swap(Lo, Hi);
-
- return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
- JoinIntegers(Lo, Hi));
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
- // We know that the extracted result type is legal.
- EVT SubVT = N->getValueType(0);
- SDValue Idx = N->getOperand(1);
- SDLoc dl(N);
- SDValue Lo, Hi;
- GetSplitVector(N->getOperand(0), Lo, Hi);
-
- uint64_t LoElts = Lo.getValueType().getVectorNumElements();
- uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
-
- if (IdxVal < LoElts) {
- assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
- "Extracted subvector crosses vector split!");
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
- } else {
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
- DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
- }
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
- SDValue Vec = N->getOperand(0);
- SDValue Idx = N->getOperand(1);
- EVT VecVT = Vec.getValueType();
-
- if (isa<ConstantSDNode>(Idx)) {
- uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
- assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
-
- SDValue Lo, Hi;
- GetSplitVector(Vec, Lo, Hi);
-
- uint64_t LoElts = Lo.getValueType().getVectorNumElements();
-
- if (IdxVal < LoElts)
- return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
- return SDValue(DAG.UpdateNodeOperands(N, Hi,
- DAG.getConstant(IdxVal - LoElts,
- Idx.getValueType())), 0);
- }
-
- // See if the target wants to custom expand this node.
- if (CustomLowerNode(N, N->getValueType(0), true))
- return SDValue();
-
- // Store the vector to the stack.
- EVT EltVT = VecVT.getVectorElementType();
- SDLoc dl(N);
- SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
- SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
- MachinePointerInfo(), false, false, 0);
-
- // Load back the required element.
- StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
- return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
- MachinePointerInfo(), EltVT, false, false, false, 0);
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
- assert(N->isUnindexed() && "Indexed store of vector?");
- assert(OpNo == 1 && "Can only split the stored value");
- SDLoc DL(N);
-
- bool isTruncating = N->isTruncatingStore();
- SDValue Ch = N->getChain();
- SDValue Ptr = N->getBasePtr();
- EVT MemoryVT = N->getMemoryVT();
- unsigned Alignment = N->getOriginalAlignment();
- bool isVol = N->isVolatile();
- bool isNT = N->isNonTemporal();
- AAMDNodes AAInfo = N->getAAInfo();
- SDValue Lo, Hi;
- GetSplitVector(N->getOperand(1), Lo, Hi);
-
- EVT LoMemVT, HiMemVT;
- std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
-
- unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
-
- if (isTruncating)
- Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
- LoMemVT, isVol, isNT, Alignment, AAInfo);
- else
- Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
- isVol, isNT, Alignment, AAInfo);
-
- // Increment the pointer to the other half.
- Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
- DAG.getConstant(IncrementSize, Ptr.getValueType()));
-
- if (isTruncating)
- Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
- N->getPointerInfo().getWithOffset(IncrementSize),
- HiMemVT, isVol, isNT, Alignment, AAInfo);
- else
- Hi = DAG.getStore(Ch, DL, Hi, Ptr,
- N->getPointerInfo().getWithOffset(IncrementSize),
- isVol, isNT, Alignment, AAInfo);
-
- return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
- SDLoc DL(N);
-
- // The input operands all must have the same type, and we know the result
- // type is valid. Convert this to a buildvector which extracts all the
- // input elements.
- // TODO: If the input elements are power-two vectors, we could convert this to
- // a new CONCAT_VECTORS node with elements that are half-wide.
- SmallVector<SDValue, 32> Elts;
- EVT EltVT = N->getValueType(0).getVectorElementType();
- for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
- SDValue Op = N->getOperand(op);
- for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
- i != e; ++i) {
- Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
- Op, DAG.getConstant(i, TLI.getVectorIdxTy())));
-
- }
- }
-
- return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) {
- // The result type is legal, but the input type is illegal. If splitting
- // ends up with the result type of each half still being legal, just
- // do that. If, however, that would result in an illegal result type,
- // we can try to get more clever with power-two vectors. Specifically,
- // split the input type, but also widen the result element size, then
- // concatenate the halves and truncate again. For example, consider a target
- // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
- // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
- // %inlo = v4i32 extract_subvector %in, 0
- // %inhi = v4i32 extract_subvector %in, 4
- // %lo16 = v4i16 trunc v4i32 %inlo
- // %hi16 = v4i16 trunc v4i32 %inhi
- // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
- // %res = v8i8 trunc v8i16 %in16
- //
- // Without this transform, the original truncate would end up being
- // scalarized, which is pretty much always a last resort.
- SDValue InVec = N->getOperand(0);
- EVT InVT = InVec->getValueType(0);
- EVT OutVT = N->getValueType(0);
- unsigned NumElements = OutVT.getVectorNumElements();
- // Widening should have already made sure this is a power-two vector
- // if we're trying to split it at all. assert() that's true, just in case.
- assert(!(NumElements & 1) && "Splitting vector, but not in half!");
-
- unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
- unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
-
- // If the input elements are only 1/2 the width of the result elements,
- // just use the normal splitting. Our trick only work if there's room
- // to split more than once.
- if (InElementSize <= OutElementSize * 2)
- return SplitVecOp_UnaryOp(N);
- SDLoc DL(N);
-
- // Extract the halves of the input via extract_subvector.
- SDValue InLoVec, InHiVec;
- std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
- // Truncate them to 1/2 the element size.
- EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
- EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
- NumElements/2);
- SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec);
- SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec);
- // Concatenate them to get the full intermediate truncation result.
- EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
- SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
- HalfHi);
- // Now finish up by truncating all the way down to the original result
- // type. This should normally be something that ends up being legal directly,
- // but in theory if a target has very wide vectors and an annoyingly
- // restricted set of legal types, this split can chain to build things up.
- return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
-}
-
-SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
- assert(N->getValueType(0).isVector() &&
- N->getOperand(0).getValueType().isVector() &&
- "Operand types must be vectors");
- // The result has a legal vector type, but the input needs splitting.
- SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
- SDLoc DL(N);
- GetSplitVector(N->getOperand(0), Lo0, Hi0);
- GetSplitVector(N->getOperand(1), Lo1, Hi1);
- unsigned PartElements = Lo0.getValueType().getVectorNumElements();
- EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
- EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
-
- LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
- HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
- SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
- return PromoteTargetBoolean(Con, N->getValueType(0));
-}
-
-
-SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
- // The result has a legal vector type, but the input needs splitting.
- EVT ResVT = N->getValueType(0);
- SDValue Lo, Hi;
- SDLoc DL(N);
- GetSplitVector(N->getOperand(0), Lo, Hi);
- EVT InVT = Lo.getValueType();
-
- EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
- InVT.getVectorNumElements());
-
- Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
- Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
-
- return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
-}
-
-
-
-//===----------------------------------------------------------------------===//
-// Result Vector Widening
-//===----------------------------------------------------------------------===//
-
-void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
- DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n");
-
- // See if the target wants to custom widen this node.
- if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
- return;
-
- SDValue Res = SDValue();
- switch (N->getOpcode()) {
- default:
-#ifndef NDEBUG
- dbgs() << "WidenVectorResult #" << ResNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n";
-#endif
- llvm_unreachable("Do not know how to widen the result of this operator!");
-
- case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
- case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
- case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
- case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
- case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
- case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
- case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
- case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
- case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
- case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
- case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
- case ISD::VSELECT:
- case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
- case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
- case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
- case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
- case ISD::VECTOR_SHUFFLE:
- Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
- break;
-
- case ISD::ADD:
- case ISD::AND:
- case ISD::MUL:
- case ISD::MULHS:
- case ISD::MULHU:
- case ISD::OR:
- case ISD::SUB:
- case ISD::XOR:
- case ISD::FMINNUM:
- case ISD::FMAXNUM:
- Res = WidenVecRes_Binary(N);
- break;
-
- case ISD::FADD:
- case ISD::FCOPYSIGN:
- case ISD::FMUL:
- case ISD::FPOW:
- case ISD::FSUB:
- case ISD::FDIV:
- case ISD::FREM:
- case ISD::SDIV:
- case ISD::UDIV:
- case ISD::SREM:
- case ISD::UREM:
- Res = WidenVecRes_BinaryCanTrap(N);
- break;
-
- case ISD::FPOWI:
- Res = WidenVecRes_POWI(N);
- break;
-
- case ISD::SHL:
- case ISD::SRA:
- case ISD::SRL:
- Res = WidenVecRes_Shift(N);
- break;
-
- case ISD::ANY_EXTEND:
- case ISD::FP_EXTEND:
- case ISD::FP_ROUND:
- case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT:
- case ISD::SIGN_EXTEND:
- case ISD::SINT_TO_FP:
- case ISD::TRUNCATE:
- case ISD::UINT_TO_FP:
- case ISD::ZERO_EXTEND:
- Res = WidenVecRes_Convert(N);
- break;
-
- case ISD::BSWAP:
- case ISD::CTLZ:
- case ISD::CTPOP:
- case ISD::CTTZ:
- case ISD::FABS:
- case ISD::FCEIL:
- case ISD::FCOS:
- case ISD::FEXP:
- case ISD::FEXP2:
- case ISD::FFLOOR:
- case ISD::FLOG:
- case ISD::FLOG10:
- case ISD::FLOG2:
- case ISD::FNEARBYINT:
- case ISD::FNEG:
- case ISD::FRINT:
- case ISD::FROUND:
- case ISD::FSIN:
- case ISD::FSQRT:
- case ISD::FTRUNC:
- Res = WidenVecRes_Unary(N);
- break;
- case ISD::FMA:
- Res = WidenVecRes_Ternary(N);
- break;
- }
-
- // If Res is null, the sub-method took care of registering the result.
- if (Res.getNode())
- SetWidenedVector(SDValue(N, ResNo), Res);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
- // Ternary op widening.
- SDLoc dl(N);
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- SDValue InOp1 = GetWidenedVector(N->getOperand(0));
- SDValue InOp2 = GetWidenedVector(N->getOperand(1));
- SDValue InOp3 = GetWidenedVector(N->getOperand(2));
- return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
- // Binary op widening.
- SDLoc dl(N);
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- SDValue InOp1 = GetWidenedVector(N->getOperand(0));
- SDValue InOp2 = GetWidenedVector(N->getOperand(1));
- return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
- // Binary op widening for operations that can trap.
- unsigned Opcode = N->getOpcode();
- SDLoc dl(N);
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- EVT WidenEltVT = WidenVT.getVectorElementType();
- EVT VT = WidenVT;
- unsigned NumElts = VT.getVectorNumElements();
- while (!TLI.isTypeLegal(VT) && NumElts != 1) {
- NumElts = NumElts / 2;
- VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
- }
-
- if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
- // Operation doesn't trap so just widen as normal.
- SDValue InOp1 = GetWidenedVector(N->getOperand(0));
- SDValue InOp2 = GetWidenedVector(N->getOperand(1));
- return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
- }
-
- // No legal vector version so unroll the vector operation and then widen.
- if (NumElts == 1)
- return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
-
- // Since the operation can trap, apply operation on the original vector.
- EVT MaxVT = VT;
- SDValue InOp1 = GetWidenedVector(N->getOperand(0));
- SDValue InOp2 = GetWidenedVector(N->getOperand(1));
- unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
-
- SmallVector<SDValue, 16> ConcatOps(CurNumElts);
- unsigned ConcatEnd = 0; // Current ConcatOps index.
- int Idx = 0; // Current Idx into input vectors.
-
- // NumElts := greatest legal vector size (at most WidenVT)
- // while (orig. vector has unhandled elements) {
- // take munches of size NumElts from the beginning and add to ConcatOps
- // NumElts := next smaller supported vector size or 1
- // }
- while (CurNumElts != 0) {
- while (CurNumElts >= NumElts) {
- SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
- DAG.getConstant(Idx, TLI.getVectorIdxTy()));
- SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
- DAG.getConstant(Idx, TLI.getVectorIdxTy()));
- ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
- Idx += NumElts;
- CurNumElts -= NumElts;
- }
- do {
- NumElts = NumElts / 2;
- VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
- } while (!TLI.isTypeLegal(VT) && NumElts != 1);
-
- if (NumElts == 1) {
- for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
- SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
- InOp1, DAG.getConstant(Idx,
- TLI.getVectorIdxTy()));
- SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
- InOp2, DAG.getConstant(Idx,
- TLI.getVectorIdxTy()));
- ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
- EOp1, EOp2);
- }
- CurNumElts = 0;
- }
- }
-
- // Check to see if we have a single operation with the widen type.
- if (ConcatEnd == 1) {
- VT = ConcatOps[0].getValueType();
- if (VT == WidenVT)
- return ConcatOps[0];
- }
-
- // while (Some element of ConcatOps is not of type MaxVT) {
- // From the end of ConcatOps, collect elements of the same type and put
- // them into an op of the next larger supported type
- // }
- while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
- Idx = ConcatEnd - 1;
- VT = ConcatOps[Idx--].getValueType();
- while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
- Idx--;
-
- int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
- EVT NextVT;
- do {
- NextSize *= 2;
- NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
- } while (!TLI.isTypeLegal(NextVT));
-
- if (!VT.isVector()) {
- // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
- SDValue VecOp = DAG.getUNDEF(NextVT);
- unsigned NumToInsert = ConcatEnd - Idx - 1;
- for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
- VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
- ConcatOps[OpIdx], DAG.getConstant(i,
- TLI.getVectorIdxTy()));
- }
- ConcatOps[Idx+1] = VecOp;
- ConcatEnd = Idx + 2;
- } else {
- // Vector type, create a CONCAT_VECTORS of type NextVT
- SDValue undefVec = DAG.getUNDEF(VT);
- unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
- SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
- unsigned RealVals = ConcatEnd - Idx - 1;
- unsigned SubConcatEnd = 0;
- unsigned SubConcatIdx = Idx + 1;
- while (SubConcatEnd < RealVals)
- SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
- while (SubConcatEnd < OpsToConcat)
- SubConcatOps[SubConcatEnd++] = undefVec;
- ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
- NextVT, SubConcatOps);
- ConcatEnd = SubConcatIdx + 1;
- }
- }
-
- // Check to see if we have a single operation with the widen type.
- if (ConcatEnd == 1) {
- VT = ConcatOps[0].getValueType();
- if (VT == WidenVT)
- return ConcatOps[0];
- }
-
- // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
- unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
- if (NumOps != ConcatEnd ) {
- SDValue UndefVal = DAG.getUNDEF(MaxVT);
- for (unsigned j = ConcatEnd; j < NumOps; ++j)
- ConcatOps[j] = UndefVal;
- }
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
- makeArrayRef(ConcatOps.data(), NumOps));
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
- SDValue InOp = N->getOperand(0);
- SDLoc DL(N);
-
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
-
- EVT InVT = InOp.getValueType();
- EVT InEltVT = InVT.getVectorElementType();
- EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
-
- unsigned Opcode = N->getOpcode();
- unsigned InVTNumElts = InVT.getVectorNumElements();
-
- if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
- InOp = GetWidenedVector(N->getOperand(0));
- InVT = InOp.getValueType();
- InVTNumElts = InVT.getVectorNumElements();
- if (InVTNumElts == WidenNumElts) {
- if (N->getNumOperands() == 1)
- return DAG.getNode(Opcode, DL, WidenVT, InOp);
- return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
- }
- }
-
- if (TLI.isTypeLegal(InWidenVT)) {
- // Because the result and the input are different vector types, widening
- // the result could create a legal type but widening the input might make
- // it an illegal type that might lead to repeatedly splitting the input
- // and then widening it. To avoid this, we widen the input only if
- // it results in a legal type.
- if (WidenNumElts % InVTNumElts == 0) {
- // Widen the input and call convert on the widened input vector.
- unsigned NumConcat = WidenNumElts/InVTNumElts;
- SmallVector<SDValue, 16> Ops(NumConcat);
- Ops[0] = InOp;
- SDValue UndefVal = DAG.getUNDEF(InVT);
- for (unsigned i = 1; i != NumConcat; ++i)
- Ops[i] = UndefVal;
- SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
- if (N->getNumOperands() == 1)
- return DAG.getNode(Opcode, DL, WidenVT, InVec);
- return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
- }
-
- if (InVTNumElts % WidenNumElts == 0) {
- SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
- InOp, DAG.getConstant(0,
- TLI.getVectorIdxTy()));
- // Extract the input and convert the shorten input vector.
- if (N->getNumOperands() == 1)
- return DAG.getNode(Opcode, DL, WidenVT, InVal);
- return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
- }
- }
-
- // Otherwise unroll into some nasty scalar code and rebuild the vector.
- SmallVector<SDValue, 16> Ops(WidenNumElts);
- EVT EltVT = WidenVT.getVectorElementType();
- unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
- unsigned i;
- for (i=0; i < MinElts; ++i) {
- SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
- DAG.getConstant(i, TLI.getVectorIdxTy()));
- if (N->getNumOperands() == 1)
- Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
- else
- Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
- }
-
- SDValue UndefVal = DAG.getUNDEF(EltVT);
- for (; i < WidenNumElts; ++i)
- Ops[i] = UndefVal;
-
- return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- SDValue InOp = GetWidenedVector(N->getOperand(0));
- SDValue ShOp = N->getOperand(1);
- return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- SDValue InOp = GetWidenedVector(N->getOperand(0));
- SDValue ShOp = N->getOperand(1);
-
- EVT ShVT = ShOp.getValueType();
- if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
- ShOp = GetWidenedVector(ShOp);
- ShVT = ShOp.getValueType();
- }
- EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
- ShVT.getVectorElementType(),
- WidenVT.getVectorNumElements());
- if (ShVT != ShWidenVT)
- ShOp = ModifyToType(ShOp, ShWidenVT);
-
- return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
- // Unary op widening.
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- SDValue InOp = GetWidenedVector(N->getOperand(0));
- return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
- cast<VTSDNode>(N->getOperand(1))->getVT()
- .getVectorElementType(),
- WidenVT.getVectorNumElements());
- SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
- return DAG.getNode(N->getOpcode(), SDLoc(N),
- WidenVT, WidenLHS, DAG.getValueType(ExtVT));
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
- SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
- return GetWidenedVector(WidenVec);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
- SDValue InOp = N->getOperand(0);
- EVT InVT = InOp.getValueType();
- EVT VT = N->getValueType(0);
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- SDLoc dl(N);
-
- switch (getTypeAction(InVT)) {
- case TargetLowering::TypeLegal:
- break;
- case TargetLowering::TypePromoteInteger:
- // If the incoming type is a vector that is being promoted, then
- // we know that the elements are arranged differently and that we
- // must perform the conversion using a stack slot.
- if (InVT.isVector())
- break;
-
- // If the InOp is promoted to the same size, convert it. Otherwise,
- // fall out of the switch and widen the promoted input.
- InOp = GetPromotedInteger(InOp);
- InVT = InOp.getValueType();
- if (WidenVT.bitsEq(InVT))
- return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
- break;
- case TargetLowering::TypeSoftenFloat:
- case TargetLowering::TypeExpandInteger:
- case TargetLowering::TypeExpandFloat:
- case TargetLowering::TypeScalarizeVector:
- case TargetLowering::TypeSplitVector:
- break;
- case TargetLowering::TypeWidenVector:
- // If the InOp is widened to the same size, convert it. Otherwise, fall
- // out of the switch and widen the widened input.
- InOp = GetWidenedVector(InOp);
- InVT = InOp.getValueType();
- if (WidenVT.bitsEq(InVT))
- // The input widens to the same size. Convert to the widen value.
- return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
- break;
- }
-
- unsigned WidenSize = WidenVT.getSizeInBits();
- unsigned InSize = InVT.getSizeInBits();
- // x86mmx is not an acceptable vector element type, so don't try.
- if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
- // Determine new input vector type. The new input vector type will use
- // the same element type (if its a vector) or use the input type as a
- // vector. It is the same size as the type to widen to.
- EVT NewInVT;
- unsigned NewNumElts = WidenSize / InSize;
- if (InVT.isVector()) {
- EVT InEltVT = InVT.getVectorElementType();
- NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
- WidenSize / InEltVT.getSizeInBits());
- } else {
- NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
- }
-
- if (TLI.isTypeLegal(NewInVT)) {
- // Because the result and the input are different vector types, widening
- // the result could create a legal type but widening the input might make
- // it an illegal type that might lead to repeatedly splitting the input
- // and then widening it. To avoid this, we widen the input only if
- // it results in a legal type.
- SmallVector<SDValue, 16> Ops(NewNumElts);
- SDValue UndefVal = DAG.getUNDEF(InVT);
- Ops[0] = InOp;
- for (unsigned i = 1; i < NewNumElts; ++i)
- Ops[i] = UndefVal;
-
- SDValue NewVec;
- if (InVT.isVector())
- NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
- else
- NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
- return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
- }
- }
-
- return CreateStackStoreLoad(InOp, WidenVT);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
- SDLoc dl(N);
- // Build a vector with undefined for the new nodes.
- EVT VT = N->getValueType(0);
-
- // Integer BUILD_VECTOR operands may be larger than the node's vector element
- // type. The UNDEFs need to have the same type as the existing operands.
- EVT EltVT = N->getOperand(0).getValueType();
- unsigned NumElts = VT.getVectorNumElements();
-
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
-
- SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
- assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
- NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
-
- return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
- EVT InVT = N->getOperand(0).getValueType();
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- SDLoc dl(N);
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
- unsigned NumInElts = InVT.getVectorNumElements();
- unsigned NumOperands = N->getNumOperands();
-
- bool InputWidened = false; // Indicates we need to widen the input.
- if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
- if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
- // Add undef vectors to widen to correct length.
- unsigned NumConcat = WidenVT.getVectorNumElements() /
- InVT.getVectorNumElements();
- SDValue UndefVal = DAG.getUNDEF(InVT);
- SmallVector<SDValue, 16> Ops(NumConcat);
- for (unsigned i=0; i < NumOperands; ++i)
- Ops[i] = N->getOperand(i);
- for (unsigned i = NumOperands; i != NumConcat; ++i)
- Ops[i] = UndefVal;
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
- }
- } else {
- InputWidened = true;
- if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
- // The inputs and the result are widen to the same value.
- unsigned i;
- for (i=1; i < NumOperands; ++i)
- if (N->getOperand(i).getOpcode() != ISD::UNDEF)
- break;
-
- if (i == NumOperands)
- // Everything but the first operand is an UNDEF so just return the
- // widened first operand.
- return GetWidenedVector(N->getOperand(0));
-
- if (NumOperands == 2) {
- // Replace concat of two operands with a shuffle.
- SmallVector<int, 16> MaskOps(WidenNumElts, -1);
- for (unsigned i = 0; i < NumInElts; ++i) {
- MaskOps[i] = i;
- MaskOps[i + NumInElts] = i + WidenNumElts;
- }
- return DAG.getVectorShuffle(WidenVT, dl,
- GetWidenedVector(N->getOperand(0)),
- GetWidenedVector(N->getOperand(1)),
- &MaskOps[0]);
- }
- }
- }
-
- // Fall back to use extracts and build vector.
- EVT EltVT = WidenVT.getVectorElementType();
- SmallVector<SDValue, 16> Ops(WidenNumElts);
- unsigned Idx = 0;
- for (unsigned i=0; i < NumOperands; ++i) {
- SDValue InOp = N->getOperand(i);
- if (InputWidened)
- InOp = GetWidenedVector(InOp);
- for (unsigned j=0; j < NumInElts; ++j)
- Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
- DAG.getConstant(j, TLI.getVectorIdxTy()));
- }
- SDValue UndefVal = DAG.getUNDEF(EltVT);
- for (; Idx < WidenNumElts; ++Idx)
- Ops[Idx] = UndefVal;
- return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
- SDLoc dl(N);
- SDValue InOp = N->getOperand(0);
- SDValue RndOp = N->getOperand(3);
- SDValue SatOp = N->getOperand(4);
-
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
-
- EVT InVT = InOp.getValueType();
- EVT InEltVT = InVT.getVectorElementType();
- EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
-
- SDValue DTyOp = DAG.getValueType(WidenVT);
- SDValue STyOp = DAG.getValueType(InWidenVT);
- ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
-
- unsigned InVTNumElts = InVT.getVectorNumElements();
- if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
- InOp = GetWidenedVector(InOp);
- InVT = InOp.getValueType();
- InVTNumElts = InVT.getVectorNumElements();
- if (InVTNumElts == WidenNumElts)
- return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
- SatOp, CvtCode);
- }
-
- if (TLI.isTypeLegal(InWidenVT)) {
- // Because the result and the input are different vector types, widening
- // the result could create a legal type but widening the input might make
- // it an illegal type that might lead to repeatedly splitting the input
- // and then widening it. To avoid this, we widen the input only if
- // it results in a legal type.
- if (WidenNumElts % InVTNumElts == 0) {
- // Widen the input and call convert on the widened input vector.
- unsigned NumConcat = WidenNumElts/InVTNumElts;
- SmallVector<SDValue, 16> Ops(NumConcat);
- Ops[0] = InOp;
- SDValue UndefVal = DAG.getUNDEF(InVT);
- for (unsigned i = 1; i != NumConcat; ++i)
- Ops[i] = UndefVal;
-
- InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
- return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
- SatOp, CvtCode);
- }
-
- if (InVTNumElts % WidenNumElts == 0) {
- // Extract the input and convert the shorten input vector.
- InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
- SatOp, CvtCode);
- }
- }
-
- // Otherwise unroll into some nasty scalar code and rebuild the vector.
- SmallVector<SDValue, 16> Ops(WidenNumElts);
- EVT EltVT = WidenVT.getVectorElementType();
- DTyOp = DAG.getValueType(EltVT);
- STyOp = DAG.getValueType(InEltVT);
-
- unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
- unsigned i;
- for (i=0; i < MinElts; ++i) {
- SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
- DAG.getConstant(i, TLI.getVectorIdxTy()));
- Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
- SatOp, CvtCode);
- }
-
- SDValue UndefVal = DAG.getUNDEF(EltVT);
- for (; i < WidenNumElts; ++i)
- Ops[i] = UndefVal;
-
- return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
- EVT VT = N->getValueType(0);
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
- SDValue InOp = N->getOperand(0);
- SDValue Idx = N->getOperand(1);
- SDLoc dl(N);
-
- if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
- InOp = GetWidenedVector(InOp);
-
- EVT InVT = InOp.getValueType();
-
- // Check if we can just return the input vector after widening.
- uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
- if (IdxVal == 0 && InVT == WidenVT)
- return InOp;
-
- // Check if we can extract from the vector.
- unsigned InNumElts = InVT.getVectorNumElements();
- if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
-
- // We could try widening the input to the right length but for now, extract
- // the original elements, fill the rest with undefs and build a vector.
- SmallVector<SDValue, 16> Ops(WidenNumElts);
- EVT EltVT = VT.getVectorElementType();
- unsigned NumElts = VT.getVectorNumElements();
- unsigned i;
- for (i=0; i < NumElts; ++i)
- Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
- DAG.getConstant(IdxVal+i, TLI.getVectorIdxTy()));
-
- SDValue UndefVal = DAG.getUNDEF(EltVT);
- for (; i < WidenNumElts; ++i)
- Ops[i] = UndefVal;
- return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
- SDValue InOp = GetWidenedVector(N->getOperand(0));
- return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
- InOp.getValueType(), InOp,
- N->getOperand(1), N->getOperand(2));
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
- LoadSDNode *LD = cast<LoadSDNode>(N);
- ISD::LoadExtType ExtType = LD->getExtensionType();
-
- SDValue Result;
- SmallVector<SDValue, 16> LdChain; // Chain for the series of load
- if (ExtType != ISD::NON_EXTLOAD)
- Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
- else
- Result = GenWidenVectorLoads(LdChain, LD);
-
- // If we generate a single load, we can use that for the chain. Otherwise,
- // build a factor node to remember the multiple loads are independent and
- // chain to that.
- SDValue NewChain;
- if (LdChain.size() == 1)
- NewChain = LdChain[0];
- else
- NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
-
- // Modified the chain - switch anything that used the old chain to use
- // the new one.
- ReplaceValueWith(SDValue(N, 1), NewChain);
-
- return Result;
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
- WidenVT, N->getOperand(0));
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
-
- SDValue Cond1 = N->getOperand(0);
- EVT CondVT = Cond1.getValueType();
- if (CondVT.isVector()) {
- EVT CondEltVT = CondVT.getVectorElementType();
- EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
- CondEltVT, WidenNumElts);
- if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
- Cond1 = GetWidenedVector(Cond1);
-
- // If we have to split the condition there is no point in widening the
- // select. This would result in an cycle of widening the select ->
- // widening the condition operand -> splitting the condition operand ->
- // splitting the select -> widening the select. Instead split this select
- // further and widen the resulting type.
- if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
- SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
- SDValue Res = ModifyToType(SplitSelect, WidenVT);
- return Res;
- }
-
- if (Cond1.getValueType() != CondWidenVT)
- Cond1 = ModifyToType(Cond1, CondWidenVT);
- }
-
- SDValue InOp1 = GetWidenedVector(N->getOperand(1));
- SDValue InOp2 = GetWidenedVector(N->getOperand(2));
- assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
- return DAG.getNode(N->getOpcode(), SDLoc(N),
- WidenVT, Cond1, InOp1, InOp2);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
- SDValue InOp1 = GetWidenedVector(N->getOperand(2));
- SDValue InOp2 = GetWidenedVector(N->getOperand(3));
- return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
- InOp1.getValueType(), N->getOperand(0),
- N->getOperand(1), InOp1, InOp2, N->getOperand(4));
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
- assert(N->getValueType(0).isVector() ==
- N->getOperand(0).getValueType().isVector() &&
- "Scalar/Vector type mismatch");
- if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
-
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- SDValue InOp1 = GetWidenedVector(N->getOperand(0));
- SDValue InOp2 = GetWidenedVector(N->getOperand(1));
- return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
- InOp1, InOp2, N->getOperand(2));
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- return DAG.getUNDEF(WidenVT);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
- EVT VT = N->getValueType(0);
- SDLoc dl(N);
-
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- unsigned NumElts = VT.getVectorNumElements();
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
-
- SDValue InOp1 = GetWidenedVector(N->getOperand(0));
- SDValue InOp2 = GetWidenedVector(N->getOperand(1));
-
- // Adjust mask based on new input vector length.
- SmallVector<int, 16> NewMask;
- for (unsigned i = 0; i != NumElts; ++i) {
- int Idx = N->getMaskElt(i);
- if (Idx < (int)NumElts)
- NewMask.push_back(Idx);
- else
- NewMask.push_back(Idx - NumElts + WidenNumElts);
- }
- for (unsigned i = NumElts; i != WidenNumElts; ++i)
- NewMask.push_back(-1);
- return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
-}
-
-SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
- assert(N->getValueType(0).isVector() &&
- N->getOperand(0).getValueType().isVector() &&
- "Operands must be vectors");
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
-
- SDValue InOp1 = N->getOperand(0);
- EVT InVT = InOp1.getValueType();
- assert(InVT.isVector() && "can not widen non-vector type");
- EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
- InVT.getVectorElementType(), WidenNumElts);
- InOp1 = GetWidenedVector(InOp1);
- SDValue InOp2 = GetWidenedVector(N->getOperand(1));
-
- // Assume that the input and output will be widen appropriately. If not,
- // we will have to unroll it at some point.
- assert(InOp1.getValueType() == WidenInVT &&
- InOp2.getValueType() == WidenInVT &&
- "Input not widened to expected type!");
- (void)WidenInVT;
- return DAG.getNode(ISD::SETCC, SDLoc(N),
- WidenVT, InOp1, InOp2, N->getOperand(2));
-}
-
-
-//===----------------------------------------------------------------------===//
-// Widen Vector Operand
-//===----------------------------------------------------------------------===//
-bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
- DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n");
- SDValue Res = SDValue();
-
- // See if the target wants to custom widen this node.
- if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
- return false;
-
- switch (N->getOpcode()) {
- default:
-#ifndef NDEBUG
- dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
- N->dump(&DAG);
- dbgs() << "\n";
-#endif
- llvm_unreachable("Do not know how to widen this operator's operand!");
-
- case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
- case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
- case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
- case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
- case ISD::STORE: Res = WidenVecOp_STORE(N); break;
- case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
-
- case ISD::ANY_EXTEND:
- case ISD::SIGN_EXTEND:
- case ISD::ZERO_EXTEND:
- Res = WidenVecOp_EXTEND(N);
- break;
-
- case ISD::FP_EXTEND:
- case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT:
- case ISD::SINT_TO_FP:
- case ISD::UINT_TO_FP:
- case ISD::TRUNCATE:
- Res = WidenVecOp_Convert(N);
- break;
- }
-
- // If Res is null, the sub-method took care of registering the result.
- if (!Res.getNode()) return false;
-
- // If the result is N, the sub-method updated N in place. Tell the legalizer
- // core about this.
- if (Res.getNode() == N)
- return true;
-
-
- assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
- "Invalid operand expansion");
-
- ReplaceValueWith(SDValue(N, 0), Res);
- return false;
-}
-
-SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
- SDLoc DL(N);
- EVT VT = N->getValueType(0);
-
- SDValue InOp = N->getOperand(0);
- // If some legalization strategy other than widening is used on the operand,
- // we can't safely assume that just extending the low lanes is the correct
- // transformation.
- if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
- return WidenVecOp_Convert(N);
- InOp = GetWidenedVector(InOp);
- assert(VT.getVectorNumElements() <
- InOp.getValueType().getVectorNumElements() &&
- "Input wasn't widened!");
-
- // We may need to further widen the operand until it has the same total
- // vector size as the result.
- EVT InVT = InOp.getValueType();
- if (InVT.getSizeInBits() != VT.getSizeInBits()) {
- EVT InEltVT = InVT.getVectorElementType();
- for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
- EVT FixedVT = (MVT::SimpleValueType)i;
- EVT FixedEltVT = FixedVT.getVectorElementType();
- if (TLI.isTypeLegal(FixedVT) &&
- FixedVT.getSizeInBits() == VT.getSizeInBits() &&
- FixedEltVT == InEltVT) {
- assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
- "Not enough elements in the fixed type for the operand!");
- assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
- "We can't have the same type as we started with!");
- if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
- InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
- DAG.getUNDEF(FixedVT), InOp,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- else
- InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- break;
- }
- }
- InVT = InOp.getValueType();
- if (InVT.getSizeInBits() != VT.getSizeInBits())
- // We couldn't find a legal vector type that was a widening of the input
- // and could be extended in-register to the result type, so we have to
- // scalarize.
- return WidenVecOp_Convert(N);
- }
-
- // Use special DAG nodes to represent the operation of extending the
- // low lanes.
- switch (N->getOpcode()) {
- default:
- llvm_unreachable("Extend legalization on on extend operation!");
- case ISD::ANY_EXTEND:
- return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
- case ISD::SIGN_EXTEND:
- return DAG.getSignExtendVectorInReg(InOp, DL, VT);
- case ISD::ZERO_EXTEND:
- return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
- }
-}
-
-SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
- // Since the result is legal and the input is illegal, it is unlikely
- // that we can fix the input to a legal type so unroll the convert
- // into some scalar code and create a nasty build vector.
- EVT VT = N->getValueType(0);
- EVT EltVT = VT.getVectorElementType();
- SDLoc dl(N);
- unsigned NumElts = VT.getVectorNumElements();
- SDValue InOp = N->getOperand(0);
- if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
- InOp = GetWidenedVector(InOp);
- EVT InVT = InOp.getValueType();
- EVT InEltVT = InVT.getVectorElementType();
-
- unsigned Opcode = N->getOpcode();
- SmallVector<SDValue, 16> Ops(NumElts);
- for (unsigned i=0; i < NumElts; ++i)
- Ops[i] = DAG.getNode(Opcode, dl, EltVT,
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
- DAG.getConstant(i, TLI.getVectorIdxTy())));
-
- return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
-}
-
-SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
- EVT VT = N->getValueType(0);
- SDValue InOp = GetWidenedVector(N->getOperand(0));
- EVT InWidenVT = InOp.getValueType();
- SDLoc dl(N);
-
- // Check if we can convert between two legal vector types and extract.
- unsigned InWidenSize = InWidenVT.getSizeInBits();
- unsigned Size = VT.getSizeInBits();
- // x86mmx is not an acceptable vector element type, so don't try.
- if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
- unsigned NewNumElts = InWidenSize / Size;
- EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
- if (TLI.isTypeLegal(NewVT)) {
- SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- }
- }
-
- return CreateStackStoreLoad(InOp, VT);
-}
-
-SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
- // If the input vector is not legal, it is likely that we will not find a
- // legal vector of the same size. Replace the concatenate vector with a
- // nasty build vector.
- EVT VT = N->getValueType(0);
- EVT EltVT = VT.getVectorElementType();
- SDLoc dl(N);
- unsigned NumElts = VT.getVectorNumElements();
- SmallVector<SDValue, 16> Ops(NumElts);
-
- EVT InVT = N->getOperand(0).getValueType();
- unsigned NumInElts = InVT.getVectorNumElements();
-
- unsigned Idx = 0;
- unsigned NumOperands = N->getNumOperands();
- for (unsigned i=0; i < NumOperands; ++i) {
- SDValue InOp = N->getOperand(i);
- if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
- InOp = GetWidenedVector(InOp);
- for (unsigned j=0; j < NumInElts; ++j)
- Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
- DAG.getConstant(j, TLI.getVectorIdxTy()));
- }
- return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
-}
-
-SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
- SDValue InOp = GetWidenedVector(N->getOperand(0));
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
- N->getValueType(0), InOp, N->getOperand(1));
-}
-
-SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
- SDValue InOp = GetWidenedVector(N->getOperand(0));
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
- N->getValueType(0), InOp, N->getOperand(1));
-}
-
-SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
- // We have to widen the value but we want only to store the original
- // vector type.
- StoreSDNode *ST = cast<StoreSDNode>(N);
-
- SmallVector<SDValue, 16> StChain;
- if (ST->isTruncatingStore())
- GenWidenVectorTruncStores(StChain, ST);
- else
- GenWidenVectorStores(StChain, ST);
-
- if (StChain.size() == 1)
- return StChain[0];
- else
- return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
-}
-
-SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
- SDValue InOp0 = GetWidenedVector(N->getOperand(0));
- SDValue InOp1 = GetWidenedVector(N->getOperand(1));
- SDLoc dl(N);
-
- // WARNING: In this code we widen the compare instruction with garbage.
- // This garbage may contain denormal floats which may be slow. Is this a real
- // concern ? Should we zero the unused lanes if this is a float compare ?
-
- // Get a new SETCC node to compare the newly widened operands.
- // Only some of the compared elements are legal.
- EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
- SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
- SVT, InOp0, InOp1, N->getOperand(2));
-
- // Extract the needed results from the result vector.
- EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
- SVT.getVectorElementType(),
- N->getValueType(0).getVectorNumElements());
- SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
- ResVT, WideSETCC, DAG.getConstant(0,
- TLI.getVectorIdxTy()));
-
- return PromoteTargetBoolean(CC, N->getValueType(0));
-}
-
-
-//===----------------------------------------------------------------------===//
-// Vector Widening Utilities
-//===----------------------------------------------------------------------===//
-
-// Utility function to find the type to chop up a widen vector for load/store
-// TLI: Target lowering used to determine legal types.
-// Width: Width left need to load/store.
-// WidenVT: The widen vector type to load to/store from
-// Align: If 0, don't allow use of a wider type
-// WidenEx: If Align is not 0, the amount additional we can load/store from.
-
-static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
- unsigned Width, EVT WidenVT,
- unsigned Align = 0, unsigned WidenEx = 0) {
- EVT WidenEltVT = WidenVT.getVectorElementType();
- unsigned WidenWidth = WidenVT.getSizeInBits();
- unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
- unsigned AlignInBits = Align*8;
-
- // If we have one element to load/store, return it.
- EVT RetVT = WidenEltVT;
- if (Width == WidenEltWidth)
- return RetVT;
-
- // See if there is larger legal integer than the element type to load/store
- unsigned VT;
- for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
- VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
- EVT MemVT((MVT::SimpleValueType) VT);
- unsigned MemVTWidth = MemVT.getSizeInBits();
- if (MemVT.getSizeInBits() <= WidenEltWidth)
- break;
- if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
- isPowerOf2_32(WidenWidth / MemVTWidth) &&
- (MemVTWidth <= Width ||
- (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
- RetVT = MemVT;
- break;
- }
- }
-
- // See if there is a larger vector type to load/store that has the same vector
- // element type and is evenly divisible with the WidenVT.
- for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
- VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
- EVT MemVT = (MVT::SimpleValueType) VT;
- unsigned MemVTWidth = MemVT.getSizeInBits();
- if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
- (WidenWidth % MemVTWidth) == 0 &&
- isPowerOf2_32(WidenWidth / MemVTWidth) &&
- (MemVTWidth <= Width ||
- (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
- if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
- return MemVT;
- }
- }
-
- return RetVT;
-}
-
-// Builds a vector type from scalar loads
-// VecTy: Resulting Vector type
-// LDOps: Load operators to build a vector type
-// [Start,End) the list of loads to use.
-static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
- SmallVectorImpl<SDValue> &LdOps,
- unsigned Start, unsigned End) {
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- SDLoc dl(LdOps[Start]);
- EVT LdTy = LdOps[Start].getValueType();
- unsigned Width = VecTy.getSizeInBits();
- unsigned NumElts = Width / LdTy.getSizeInBits();
- EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
-
- unsigned Idx = 1;
- SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
-
- for (unsigned i = Start + 1; i != End; ++i) {
- EVT NewLdTy = LdOps[i].getValueType();
- if (NewLdTy != LdTy) {
- NumElts = Width / NewLdTy.getSizeInBits();
- NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
- VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
- // Readjust position and vector position based on new load type
- Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
- LdTy = NewLdTy;
- }
- VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
- DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
- }
- return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
-}
-
-SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
- LoadSDNode *LD) {
- // The strategy assumes that we can efficiently load powers of two widths.
- // The routines chops the vector into the largest vector loads with the same
- // element type or scalar loads and then recombines it to the widen vector
- // type.
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
- unsigned WidenWidth = WidenVT.getSizeInBits();
- EVT LdVT = LD->getMemoryVT();
- SDLoc dl(LD);
- assert(LdVT.isVector() && WidenVT.isVector());
- assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
-
- // Load information
- SDValue Chain = LD->getChain();
- SDValue BasePtr = LD->getBasePtr();
- unsigned Align = LD->getAlignment();
- bool isVolatile = LD->isVolatile();
- bool isNonTemporal = LD->isNonTemporal();
- bool isInvariant = LD->isInvariant();
- AAMDNodes AAInfo = LD->getAAInfo();
-
- int LdWidth = LdVT.getSizeInBits();
- int WidthDiff = WidenWidth - LdWidth; // Difference
- unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
-
- // Find the vector type that can load from.
- EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
- int NewVTWidth = NewVT.getSizeInBits();
- SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
- isVolatile, isNonTemporal, isInvariant, Align,
- AAInfo);
- LdChain.push_back(LdOp.getValue(1));
-
- // Check if we can load the element with one instruction
- if (LdWidth <= NewVTWidth) {
- if (!NewVT.isVector()) {
- unsigned NumElts = WidenWidth / NewVTWidth;
- EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
- SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
- return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
- }
- if (NewVT == WidenVT)
- return LdOp;
-
- assert(WidenWidth % NewVTWidth == 0);
- unsigned NumConcat = WidenWidth / NewVTWidth;
- SmallVector<SDValue, 16> ConcatOps(NumConcat);
- SDValue UndefVal = DAG.getUNDEF(NewVT);
- ConcatOps[0] = LdOp;
- for (unsigned i = 1; i != NumConcat; ++i)
- ConcatOps[i] = UndefVal;
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
- }
-
- // Load vector by using multiple loads from largest vector to scalar
- SmallVector<SDValue, 16> LdOps;
- LdOps.push_back(LdOp);
-
- LdWidth -= NewVTWidth;
- unsigned Offset = 0;
-
- while (LdWidth > 0) {
- unsigned Increment = NewVTWidth / 8;
- Offset += Increment;
- BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
- DAG.getConstant(Increment, BasePtr.getValueType()));
-
- SDValue L;
- if (LdWidth < NewVTWidth) {
- // Our current type we are using is too large, find a better size
- NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
- NewVTWidth = NewVT.getSizeInBits();
- L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
- LD->getPointerInfo().getWithOffset(Offset), isVolatile,
- isNonTemporal, isInvariant, MinAlign(Align, Increment),
- AAInfo);
- LdChain.push_back(L.getValue(1));
- if (L->getValueType(0).isVector()) {
- SmallVector<SDValue, 16> Loads;
- Loads.push_back(L);
- unsigned size = L->getValueSizeInBits(0);
- while (size < LdOp->getValueSizeInBits(0)) {
- Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
- size += L->getValueSizeInBits(0);
- }
- L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
- }
- } else {
- L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
- LD->getPointerInfo().getWithOffset(Offset), isVolatile,
- isNonTemporal, isInvariant, MinAlign(Align, Increment),
- AAInfo);
- LdChain.push_back(L.getValue(1));
- }
-
- LdOps.push_back(L);
-
-
- LdWidth -= NewVTWidth;
- }
-
- // Build the vector from the loads operations
- unsigned End = LdOps.size();
- if (!LdOps[0].getValueType().isVector())
- // All the loads are scalar loads.
- return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
-
- // If the load contains vectors, build the vector using concat vector.
- // All of the vectors used to loads are power of 2 and the scalars load
- // can be combined to make a power of 2 vector.
- SmallVector<SDValue, 16> ConcatOps(End);
- int i = End - 1;
- int Idx = End;
- EVT LdTy = LdOps[i].getValueType();
- // First combine the scalar loads to a vector
- if (!LdTy.isVector()) {
- for (--i; i >= 0; --i) {
- LdTy = LdOps[i].getValueType();
- if (LdTy.isVector())
- break;
- }
- ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
- }
- ConcatOps[--Idx] = LdOps[i];
- for (--i; i >= 0; --i) {
- EVT NewLdTy = LdOps[i].getValueType();
- if (NewLdTy != LdTy) {
- // Create a larger vector
- ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
- makeArrayRef(&ConcatOps[Idx], End - Idx));
- Idx = End - 1;
- LdTy = NewLdTy;
- }
- ConcatOps[--Idx] = LdOps[i];
- }
-
- if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
- makeArrayRef(&ConcatOps[Idx], End - Idx));
-
- // We need to fill the rest with undefs to build the vector
- unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
- SmallVector<SDValue, 16> WidenOps(NumOps);
- SDValue UndefVal = DAG.getUNDEF(LdTy);
- {
- unsigned i = 0;
- for (; i != End-Idx; ++i)
- WidenOps[i] = ConcatOps[Idx+i];
- for (; i != NumOps; ++i)
- WidenOps[i] = UndefVal;
- }
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
-}
-
-SDValue
-DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
- LoadSDNode *LD,
- ISD::LoadExtType ExtType) {
- // For extension loads, it may not be more efficient to chop up the vector
- // and then extended it. Instead, we unroll the load and build a new vector.
- EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
- EVT LdVT = LD->getMemoryVT();
- SDLoc dl(LD);
- assert(LdVT.isVector() && WidenVT.isVector());
-
- // Load information
- SDValue Chain = LD->getChain();
- SDValue BasePtr = LD->getBasePtr();
- unsigned Align = LD->getAlignment();
- bool isVolatile = LD->isVolatile();
- bool isNonTemporal = LD->isNonTemporal();
- bool isInvariant = LD->isInvariant();
- AAMDNodes AAInfo = LD->getAAInfo();
-
- EVT EltVT = WidenVT.getVectorElementType();
- EVT LdEltVT = LdVT.getVectorElementType();
- unsigned NumElts = LdVT.getVectorNumElements();
-
- // Load each element and widen
- unsigned WidenNumElts = WidenVT.getVectorNumElements();
- SmallVector<SDValue, 16> Ops(WidenNumElts);
- unsigned Increment = LdEltVT.getSizeInBits() / 8;
- Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
- LD->getPointerInfo(),
- LdEltVT, isVolatile, isNonTemporal, isInvariant,
- Align, AAInfo);
- LdChain.push_back(Ops[0].getValue(1));
- unsigned i = 0, Offset = Increment;
- for (i=1; i < NumElts; ++i, Offset += Increment) {
- SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
- BasePtr,
- DAG.getConstant(Offset,
- BasePtr.getValueType()));
- Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
- LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
- isVolatile, isNonTemporal, isInvariant, Align,
- AAInfo);
- LdChain.push_back(Ops[i].getValue(1));
- }
-
- // Fill the rest with undefs
- SDValue UndefVal = DAG.getUNDEF(EltVT);
- for (; i != WidenNumElts; ++i)
- Ops[i] = UndefVal;
-
- return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
-}
-
-
-void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
- StoreSDNode *ST) {
- // The strategy assumes that we can efficiently store powers of two widths.
- // The routines chops the vector into the largest vector stores with the same
- // element type or scalar stores.
- SDValue Chain = ST->getChain();
- SDValue BasePtr = ST->getBasePtr();
- unsigned Align = ST->getAlignment();
- bool isVolatile = ST->isVolatile();
- bool isNonTemporal = ST->isNonTemporal();
- AAMDNodes AAInfo = ST->getAAInfo();
- SDValue ValOp = GetWidenedVector(ST->getValue());
- SDLoc dl(ST);
-
- EVT StVT = ST->getMemoryVT();
- unsigned StWidth = StVT.getSizeInBits();
- EVT ValVT = ValOp.getValueType();
- unsigned ValWidth = ValVT.getSizeInBits();
- EVT ValEltVT = ValVT.getVectorElementType();
- unsigned ValEltWidth = ValEltVT.getSizeInBits();
- assert(StVT.getVectorElementType() == ValEltVT);
-
- int Idx = 0; // current index to store
- unsigned Offset = 0; // offset from base to store
- while (StWidth != 0) {
- // Find the largest vector type we can store with
- EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
- unsigned NewVTWidth = NewVT.getSizeInBits();
- unsigned Increment = NewVTWidth / 8;
- if (NewVT.isVector()) {
- unsigned NumVTElts = NewVT.getVectorNumElements();
- do {
- SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
- DAG.getConstant(Idx, TLI.getVectorIdxTy()));
- StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
- ST->getPointerInfo().getWithOffset(Offset),
- isVolatile, isNonTemporal,
- MinAlign(Align, Offset), AAInfo));
- StWidth -= NewVTWidth;
- Offset += Increment;
- Idx += NumVTElts;
- BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
- DAG.getConstant(Increment, BasePtr.getValueType()));
- } while (StWidth != 0 && StWidth >= NewVTWidth);
- } else {
- // Cast the vector to the scalar type we can store
- unsigned NumElts = ValWidth / NewVTWidth;
- EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
- SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
- // Readjust index position based on new vector type
- Idx = Idx * ValEltWidth / NewVTWidth;
- do {
- SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
- DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
- StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
- ST->getPointerInfo().getWithOffset(Offset),
- isVolatile, isNonTemporal,
- MinAlign(Align, Offset), AAInfo));
- StWidth -= NewVTWidth;
- Offset += Increment;
- BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
- DAG.getConstant(Increment, BasePtr.getValueType()));
- } while (StWidth != 0 && StWidth >= NewVTWidth);
- // Restore index back to be relative to the original widen element type
- Idx = Idx * NewVTWidth / ValEltWidth;
- }
- }
-}
-
-void
-DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
- StoreSDNode *ST) {
- // For extension loads, it may not be more efficient to truncate the vector
- // and then store it. Instead, we extract each element and then store it.
- SDValue Chain = ST->getChain();
- SDValue BasePtr = ST->getBasePtr();
- unsigned Align = ST->getAlignment();
- bool isVolatile = ST->isVolatile();
- bool isNonTemporal = ST->isNonTemporal();
- AAMDNodes AAInfo = ST->getAAInfo();
- SDValue ValOp = GetWidenedVector(ST->getValue());
- SDLoc dl(ST);
-
- EVT StVT = ST->getMemoryVT();
- EVT ValVT = ValOp.getValueType();
-
- // It must be true that we the widen vector type is bigger than where
- // we need to store.
- assert(StVT.isVector() && ValOp.getValueType().isVector());
- assert(StVT.bitsLT(ValOp.getValueType()));
-
- // For truncating stores, we can not play the tricks of chopping legal
- // vector types and bit cast it to the right type. Instead, we unroll
- // the store.
- EVT StEltVT = StVT.getVectorElementType();
- EVT ValEltVT = ValVT.getVectorElementType();
- unsigned Increment = ValEltVT.getSizeInBits() / 8;
- unsigned NumElts = StVT.getVectorNumElements();
- SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
- ST->getPointerInfo(), StEltVT,
- isVolatile, isNonTemporal, Align,
- AAInfo));
- unsigned Offset = Increment;
- for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
- SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
- BasePtr, DAG.getConstant(Offset,
- BasePtr.getValueType()));
- SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
- StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
- ST->getPointerInfo().getWithOffset(Offset),
- StEltVT, isVolatile, isNonTemporal,
- MinAlign(Align, Offset), AAInfo));
- }
-}
-
-/// Modifies a vector input (widen or narrows) to a vector of NVT. The
-/// input vector must have the same element type as NVT.
-SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
- // Note that InOp might have been widened so it might already have
- // the right width or it might need be narrowed.
- EVT InVT = InOp.getValueType();
- assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
- "input and widen element type must match");
- SDLoc dl(InOp);
-
- // Check if InOp already has the right width.
- if (InVT == NVT)
- return InOp;
-
- unsigned InNumElts = InVT.getVectorNumElements();
- unsigned WidenNumElts = NVT.getVectorNumElements();
- if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
- unsigned NumConcat = WidenNumElts / InNumElts;
- SmallVector<SDValue, 16> Ops(NumConcat);
- SDValue UndefVal = DAG.getUNDEF(InVT);
- Ops[0] = InOp;
- for (unsigned i = 1; i != NumConcat; ++i)
- Ops[i] = UndefVal;
-
- return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
- }
-
- if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
- DAG.getConstant(0, TLI.getVectorIdxTy()));
-
- // Fall back to extract and build.
- SmallVector<SDValue, 16> Ops(WidenNumElts);
- EVT EltVT = NVT.getVectorElementType();
- unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
- unsigned Idx;
- for (Idx = 0; Idx < MinNumElts; ++Idx)
- Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
- DAG.getConstant(Idx, TLI.getVectorIdxTy()));
-
- SDValue UndefVal = DAG.getUNDEF(EltVT);
- for ( ; Idx < WidenNumElts; ++Idx)
- Ops[Idx] = UndefVal;
- return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
-}
+//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//\r
+//\r
+// The LLVM Compiler Infrastructure\r
+//\r
+// This file is distributed under the University of Illinois Open Source\r
+// License. See LICENSE.TXT for details.\r
+//\r
+//===----------------------------------------------------------------------===//\r
+//\r
+// This file performs vector type splitting and scalarization for LegalizeTypes.\r
+// Scalarization is the act of changing a computation in an illegal one-element\r
+// vector type to be a computation in its scalar element type. For example,\r
+// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed\r
+// as a base case when scalarizing vector arithmetic like <4 x f32>, which\r
+// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32\r
+// types.\r
+// Splitting is the act of changing a computation in an invalid vector type to\r
+// be a computation in two vectors of half the size. For example, implementing\r
+// <128 x f32> operations in terms of two <64 x f32> operations.\r
+//\r
+//===----------------------------------------------------------------------===//\r
+\r
+#include "LegalizeTypes.h"\r
+#include "llvm/IR/DataLayout.h"\r
+#include "llvm/Support/ErrorHandling.h"\r
+#include "llvm/Support/raw_ostream.h"\r
+using namespace llvm;\r
+\r
+#define DEBUG_TYPE "legalize-types"\r
+\r
+//===----------------------------------------------------------------------===//\r
+// Result Vector Scalarization: <1 x ty> -> ty.\r
+//===----------------------------------------------------------------------===//\r
+\r
+void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {\r
+ DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n");\r
+ SDValue R = SDValue();\r
+\r
+ switch (N->getOpcode()) {\r
+ default:\r
+#ifndef NDEBUG\r
+ dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n";\r
+#endif\r
+ report_fatal_error("Do not know how to scalarize the result of this "\r
+ "operator!\n");\r
+\r
+ case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;\r
+ case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;\r
+ case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;\r
+ case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;\r
+ case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;\r
+ case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;\r
+ case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;\r
+ case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;\r
+ case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;\r
+ case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;\r
+ case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;\r
+ case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;\r
+ case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;\r
+ case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;\r
+ case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;\r
+ case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;\r
+ case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;\r
+ case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;\r
+ case ISD::ANY_EXTEND:\r
+ case ISD::BSWAP:\r
+ case ISD::CTLZ:\r
+ case ISD::CTLZ_ZERO_UNDEF:\r
+ case ISD::CTPOP:\r
+ case ISD::CTTZ:\r
+ case ISD::CTTZ_ZERO_UNDEF:\r
+ case ISD::FABS:\r
+ case ISD::FCEIL:\r
+ case ISD::FCOS:\r
+ case ISD::FEXP:\r
+ case ISD::FEXP2:\r
+ case ISD::FFLOOR:\r
+ case ISD::FLOG:\r
+ case ISD::FLOG10:\r
+ case ISD::FLOG2:\r
+ case ISD::FNEARBYINT:\r
+ case ISD::FNEG:\r
+ case ISD::FP_EXTEND:\r
+ case ISD::FP_TO_SINT:\r
+ case ISD::FP_TO_UINT:\r
+ case ISD::FRINT:\r
+ case ISD::FROUND:\r
+ case ISD::FSIN:\r
+ case ISD::FSQRT:\r
+ case ISD::FTRUNC:\r
+ case ISD::SIGN_EXTEND:\r
+ case ISD::SINT_TO_FP:\r
+ case ISD::TRUNCATE:\r
+ case ISD::UINT_TO_FP:\r
+ case ISD::ZERO_EXTEND:\r
+ R = ScalarizeVecRes_UnaryOp(N);\r
+ break;\r
+\r
+ case ISD::ADD:\r
+ case ISD::AND:\r
+ case ISD::FADD:\r
+ case ISD::FCOPYSIGN:\r
+ case ISD::FDIV:\r
+ case ISD::FMUL:\r
+ case ISD::FMINNUM:\r
+ case ISD::FMAXNUM:\r
+\r
+ case ISD::FPOW:\r
+ case ISD::FREM:\r
+ case ISD::FSUB:\r
+ case ISD::MUL:\r
+ case ISD::OR:\r
+ case ISD::SDIV:\r
+ case ISD::SREM:\r
+ case ISD::SUB:\r
+ case ISD::UDIV:\r
+ case ISD::UREM:\r
+ case ISD::XOR:\r
+ case ISD::SHL:\r
+ case ISD::SRA:\r
+ case ISD::SRL:\r
+ R = ScalarizeVecRes_BinOp(N);\r
+ break;\r
+ case ISD::FMA:\r
+ R = ScalarizeVecRes_TernaryOp(N);\r
+ break;\r
+ }\r
+\r
+ // If R is null, the sub-method took care of registering the result.\r
+ if (R.getNode())\r
+ SetScalarizedVector(SDValue(N, ResNo), R);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {\r
+ SDValue LHS = GetScalarizedVector(N->getOperand(0));\r
+ SDValue RHS = GetScalarizedVector(N->getOperand(1));\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N),\r
+ LHS.getValueType(), LHS, RHS);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {\r
+ SDValue Op0 = GetScalarizedVector(N->getOperand(0));\r
+ SDValue Op1 = GetScalarizedVector(N->getOperand(1));\r
+ SDValue Op2 = GetScalarizedVector(N->getOperand(2));\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N),\r
+ Op0.getValueType(), Op0, Op1, Op2);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,\r
+ unsigned ResNo) {\r
+ SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);\r
+ return GetScalarizedVector(Op);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {\r
+ EVT NewVT = N->getValueType(0).getVectorElementType();\r
+ return DAG.getNode(ISD::BITCAST, SDLoc(N),\r
+ NewVT, N->getOperand(0));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {\r
+ EVT EltVT = N->getValueType(0).getVectorElementType();\r
+ SDValue InOp = N->getOperand(0);\r
+ // The BUILD_VECTOR operands may be of wider element types and\r
+ // we may need to truncate them back to the requested return type.\r
+ if (EltVT.isInteger())\r
+ return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);\r
+ return InOp;\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {\r
+ EVT NewVT = N->getValueType(0).getVectorElementType();\r
+ SDValue Op0 = GetScalarizedVector(N->getOperand(0));\r
+ return DAG.getConvertRndSat(NewVT, SDLoc(N),\r
+ Op0, DAG.getValueType(NewVT),\r
+ DAG.getValueType(Op0.getValueType()),\r
+ N->getOperand(3),\r
+ N->getOperand(4),\r
+ cast<CvtRndSatSDNode>(N)->getCvtCode());\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {\r
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),\r
+ N->getValueType(0).getVectorElementType(),\r
+ N->getOperand(0), N->getOperand(1));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {\r
+ EVT NewVT = N->getValueType(0).getVectorElementType();\r
+ SDValue Op = GetScalarizedVector(N->getOperand(0));\r
+ return DAG.getNode(ISD::FP_ROUND, SDLoc(N),\r
+ NewVT, Op, N->getOperand(1));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {\r
+ SDValue Op = GetScalarizedVector(N->getOperand(0));\r
+ return DAG.getNode(ISD::FPOWI, SDLoc(N),\r
+ Op.getValueType(), Op, N->getOperand(1));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {\r
+ // The value to insert may have a wider type than the vector element type,\r
+ // so be sure to truncate it to the element type if necessary.\r
+ SDValue Op = N->getOperand(1);\r
+ EVT EltVT = N->getValueType(0).getVectorElementType();\r
+ if (Op.getValueType() != EltVT)\r
+ // FIXME: Can this happen for floating point types?\r
+ Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);\r
+ return Op;\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {\r
+ assert(N->isUnindexed() && "Indexed vector load?");\r
+\r
+ SDValue Result = DAG.getLoad(ISD::UNINDEXED,\r
+ N->getExtensionType(),\r
+ N->getValueType(0).getVectorElementType(),\r
+ SDLoc(N),\r
+ N->getChain(), N->getBasePtr(),\r
+ DAG.getUNDEF(N->getBasePtr().getValueType()),\r
+ N->getPointerInfo(),\r
+ N->getMemoryVT().getVectorElementType(),\r
+ N->isVolatile(), N->isNonTemporal(),\r
+ N->isInvariant(), N->getOriginalAlignment(),\r
+ N->getAAInfo());\r
+\r
+ // Legalized the chain result - switch anything that used the old chain to\r
+ // use the new one.\r
+ ReplaceValueWith(SDValue(N, 1), Result.getValue(1));\r
+ return Result;\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {\r
+ // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.\r
+ EVT DestVT = N->getValueType(0).getVectorElementType();\r
+ SDValue Op = N->getOperand(0);\r
+ EVT OpVT = Op.getValueType();\r
+ SDLoc DL(N);\r
+ // The result needs scalarizing, but it's not a given that the source does.\r
+ // This is a workaround for targets where it's impossible to scalarize the\r
+ // result of a conversion, because the source type is legal.\r
+ // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}\r
+ // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is\r
+ // legal and was not scalarized.\r
+ // See the similar logic in ScalarizeVecRes_VSETCC\r
+ if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {\r
+ Op = GetScalarizedVector(Op);\r
+ } else {\r
+ EVT VT = OpVT.getVectorElementType();\r
+ Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ }\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {\r
+ EVT EltVT = N->getValueType(0).getVectorElementType();\r
+ EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();\r
+ SDValue LHS = GetScalarizedVector(N->getOperand(0));\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,\r
+ LHS, DAG.getValueType(ExtVT));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {\r
+ // If the operand is wider than the vector element type then it is implicitly\r
+ // truncated. Make that explicit here.\r
+ EVT EltVT = N->getValueType(0).getVectorElementType();\r
+ SDValue InOp = N->getOperand(0);\r
+ if (InOp.getValueType() != EltVT)\r
+ return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);\r
+ return InOp;\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {\r
+ SDValue Cond = GetScalarizedVector(N->getOperand(0));\r
+ SDValue LHS = GetScalarizedVector(N->getOperand(1));\r
+ TargetLowering::BooleanContent ScalarBool =\r
+ TLI.getBooleanContents(false, false);\r
+ TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);\r
+\r
+ // If integer and float booleans have different contents then we can't\r
+ // reliably optimize in all cases. There is a full explanation for this in\r
+ // DAGCombiner::visitSELECT() where the same issue affects folding\r
+ // (select C, 0, 1) to (xor C, 1).\r
+ if (TLI.getBooleanContents(false, false) !=\r
+ TLI.getBooleanContents(false, true)) {\r
+ // At least try the common case where the boolean is generated by a\r
+ // comparison.\r
+ if (Cond->getOpcode() == ISD::SETCC) {\r
+ EVT OpVT = Cond->getOperand(0)->getValueType(0);\r
+ ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());\r
+ VecBool = TLI.getBooleanContents(OpVT);\r
+ } else\r
+ ScalarBool = TargetLowering::UndefinedBooleanContent;\r
+ }\r
+\r
+ if (ScalarBool != VecBool) {\r
+ EVT CondVT = Cond.getValueType();\r
+ switch (ScalarBool) {\r
+ case TargetLowering::UndefinedBooleanContent:\r
+ break;\r
+ case TargetLowering::ZeroOrOneBooleanContent:\r
+ assert(VecBool == TargetLowering::UndefinedBooleanContent ||\r
+ VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);\r
+ // Vector read from all ones, scalar expects a single 1 so mask.\r
+ Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,\r
+ Cond, DAG.getConstant(1, CondVT));\r
+ break;\r
+ case TargetLowering::ZeroOrNegativeOneBooleanContent:\r
+ assert(VecBool == TargetLowering::UndefinedBooleanContent ||\r
+ VecBool == TargetLowering::ZeroOrOneBooleanContent);\r
+ // Vector reads from a one, scalar from all ones so sign extend.\r
+ Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,\r
+ Cond, DAG.getValueType(MVT::i1));\r
+ break;\r
+ }\r
+ }\r
+\r
+ return DAG.getSelect(SDLoc(N),\r
+ LHS.getValueType(), Cond, LHS,\r
+ GetScalarizedVector(N->getOperand(2)));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {\r
+ SDValue LHS = GetScalarizedVector(N->getOperand(1));\r
+ return DAG.getSelect(SDLoc(N),\r
+ LHS.getValueType(), N->getOperand(0), LHS,\r
+ GetScalarizedVector(N->getOperand(2)));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {\r
+ SDValue LHS = GetScalarizedVector(N->getOperand(2));\r
+ return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),\r
+ N->getOperand(0), N->getOperand(1),\r
+ LHS, GetScalarizedVector(N->getOperand(3)),\r
+ N->getOperand(4));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {\r
+ assert(N->getValueType(0).isVector() ==\r
+ N->getOperand(0).getValueType().isVector() &&\r
+ "Scalar/Vector type mismatch");\r
+\r
+ if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);\r
+\r
+ SDValue LHS = GetScalarizedVector(N->getOperand(0));\r
+ SDValue RHS = GetScalarizedVector(N->getOperand(1));\r
+ SDLoc DL(N);\r
+\r
+ // Turn it into a scalar SETCC.\r
+ return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {\r
+ return DAG.getUNDEF(N->getValueType(0).getVectorElementType());\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {\r
+ // Figure out if the scalar is the LHS or RHS and return it.\r
+ SDValue Arg = N->getOperand(2).getOperand(0);\r
+ if (Arg.getOpcode() == ISD::UNDEF)\r
+ return DAG.getUNDEF(N->getValueType(0).getVectorElementType());\r
+ unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();\r
+ return GetScalarizedVector(N->getOperand(Op));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {\r
+ assert(N->getValueType(0).isVector() &&\r
+ N->getOperand(0).getValueType().isVector() &&\r
+ "Operand types must be vectors");\r
+ SDValue LHS = N->getOperand(0);\r
+ SDValue RHS = N->getOperand(1);\r
+ EVT OpVT = LHS.getValueType();\r
+ EVT NVT = N->getValueType(0).getVectorElementType();\r
+ SDLoc DL(N);\r
+\r
+ // The result needs scalarizing, but it's not a given that the source does.\r
+ if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {\r
+ LHS = GetScalarizedVector(LHS);\r
+ RHS = GetScalarizedVector(RHS);\r
+ } else {\r
+ EVT VT = OpVT.getVectorElementType();\r
+ LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ }\r
+\r
+ // Turn it into a scalar SETCC.\r
+ SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,\r
+ N->getOperand(2));\r
+ // Vectors may have a different boolean contents to scalars. Promote the\r
+ // value appropriately.\r
+ ISD::NodeType ExtendCode =\r
+ TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));\r
+ return DAG.getNode(ExtendCode, DL, NVT, Res);\r
+}\r
+\r
+\r
+//===----------------------------------------------------------------------===//\r
+// Operand Vector Scalarization <1 x ty> -> ty.\r
+//===----------------------------------------------------------------------===//\r
+\r
+bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {\r
+ DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n");\r
+ SDValue Res = SDValue();\r
+\r
+ if (!Res.getNode()) {\r
+ switch (N->getOpcode()) {\r
+ default:\r
+#ifndef NDEBUG\r
+ dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n";\r
+#endif\r
+ llvm_unreachable("Do not know how to scalarize this operator's operand!");\r
+ case ISD::BITCAST:\r
+ Res = ScalarizeVecOp_BITCAST(N);\r
+ break;\r
+ case ISD::ANY_EXTEND:\r
+ case ISD::ZERO_EXTEND:\r
+ case ISD::SIGN_EXTEND:\r
+ case ISD::TRUNCATE:\r
+ case ISD::FP_TO_SINT:\r
+ case ISD::FP_TO_UINT:\r
+ case ISD::SINT_TO_FP:\r
+ case ISD::UINT_TO_FP:\r
+ Res = ScalarizeVecOp_UnaryOp(N);\r
+ break;\r
+ case ISD::CONCAT_VECTORS:\r
+ Res = ScalarizeVecOp_CONCAT_VECTORS(N);\r
+ break;\r
+ case ISD::EXTRACT_VECTOR_ELT:\r
+ Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);\r
+ break;\r
+ case ISD::VSELECT:\r
+ Res = ScalarizeVecOp_VSELECT(N);\r
+ break;\r
+ case ISD::STORE:\r
+ Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);\r
+ break;\r
+ case ISD::FP_ROUND:\r
+ Res = ScalarizeVecOp_FP_ROUND(N, OpNo);\r
+ break;\r
+ }\r
+ }\r
+\r
+ // If the result is null, the sub-method took care of registering results etc.\r
+ if (!Res.getNode()) return false;\r
+\r
+ // If the result is N, the sub-method updated N in place. Tell the legalizer\r
+ // core about this.\r
+ if (Res.getNode() == N)\r
+ return true;\r
+\r
+ assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&\r
+ "Invalid operand expansion");\r
+\r
+ ReplaceValueWith(SDValue(N, 0), Res);\r
+ return false;\r
+}\r
+\r
+/// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs\r
+/// to be scalarized, it must be <1 x ty>. Convert the element instead.\r
+SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {\r
+ SDValue Elt = GetScalarizedVector(N->getOperand(0));\r
+ return DAG.getNode(ISD::BITCAST, SDLoc(N),\r
+ N->getValueType(0), Elt);\r
+}\r
+\r
+/// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be\r
+/// scalarized, it must be <1 x ty>. Do the operation on the element instead.\r
+SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {\r
+ assert(N->getValueType(0).getVectorNumElements() == 1 &&\r
+ "Unexpected vector type!");\r
+ SDValue Elt = GetScalarizedVector(N->getOperand(0));\r
+ SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),\r
+ N->getValueType(0).getScalarType(), Elt);\r
+ // Revectorize the result so the types line up with what the uses of this\r
+ // expression expect.\r
+ return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);\r
+}\r
+\r
+/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -\r
+/// use a BUILD_VECTOR instead.\r
+SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {\r
+ SmallVector<SDValue, 8> Ops(N->getNumOperands());\r
+ for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)\r
+ Ops[i] = GetScalarizedVector(N->getOperand(i));\r
+ return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);\r
+}\r
+\r
+/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to\r
+/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the\r
+/// index.\r
+SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {\r
+ SDValue Res = GetScalarizedVector(N->getOperand(0));\r
+ if (Res.getValueType() != N->getValueType(0))\r
+ Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),\r
+ Res);\r
+ return Res;\r
+}\r
+\r
+\r
+/// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be\r
+/// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT\r
+/// (still with vector output type since that was acceptable if we got here).\r
+SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {\r
+ SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));\r
+ EVT VT = N->getValueType(0);\r
+\r
+ return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),\r
+ N->getOperand(2));\r
+}\r
+\r
+/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be\r
+/// scalarized, it must be <1 x ty>. Just store the element.\r
+SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){\r
+ assert(N->isUnindexed() && "Indexed store of one-element vector?");\r
+ assert(OpNo == 1 && "Do not know how to scalarize this operand!");\r
+ SDLoc dl(N);\r
+\r
+ if (N->isTruncatingStore())\r
+ return DAG.getTruncStore(N->getChain(), dl,\r
+ GetScalarizedVector(N->getOperand(1)),\r
+ N->getBasePtr(), N->getPointerInfo(),\r
+ N->getMemoryVT().getVectorElementType(),\r
+ N->isVolatile(), N->isNonTemporal(),\r
+ N->getAlignment(), N->getAAInfo());\r
+\r
+ return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),\r
+ N->getBasePtr(), N->getPointerInfo(),\r
+ N->isVolatile(), N->isNonTemporal(),\r
+ N->getOriginalAlignment(), N->getAAInfo());\r
+}\r
+\r
+/// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs\r
+/// to be scalarized, it must be <1 x ty>. Convert the element instead.\r
+SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {\r
+ SDValue Elt = GetScalarizedVector(N->getOperand(0));\r
+ SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),\r
+ N->getValueType(0).getVectorElementType(), Elt,\r
+ N->getOperand(1));\r
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);\r
+}\r
+\r
+//===----------------------------------------------------------------------===//\r
+// Result Vector Splitting\r
+//===----------------------------------------------------------------------===//\r
+\r
+/// SplitVectorResult - This method is called when the specified result of the\r
+/// specified node is found to need vector splitting. At this point, the node\r
+/// may also have invalid operands or may have other results that need\r
+/// legalization, we just know that (at least) one result needs vector\r
+/// splitting.\r
+void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {\r
+ DEBUG(dbgs() << "Split node result: ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n");\r
+ SDValue Lo, Hi;\r
+\r
+ // See if the target wants to custom expand this node.\r
+ if (CustomLowerNode(N, N->getValueType(ResNo), true))\r
+ return;\r
+\r
+ switch (N->getOpcode()) {\r
+ default:\r
+#ifndef NDEBUG\r
+ dbgs() << "SplitVectorResult #" << ResNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n";\r
+#endif\r
+ report_fatal_error("Do not know how to split the result of this "\r
+ "operator!\n");\r
+\r
+ case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;\r
+ case ISD::VSELECT:\r
+ case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;\r
+ case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;\r
+ case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;\r
+ case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;\r
+ case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;\r
+ case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;\r
+ case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;\r
+ case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;\r
+ case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;\r
+ case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;\r
+ case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;\r
+ case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;\r
+ case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;\r
+ case ISD::LOAD:\r
+ SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);\r
+ break;\r
+ case ISD::MLOAD:\r
+ SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);\r
+ break;\r
+ case ISD::SETCC:\r
+ SplitVecRes_SETCC(N, Lo, Hi);\r
+ break;\r
+ case ISD::VECTOR_SHUFFLE:\r
+ SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);\r
+ break;\r
+\r
+ case ISD::BSWAP:\r
+ case ISD::CONVERT_RNDSAT:\r
+ case ISD::CTLZ:\r
+ case ISD::CTTZ:\r
+ case ISD::CTLZ_ZERO_UNDEF:\r
+ case ISD::CTTZ_ZERO_UNDEF:\r
+ case ISD::CTPOP:\r
+ case ISD::FABS:\r
+ case ISD::FCEIL:\r
+ case ISD::FCOS:\r
+ case ISD::FEXP:\r
+ case ISD::FEXP2:\r
+ case ISD::FFLOOR:\r
+ case ISD::FLOG:\r
+ case ISD::FLOG10:\r
+ case ISD::FLOG2:\r
+ case ISD::FNEARBYINT:\r
+ case ISD::FNEG:\r
+ case ISD::FP_EXTEND:\r
+ case ISD::FP_ROUND:\r
+ case ISD::FP_TO_SINT:\r
+ case ISD::FP_TO_UINT:\r
+ case ISD::FRINT:\r
+ case ISD::FROUND:\r
+ case ISD::FSIN:\r
+ case ISD::FSQRT:\r
+ case ISD::FTRUNC:\r
+ case ISD::SINT_TO_FP:\r
+ case ISD::TRUNCATE:\r
+ case ISD::UINT_TO_FP:\r
+ SplitVecRes_UnaryOp(N, Lo, Hi);\r
+ break;\r
+\r
+ case ISD::ANY_EXTEND:\r
+ case ISD::SIGN_EXTEND:\r
+ case ISD::ZERO_EXTEND:\r
+ SplitVecRes_ExtendOp(N, Lo, Hi);\r
+ break;\r
+\r
+ case ISD::ADD:\r
+ case ISD::SUB:\r
+ case ISD::MUL:\r
+ case ISD::FADD:\r
+ case ISD::FCOPYSIGN:\r
+ case ISD::FSUB:\r
+ case ISD::FMUL:\r
+ case ISD::FMINNUM:\r
+ case ISD::FMAXNUM:\r
+ case ISD::SDIV:\r
+ case ISD::UDIV:\r
+ case ISD::FDIV:\r
+ case ISD::FPOW:\r
+ case ISD::AND:\r
+ case ISD::OR:\r
+ case ISD::XOR:\r
+ case ISD::SHL:\r
+ case ISD::SRA:\r
+ case ISD::SRL:\r
+ case ISD::UREM:\r
+ case ISD::SREM:\r
+ case ISD::FREM:\r
+ SplitVecRes_BinOp(N, Lo, Hi);\r
+ break;\r
+ case ISD::FMA:\r
+ SplitVecRes_TernaryOp(N, Lo, Hi);\r
+ break;\r
+ }\r
+\r
+ // If Lo/Hi is null, the sub-method took care of registering results etc.\r
+ if (Lo.getNode())\r
+ SetSplitVector(SDValue(N, ResNo), Lo, Hi);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ SDValue LHSLo, LHSHi;\r
+ GetSplitVector(N->getOperand(0), LHSLo, LHSHi);\r
+ SDValue RHSLo, RHSHi;\r
+ GetSplitVector(N->getOperand(1), RHSLo, RHSHi);\r
+ SDLoc dl(N);\r
+\r
+ Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);\r
+ Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ SDValue Op0Lo, Op0Hi;\r
+ GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);\r
+ SDValue Op1Lo, Op1Hi;\r
+ GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);\r
+ SDValue Op2Lo, Op2Hi;\r
+ GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);\r
+ SDLoc dl(N);\r
+\r
+ Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),\r
+ Op0Lo, Op1Lo, Op2Lo);\r
+ Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),\r
+ Op0Hi, Op1Hi, Op2Hi);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ // We know the result is a vector. The input may be either a vector or a\r
+ // scalar value.\r
+ EVT LoVT, HiVT;\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));\r
+ SDLoc dl(N);\r
+\r
+ SDValue InOp = N->getOperand(0);\r
+ EVT InVT = InOp.getValueType();\r
+\r
+ // Handle some special cases efficiently.\r
+ switch (getTypeAction(InVT)) {\r
+ case TargetLowering::TypeLegal:\r
+ case TargetLowering::TypePromoteInteger:\r
+ case TargetLowering::TypeSoftenFloat:\r
+ case TargetLowering::TypeScalarizeVector:\r
+ case TargetLowering::TypeWidenVector:\r
+ break;\r
+ case TargetLowering::TypeExpandInteger:\r
+ case TargetLowering::TypeExpandFloat:\r
+ // A scalar to vector conversion, where the scalar needs expansion.\r
+ // If the vector is being split in two then we can just convert the\r
+ // expanded pieces.\r
+ if (LoVT == HiVT) {\r
+ GetExpandedOp(InOp, Lo, Hi);\r
+ if (TLI.isBigEndian())\r
+ std::swap(Lo, Hi);\r
+ Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);\r
+ Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);\r
+ return;\r
+ }\r
+ break;\r
+ case TargetLowering::TypeSplitVector:\r
+ // If the input is a vector that needs to be split, convert each split\r
+ // piece of the input now.\r
+ GetSplitVector(InOp, Lo, Hi);\r
+ Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);\r
+ Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);\r
+ return;\r
+ }\r
+\r
+ // In the general case, convert the input to an integer and split it by hand.\r
+ EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());\r
+ EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());\r
+ if (TLI.isBigEndian())\r
+ std::swap(LoIntVT, HiIntVT);\r
+\r
+ SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);\r
+\r
+ if (TLI.isBigEndian())\r
+ std::swap(Lo, Hi);\r
+ Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);\r
+ Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ EVT LoVT, HiVT;\r
+ SDLoc dl(N);\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));\r
+ unsigned LoNumElts = LoVT.getVectorNumElements();\r
+ SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);\r
+ Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);\r
+\r
+ SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());\r
+ Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");\r
+ SDLoc dl(N);\r
+ unsigned NumSubvectors = N->getNumOperands() / 2;\r
+ if (NumSubvectors == 1) {\r
+ Lo = N->getOperand(0);\r
+ Hi = N->getOperand(1);\r
+ return;\r
+ }\r
+\r
+ EVT LoVT, HiVT;\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));\r
+\r
+ SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);\r
+ Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);\r
+\r
+ SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());\r
+ Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ SDValue Vec = N->getOperand(0);\r
+ SDValue Idx = N->getOperand(1);\r
+ SDLoc dl(N);\r
+\r
+ EVT LoVT, HiVT;\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));\r
+\r
+ Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);\r
+ uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();\r
+ Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,\r
+ DAG.getConstant(IdxVal + LoVT.getVectorNumElements(),\r
+ TLI.getVectorIdxTy()));\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ SDValue Vec = N->getOperand(0);\r
+ SDValue SubVec = N->getOperand(1);\r
+ SDValue Idx = N->getOperand(2);\r
+ SDLoc dl(N);\r
+ GetSplitVector(Vec, Lo, Hi);\r
+\r
+ // Spill the vector to the stack.\r
+ EVT VecVT = Vec.getValueType();\r
+ EVT SubVecVT = VecVT.getVectorElementType();\r
+ SDValue StackPtr = DAG.CreateStackTemporary(VecVT);\r
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,\r
+ MachinePointerInfo(), false, false, 0);\r
+\r
+ // Store the new subvector into the specified index.\r
+ SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);\r
+ Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());\r
+ unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);\r
+ Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),\r
+ false, false, 0);\r
+\r
+ // Load the Lo part from the stack slot.\r
+ Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),\r
+ false, false, false, 0);\r
+\r
+ // Increment the pointer to the other part.\r
+ unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;\r
+ StackPtr =\r
+ DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,\r
+ DAG.getConstant(IncrementSize, StackPtr.getValueType()));\r
+\r
+ // Load the Hi part from the stack slot.\r
+ Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),\r
+ false, false, false, MinAlign(Alignment, IncrementSize));\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ SDLoc dl(N);\r
+ GetSplitVector(N->getOperand(0), Lo, Hi);\r
+ Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));\r
+ Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ SDValue LHSLo, LHSHi;\r
+ GetSplitVector(N->getOperand(0), LHSLo, LHSHi);\r
+ SDLoc dl(N);\r
+\r
+ EVT LoVT, HiVT;\r
+ std::tie(LoVT, HiVT) =\r
+ DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());\r
+\r
+ Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,\r
+ DAG.getValueType(LoVT));\r
+ Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,\r
+ DAG.getValueType(HiVT));\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ SDValue Vec = N->getOperand(0);\r
+ SDValue Elt = N->getOperand(1);\r
+ SDValue Idx = N->getOperand(2);\r
+ SDLoc dl(N);\r
+ GetSplitVector(Vec, Lo, Hi);\r
+\r
+ if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {\r
+ unsigned IdxVal = CIdx->getZExtValue();\r
+ unsigned LoNumElts = Lo.getValueType().getVectorNumElements();\r
+ if (IdxVal < LoNumElts)\r
+ Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,\r
+ Lo.getValueType(), Lo, Elt, Idx);\r
+ else\r
+ Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,\r
+ DAG.getConstant(IdxVal - LoNumElts,\r
+ TLI.getVectorIdxTy()));\r
+ return;\r
+ }\r
+\r
+ // See if the target wants to custom expand this node.\r
+ if (CustomLowerNode(N, N->getValueType(0), true))\r
+ return;\r
+\r
+ // Spill the vector to the stack.\r
+ EVT VecVT = Vec.getValueType();\r
+ EVT EltVT = VecVT.getVectorElementType();\r
+ SDValue StackPtr = DAG.CreateStackTemporary(VecVT);\r
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,\r
+ MachinePointerInfo(), false, false, 0);\r
+\r
+ // Store the new element. This may be larger than the vector element type,\r
+ // so use a truncating store.\r
+ SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);\r
+ Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());\r
+ unsigned Alignment =\r
+ TLI.getDataLayout()->getPrefTypeAlignment(VecType);\r
+ Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,\r
+ false, false, 0);\r
+\r
+ // Load the Lo part from the stack slot.\r
+ Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),\r
+ false, false, false, 0);\r
+\r
+ // Increment the pointer to the other part.\r
+ unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;\r
+ StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,\r
+ DAG.getConstant(IncrementSize, StackPtr.getValueType()));\r
+\r
+ // Load the Hi part from the stack slot.\r
+ Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),\r
+ false, false, false, MinAlign(Alignment, IncrementSize));\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ EVT LoVT, HiVT;\r
+ SDLoc dl(N);\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));\r
+ Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));\r
+ Hi = DAG.getUNDEF(HiVT);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");\r
+ EVT LoVT, HiVT;\r
+ SDLoc dl(LD);\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));\r
+\r
+ ISD::LoadExtType ExtType = LD->getExtensionType();\r
+ SDValue Ch = LD->getChain();\r
+ SDValue Ptr = LD->getBasePtr();\r
+ SDValue Offset = DAG.getUNDEF(Ptr.getValueType());\r
+ EVT MemoryVT = LD->getMemoryVT();\r
+ unsigned Alignment = LD->getOriginalAlignment();\r
+ bool isVolatile = LD->isVolatile();\r
+ bool isNonTemporal = LD->isNonTemporal();\r
+ bool isInvariant = LD->isInvariant();\r
+ AAMDNodes AAInfo = LD->getAAInfo();\r
+\r
+ EVT LoMemVT, HiMemVT;\r
+ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);\r
+\r
+ Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,\r
+ LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,\r
+ isInvariant, Alignment, AAInfo);\r
+\r
+ unsigned IncrementSize = LoMemVT.getSizeInBits()/8;\r
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,\r
+ DAG.getConstant(IncrementSize, Ptr.getValueType()));\r
+ Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,\r
+ LD->getPointerInfo().getWithOffset(IncrementSize),\r
+ HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,\r
+ AAInfo);\r
+\r
+ // Build a factor node to remember that this load is independent of the\r
+ // other one.\r
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),\r
+ Hi.getValue(1));\r
+\r
+ // Legalized the chain result - switch anything that used the old chain to\r
+ // use the new one.\r
+ ReplaceValueWith(SDValue(LD, 1), Ch);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,\r
+ SDValue &Lo, SDValue &Hi) {\r
+ EVT LoVT, HiVT;\r
+ SDLoc dl(MLD);\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));\r
+\r
+ SDValue Ch = MLD->getChain();\r
+ SDValue Ptr = MLD->getBasePtr();\r
+ SDValue Mask = MLD->getMask();\r
+ unsigned Alignment = MLD->getOriginalAlignment();\r
+\r
+ // if Alignment is equal to the vector size,\r
+ // take the half of it for the second part\r
+ unsigned SecondHalfAlignment =\r
+ (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?\r
+ Alignment/2 : Alignment;\r
+\r
+ SDValue MaskLo, MaskHi;\r
+ std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);\r
+\r
+ EVT MemoryVT = MLD->getMemoryVT();\r
+ EVT LoMemVT, HiMemVT;\r
+ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);\r
+\r
+ SDValue Src0 = MLD->getSrc0();\r
+ SDValue Src0Lo, Src0Hi;\r
+ std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);\r
+\r
+ MachineMemOperand *MMO = DAG.getMachineFunction().\r
+ getMachineMemOperand(MLD->getPointerInfo(), \r
+ MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),\r
+ Alignment, MLD->getAAInfo(), MLD->getRanges());\r
+\r
+ Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, MMO);\r
+\r
+ unsigned IncrementSize = LoMemVT.getSizeInBits()/8;\r
+ Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,\r
+ DAG.getConstant(IncrementSize, Ptr.getValueType()));\r
+\r
+ MMO = DAG.getMachineFunction().\r
+ getMachineMemOperand(MLD->getPointerInfo(), \r
+ MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),\r
+ SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());\r
+\r
+ Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, MMO);\r
+\r
+\r
+ // Build a factor node to remember that this load is independent of the\r
+ // other one.\r
+ Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),\r
+ Hi.getValue(1));\r
+\r
+ // Legalized the chain result - switch anything that used the old chain to\r
+ // use the new one.\r
+ ReplaceValueWith(SDValue(MLD, 1), Ch);\r
+\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {\r
+ assert(N->getValueType(0).isVector() &&\r
+ N->getOperand(0).getValueType().isVector() &&\r
+ "Operand types must be vectors");\r
+\r
+ EVT LoVT, HiVT;\r
+ SDLoc DL(N);\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));\r
+\r
+ // Split the input.\r
+ SDValue LL, LH, RL, RH;\r
+ std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);\r
+ std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);\r
+\r
+ Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));\r
+ Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ // Get the dest types - they may not match the input types, e.g. int_to_fp.\r
+ EVT LoVT, HiVT;\r
+ SDLoc dl(N);\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));\r
+\r
+ // If the input also splits, handle it directly for a compile time speedup.\r
+ // Otherwise split it by hand.\r
+ EVT InVT = N->getOperand(0).getValueType();\r
+ if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)\r
+ GetSplitVector(N->getOperand(0), Lo, Hi);\r
+ else\r
+ std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);\r
+\r
+ if (N->getOpcode() == ISD::FP_ROUND) {\r
+ Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));\r
+ Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));\r
+ } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {\r
+ SDValue DTyOpLo = DAG.getValueType(LoVT);\r
+ SDValue DTyOpHi = DAG.getValueType(HiVT);\r
+ SDValue STyOpLo = DAG.getValueType(Lo.getValueType());\r
+ SDValue STyOpHi = DAG.getValueType(Hi.getValueType());\r
+ SDValue RndOp = N->getOperand(3);\r
+ SDValue SatOp = N->getOperand(4);\r
+ ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();\r
+ Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,\r
+ CvtCode);\r
+ Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,\r
+ CvtCode);\r
+ } else {\r
+ Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);\r
+ Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);\r
+ }\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,\r
+ SDValue &Hi) {\r
+ SDLoc dl(N);\r
+ EVT SrcVT = N->getOperand(0).getValueType();\r
+ EVT DestVT = N->getValueType(0);\r
+ EVT LoVT, HiVT;\r
+ std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);\r
+\r
+ // We can do better than a generic split operation if the extend is doing\r
+ // more than just doubling the width of the elements and the following are\r
+ // true:\r
+ // - The number of vector elements is even,\r
+ // - the source type is legal,\r
+ // - the type of a split source is illegal,\r
+ // - the type of an extended (by doubling element size) source is legal, and\r
+ // - the type of that extended source when split is legal.\r
+ //\r
+ // This won't necessarily completely legalize the operation, but it will\r
+ // more effectively move in the right direction and prevent falling down\r
+ // to scalarization in many cases due to the input vector being split too\r
+ // far.\r
+ unsigned NumElements = SrcVT.getVectorNumElements();\r
+ if ((NumElements & 1) == 0 &&\r
+ SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {\r
+ LLVMContext &Ctx = *DAG.getContext();\r
+ EVT NewSrcVT = EVT::getVectorVT(\r
+ Ctx, EVT::getIntegerVT(\r
+ Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),\r
+ NumElements);\r
+ EVT SplitSrcVT =\r
+ EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);\r
+ EVT SplitLoVT, SplitHiVT;\r
+ std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);\r
+ if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&\r
+ TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {\r
+ DEBUG(dbgs() << "Split vector extend via incremental extend:";\r
+ N->dump(&DAG); dbgs() << "\n");\r
+ // Extend the source vector by one step.\r
+ SDValue NewSrc =\r
+ DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));\r
+ // Get the low and high halves of the new, extended one step, vector.\r
+ std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);\r
+ // Extend those vector halves the rest of the way.\r
+ Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);\r
+ Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);\r
+ return;\r
+ }\r
+ }\r
+ // Fall back to the generic unary operator splitting otherwise.\r
+ SplitVecRes_UnaryOp(N, Lo, Hi);\r
+}\r
+\r
+void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,\r
+ SDValue &Lo, SDValue &Hi) {\r
+ // The low and high parts of the original input give four input vectors.\r
+ SDValue Inputs[4];\r
+ SDLoc dl(N);\r
+ GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);\r
+ GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);\r
+ EVT NewVT = Inputs[0].getValueType();\r
+ unsigned NewElts = NewVT.getVectorNumElements();\r
+\r
+ // If Lo or Hi uses elements from at most two of the four input vectors, then\r
+ // express it as a vector shuffle of those two inputs. Otherwise extract the\r
+ // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.\r
+ SmallVector<int, 16> Ops;\r
+ for (unsigned High = 0; High < 2; ++High) {\r
+ SDValue &Output = High ? Hi : Lo;\r
+\r
+ // Build a shuffle mask for the output, discovering on the fly which\r
+ // input vectors to use as shuffle operands (recorded in InputUsed).\r
+ // If building a suitable shuffle vector proves too hard, then bail\r
+ // out with useBuildVector set.\r
+ unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.\r
+ unsigned FirstMaskIdx = High * NewElts;\r
+ bool useBuildVector = false;\r
+ for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {\r
+ // The mask element. This indexes into the input.\r
+ int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);\r
+\r
+ // The input vector this mask element indexes into.\r
+ unsigned Input = (unsigned)Idx / NewElts;\r
+\r
+ if (Input >= array_lengthof(Inputs)) {\r
+ // The mask element does not index into any input vector.\r
+ Ops.push_back(-1);\r
+ continue;\r
+ }\r
+\r
+ // Turn the index into an offset from the start of the input vector.\r
+ Idx -= Input * NewElts;\r
+\r
+ // Find or create a shuffle vector operand to hold this input.\r
+ unsigned OpNo;\r
+ for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {\r
+ if (InputUsed[OpNo] == Input) {\r
+ // This input vector is already an operand.\r
+ break;\r
+ } else if (InputUsed[OpNo] == -1U) {\r
+ // Create a new operand for this input vector.\r
+ InputUsed[OpNo] = Input;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (OpNo >= array_lengthof(InputUsed)) {\r
+ // More than two input vectors used! Give up on trying to create a\r
+ // shuffle vector. Insert all elements into a BUILD_VECTOR instead.\r
+ useBuildVector = true;\r
+ break;\r
+ }\r
+\r
+ // Add the mask index for the new shuffle vector.\r
+ Ops.push_back(Idx + OpNo * NewElts);\r
+ }\r
+\r
+ if (useBuildVector) {\r
+ EVT EltVT = NewVT.getVectorElementType();\r
+ SmallVector<SDValue, 16> SVOps;\r
+\r
+ // Extract the input elements by hand.\r
+ for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {\r
+ // The mask element. This indexes into the input.\r
+ int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);\r
+\r
+ // The input vector this mask element indexes into.\r
+ unsigned Input = (unsigned)Idx / NewElts;\r
+\r
+ if (Input >= array_lengthof(Inputs)) {\r
+ // The mask element is "undef" or indexes off the end of the input.\r
+ SVOps.push_back(DAG.getUNDEF(EltVT));\r
+ continue;\r
+ }\r
+\r
+ // Turn the index into an offset from the start of the input vector.\r
+ Idx -= Input * NewElts;\r
+\r
+ // Extract the vector element by hand.\r
+ SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,\r
+ Inputs[Input], DAG.getConstant(Idx,\r
+ TLI.getVectorIdxTy())));\r
+ }\r
+\r
+ // Construct the Lo/Hi output using a BUILD_VECTOR.\r
+ Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);\r
+ } else if (InputUsed[0] == -1U) {\r
+ // No input vectors were used! The result is undefined.\r
+ Output = DAG.getUNDEF(NewVT);\r
+ } else {\r
+ SDValue Op0 = Inputs[InputUsed[0]];\r
+ // If only one input was used, use an undefined vector for the other.\r
+ SDValue Op1 = InputUsed[1] == -1U ?\r
+ DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];\r
+ // At least one input vector was used. Create a new shuffle vector.\r
+ Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);\r
+ }\r
+\r
+ Ops.clear();\r
+ }\r
+}\r
+\r
+\r
+//===----------------------------------------------------------------------===//\r
+// Operand Vector Splitting\r
+//===----------------------------------------------------------------------===//\r
+\r
+/// SplitVectorOperand - This method is called when the specified operand of the\r
+/// specified node is found to need vector splitting. At this point, all of the\r
+/// result types of the node are known to be legal, but other operands of the\r
+/// node may need legalization as well as the specified one.\r
+bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {\r
+ DEBUG(dbgs() << "Split node operand: ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n");\r
+ SDValue Res = SDValue();\r
+\r
+ // See if the target wants to custom split this node.\r
+ if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))\r
+ return false;\r
+\r
+ if (!Res.getNode()) {\r
+ switch (N->getOpcode()) {\r
+ default:\r
+#ifndef NDEBUG\r
+ dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n";\r
+#endif\r
+ report_fatal_error("Do not know how to split this operator's "\r
+ "operand!\n");\r
+\r
+ case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;\r
+ case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;\r
+ case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;\r
+ case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;\r
+ case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;\r
+ case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break;\r
+ case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;\r
+ case ISD::STORE:\r
+ Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);\r
+ break;\r
+ case ISD::MSTORE:\r
+ Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);\r
+ break;\r
+ case ISD::VSELECT:\r
+ Res = SplitVecOp_VSELECT(N, OpNo);\r
+ break;\r
+ case ISD::CTTZ:\r
+ case ISD::CTLZ:\r
+ case ISD::CTPOP:\r
+ case ISD::FP_EXTEND:\r
+ case ISD::FP_TO_SINT:\r
+ case ISD::FP_TO_UINT:\r
+ case ISD::SINT_TO_FP:\r
+ case ISD::UINT_TO_FP:\r
+ case ISD::FTRUNC:\r
+ case ISD::SIGN_EXTEND:\r
+ case ISD::ZERO_EXTEND:\r
+ case ISD::ANY_EXTEND:\r
+ Res = SplitVecOp_UnaryOp(N);\r
+ break;\r
+ }\r
+ }\r
+\r
+ // If the result is null, the sub-method took care of registering results etc.\r
+ if (!Res.getNode()) return false;\r
+\r
+ // If the result is N, the sub-method updated N in place. Tell the legalizer\r
+ // core about this.\r
+ if (Res.getNode() == N)\r
+ return true;\r
+\r
+ assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&\r
+ "Invalid operand expansion");\r
+\r
+ ReplaceValueWith(SDValue(N, 0), Res);\r
+ return false;\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {\r
+ // The only possibility for an illegal operand is the mask, since result type\r
+ // legalization would have handled this node already otherwise.\r
+ assert(OpNo == 0 && "Illegal operand must be mask");\r
+\r
+ SDValue Mask = N->getOperand(0);\r
+ SDValue Src0 = N->getOperand(1);\r
+ SDValue Src1 = N->getOperand(2);\r
+ EVT Src0VT = Src0.getValueType();\r
+ SDLoc DL(N);\r
+ assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");\r
+\r
+ SDValue Lo, Hi;\r
+ GetSplitVector(N->getOperand(0), Lo, Hi);\r
+ assert(Lo.getValueType() == Hi.getValueType() &&\r
+ "Lo and Hi have differing types");\r
+\r
+ EVT LoOpVT, HiOpVT;\r
+ std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);\r
+ assert(LoOpVT == HiOpVT && "Asymmetric vector split?");\r
+\r
+ SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;\r
+ std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);\r
+ std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);\r
+ std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);\r
+\r
+ SDValue LoSelect =\r
+ DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);\r
+ SDValue HiSelect =\r
+ DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);\r
+\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {\r
+ // The result has a legal vector type, but the input needs splitting.\r
+ EVT ResVT = N->getValueType(0);\r
+ SDValue Lo, Hi;\r
+ SDLoc dl(N);\r
+ GetSplitVector(N->getOperand(0), Lo, Hi);\r
+ EVT InVT = Lo.getValueType();\r
+\r
+ EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),\r
+ InVT.getVectorNumElements());\r
+\r
+ Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);\r
+ Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);\r
+\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {\r
+ // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will\r
+ // end up being split all the way down to individual components. Convert the\r
+ // split pieces into integers and reassemble.\r
+ SDValue Lo, Hi;\r
+ GetSplitVector(N->getOperand(0), Lo, Hi);\r
+ Lo = BitConvertToInteger(Lo);\r
+ Hi = BitConvertToInteger(Hi);\r
+\r
+ if (TLI.isBigEndian())\r
+ std::swap(Lo, Hi);\r
+\r
+ return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),\r
+ JoinIntegers(Lo, Hi));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {\r
+ // We know that the extracted result type is legal.\r
+ EVT SubVT = N->getValueType(0);\r
+ SDValue Idx = N->getOperand(1);\r
+ SDLoc dl(N);\r
+ SDValue Lo, Hi;\r
+ GetSplitVector(N->getOperand(0), Lo, Hi);\r
+\r
+ uint64_t LoElts = Lo.getValueType().getVectorNumElements();\r
+ uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();\r
+\r
+ if (IdxVal < LoElts) {\r
+ assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&\r
+ "Extracted subvector crosses vector split!");\r
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);\r
+ } else {\r
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,\r
+ DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));\r
+ }\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {\r
+ SDValue Vec = N->getOperand(0);\r
+ SDValue Idx = N->getOperand(1);\r
+ EVT VecVT = Vec.getValueType();\r
+\r
+ if (isa<ConstantSDNode>(Idx)) {\r
+ uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();\r
+ assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");\r
+\r
+ SDValue Lo, Hi;\r
+ GetSplitVector(Vec, Lo, Hi);\r
+\r
+ uint64_t LoElts = Lo.getValueType().getVectorNumElements();\r
+\r
+ if (IdxVal < LoElts)\r
+ return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);\r
+ return SDValue(DAG.UpdateNodeOperands(N, Hi,\r
+ DAG.getConstant(IdxVal - LoElts,\r
+ Idx.getValueType())), 0);\r
+ }\r
+\r
+ // See if the target wants to custom expand this node.\r
+ if (CustomLowerNode(N, N->getValueType(0), true))\r
+ return SDValue();\r
+\r
+ // Store the vector to the stack.\r
+ EVT EltVT = VecVT.getVectorElementType();\r
+ SDLoc dl(N);\r
+ SDValue StackPtr = DAG.CreateStackTemporary(VecVT);\r
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,\r
+ MachinePointerInfo(), false, false, 0);\r
+\r
+ // Load back the required element.\r
+ StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);\r
+ return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,\r
+ MachinePointerInfo(), EltVT, false, false, false, 0);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,\r
+ unsigned OpNo) {\r
+ SDValue Ch = N->getChain();\r
+ SDValue Ptr = N->getBasePtr();\r
+ SDValue Mask = N->getMask();\r
+ SDValue Data = N->getData();\r
+ EVT MemoryVT = N->getMemoryVT();\r
+ unsigned Alignment = N->getOriginalAlignment();\r
+ SDLoc DL(N);\r
+ \r
+ EVT LoMemVT, HiMemVT;\r
+ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);\r
+\r
+ SDValue DataLo, DataHi;\r
+ GetSplitVector(Data, DataLo, DataHi);\r
+ SDValue MaskLo, MaskHi;\r
+ GetSplitVector(Mask, MaskLo, MaskHi);\r
+\r
+ // if Alignment is equal to the vector size,\r
+ // take the half of it for the second part\r
+ unsigned SecondHalfAlignment =\r
+ (Alignment == Data->getValueType(0).getSizeInBits()/8) ?\r
+ Alignment/2 : Alignment;\r
+\r
+ SDValue Lo, Hi;\r
+ MachineMemOperand *MMO = DAG.getMachineFunction().\r
+ getMachineMemOperand(N->getPointerInfo(), \r
+ MachineMemOperand::MOStore, LoMemVT.getStoreSize(),\r
+ Alignment, N->getAAInfo(), N->getRanges());\r
+\r
+ Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, MMO);\r
+\r
+ unsigned IncrementSize = LoMemVT.getSizeInBits()/8;\r
+ Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,\r
+ DAG.getConstant(IncrementSize, Ptr.getValueType()));\r
+\r
+ MMO = DAG.getMachineFunction().\r
+ getMachineMemOperand(N->getPointerInfo(), \r
+ MachineMemOperand::MOStore, HiMemVT.getStoreSize(),\r
+ SecondHalfAlignment, N->getAAInfo(), N->getRanges());\r
+\r
+ Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, MMO);\r
+\r
+\r
+ // Build a factor node to remember that this store is independent of the\r
+ // other one.\r
+ return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);\r
+\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {\r
+ assert(N->isUnindexed() && "Indexed store of vector?");\r
+ assert(OpNo == 1 && "Can only split the stored value");\r
+ SDLoc DL(N);\r
+\r
+ bool isTruncating = N->isTruncatingStore();\r
+ SDValue Ch = N->getChain();\r
+ SDValue Ptr = N->getBasePtr();\r
+ EVT MemoryVT = N->getMemoryVT();\r
+ unsigned Alignment = N->getOriginalAlignment();\r
+ bool isVol = N->isVolatile();\r
+ bool isNT = N->isNonTemporal();\r
+ AAMDNodes AAInfo = N->getAAInfo();\r
+ SDValue Lo, Hi;\r
+ GetSplitVector(N->getOperand(1), Lo, Hi);\r
+\r
+ EVT LoMemVT, HiMemVT;\r
+ std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);\r
+\r
+ unsigned IncrementSize = LoMemVT.getSizeInBits()/8;\r
+\r
+ if (isTruncating)\r
+ Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),\r
+ LoMemVT, isVol, isNT, Alignment, AAInfo);\r
+ else\r
+ Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),\r
+ isVol, isNT, Alignment, AAInfo);\r
+\r
+ // Increment the pointer to the other half.\r
+ Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,\r
+ DAG.getConstant(IncrementSize, Ptr.getValueType()));\r
+\r
+ if (isTruncating)\r
+ Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,\r
+ N->getPointerInfo().getWithOffset(IncrementSize),\r
+ HiMemVT, isVol, isNT, Alignment, AAInfo);\r
+ else\r
+ Hi = DAG.getStore(Ch, DL, Hi, Ptr,\r
+ N->getPointerInfo().getWithOffset(IncrementSize),\r
+ isVol, isNT, Alignment, AAInfo);\r
+\r
+ return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {\r
+ SDLoc DL(N);\r
+\r
+ // The input operands all must have the same type, and we know the result\r
+ // type is valid. Convert this to a buildvector which extracts all the\r
+ // input elements.\r
+ // TODO: If the input elements are power-two vectors, we could convert this to\r
+ // a new CONCAT_VECTORS node with elements that are half-wide.\r
+ SmallVector<SDValue, 32> Elts;\r
+ EVT EltVT = N->getValueType(0).getVectorElementType();\r
+ for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {\r
+ SDValue Op = N->getOperand(op);\r
+ for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();\r
+ i != e; ++i) {\r
+ Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,\r
+ Op, DAG.getConstant(i, TLI.getVectorIdxTy())));\r
+\r
+ }\r
+ }\r
+\r
+ return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) {\r
+ // The result type is legal, but the input type is illegal. If splitting\r
+ // ends up with the result type of each half still being legal, just\r
+ // do that. If, however, that would result in an illegal result type,\r
+ // we can try to get more clever with power-two vectors. Specifically,\r
+ // split the input type, but also widen the result element size, then\r
+ // concatenate the halves and truncate again. For example, consider a target\r
+ // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit\r
+ // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:\r
+ // %inlo = v4i32 extract_subvector %in, 0\r
+ // %inhi = v4i32 extract_subvector %in, 4\r
+ // %lo16 = v4i16 trunc v4i32 %inlo\r
+ // %hi16 = v4i16 trunc v4i32 %inhi\r
+ // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16\r
+ // %res = v8i8 trunc v8i16 %in16\r
+ //\r
+ // Without this transform, the original truncate would end up being\r
+ // scalarized, which is pretty much always a last resort.\r
+ SDValue InVec = N->getOperand(0);\r
+ EVT InVT = InVec->getValueType(0);\r
+ EVT OutVT = N->getValueType(0);\r
+ unsigned NumElements = OutVT.getVectorNumElements();\r
+ // Widening should have already made sure this is a power-two vector\r
+ // if we're trying to split it at all. assert() that's true, just in case.\r
+ assert(!(NumElements & 1) && "Splitting vector, but not in half!");\r
+\r
+ unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();\r
+ unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();\r
+\r
+ // If the input elements are only 1/2 the width of the result elements,\r
+ // just use the normal splitting. Our trick only work if there's room\r
+ // to split more than once.\r
+ if (InElementSize <= OutElementSize * 2)\r
+ return SplitVecOp_UnaryOp(N);\r
+ SDLoc DL(N);\r
+\r
+ // Extract the halves of the input via extract_subvector.\r
+ SDValue InLoVec, InHiVec;\r
+ std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);\r
+ // Truncate them to 1/2 the element size.\r
+ EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);\r
+ EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,\r
+ NumElements/2);\r
+ SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec);\r
+ SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec);\r
+ // Concatenate them to get the full intermediate truncation result.\r
+ EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);\r
+ SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,\r
+ HalfHi);\r
+ // Now finish up by truncating all the way down to the original result\r
+ // type. This should normally be something that ends up being legal directly,\r
+ // but in theory if a target has very wide vectors and an annoyingly\r
+ // restricted set of legal types, this split can chain to build things up.\r
+ return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {\r
+ assert(N->getValueType(0).isVector() &&\r
+ N->getOperand(0).getValueType().isVector() &&\r
+ "Operand types must be vectors");\r
+ // The result has a legal vector type, but the input needs splitting.\r
+ SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;\r
+ SDLoc DL(N);\r
+ GetSplitVector(N->getOperand(0), Lo0, Hi0);\r
+ GetSplitVector(N->getOperand(1), Lo1, Hi1);\r
+ unsigned PartElements = Lo0.getValueType().getVectorNumElements();\r
+ EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);\r
+ EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);\r
+\r
+ LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));\r
+ HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));\r
+ SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);\r
+ return PromoteTargetBoolean(Con, N->getValueType(0));\r
+}\r
+\r
+\r
+SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {\r
+ // The result has a legal vector type, but the input needs splitting.\r
+ EVT ResVT = N->getValueType(0);\r
+ SDValue Lo, Hi;\r
+ SDLoc DL(N);\r
+ GetSplitVector(N->getOperand(0), Lo, Hi);\r
+ EVT InVT = Lo.getValueType();\r
+\r
+ EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),\r
+ InVT.getVectorNumElements());\r
+\r
+ Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));\r
+ Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));\r
+\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);\r
+}\r
+\r
+\r
+\r
+//===----------------------------------------------------------------------===//\r
+// Result Vector Widening\r
+//===----------------------------------------------------------------------===//\r
+\r
+void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {\r
+ DEBUG(dbgs() << "Widen node result " << ResNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n");\r
+\r
+ // See if the target wants to custom widen this node.\r
+ if (CustomWidenLowerNode(N, N->getValueType(ResNo)))\r
+ return;\r
+\r
+ SDValue Res = SDValue();\r
+ switch (N->getOpcode()) {\r
+ default:\r
+#ifndef NDEBUG\r
+ dbgs() << "WidenVectorResult #" << ResNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n";\r
+#endif\r
+ llvm_unreachable("Do not know how to widen the result of this operator!");\r
+\r
+ case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;\r
+ case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;\r
+ case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;\r
+ case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;\r
+ case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;\r
+ case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;\r
+ case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;\r
+ case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;\r
+ case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;\r
+ case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;\r
+ case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;\r
+ case ISD::VSELECT:\r
+ case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;\r
+ case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;\r
+ case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;\r
+ case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;\r
+ case ISD::VECTOR_SHUFFLE:\r
+ Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));\r
+ break;\r
+\r
+ case ISD::ADD:\r
+ case ISD::AND:\r
+ case ISD::MUL:\r
+ case ISD::MULHS:\r
+ case ISD::MULHU:\r
+ case ISD::OR:\r
+ case ISD::SUB:\r
+ case ISD::XOR:\r
+ case ISD::FMINNUM:\r
+ case ISD::FMAXNUM:\r
+ Res = WidenVecRes_Binary(N);\r
+ break;\r
+\r
+ case ISD::FADD:\r
+ case ISD::FCOPYSIGN:\r
+ case ISD::FMUL:\r
+ case ISD::FPOW:\r
+ case ISD::FSUB:\r
+ case ISD::FDIV:\r
+ case ISD::FREM:\r
+ case ISD::SDIV:\r
+ case ISD::UDIV:\r
+ case ISD::SREM:\r
+ case ISD::UREM:\r
+ Res = WidenVecRes_BinaryCanTrap(N);\r
+ break;\r
+\r
+ case ISD::FPOWI:\r
+ Res = WidenVecRes_POWI(N);\r
+ break;\r
+\r
+ case ISD::SHL:\r
+ case ISD::SRA:\r
+ case ISD::SRL:\r
+ Res = WidenVecRes_Shift(N);\r
+ break;\r
+\r
+ case ISD::ANY_EXTEND:\r
+ case ISD::FP_EXTEND:\r
+ case ISD::FP_ROUND:\r
+ case ISD::FP_TO_SINT:\r
+ case ISD::FP_TO_UINT:\r
+ case ISD::SIGN_EXTEND:\r
+ case ISD::SINT_TO_FP:\r
+ case ISD::TRUNCATE:\r
+ case ISD::UINT_TO_FP:\r
+ case ISD::ZERO_EXTEND:\r
+ Res = WidenVecRes_Convert(N);\r
+ break;\r
+\r
+ case ISD::BSWAP:\r
+ case ISD::CTLZ:\r
+ case ISD::CTPOP:\r
+ case ISD::CTTZ:\r
+ case ISD::FABS:\r
+ case ISD::FCEIL:\r
+ case ISD::FCOS:\r
+ case ISD::FEXP:\r
+ case ISD::FEXP2:\r
+ case ISD::FFLOOR:\r
+ case ISD::FLOG:\r
+ case ISD::FLOG10:\r
+ case ISD::FLOG2:\r
+ case ISD::FNEARBYINT:\r
+ case ISD::FNEG:\r
+ case ISD::FRINT:\r
+ case ISD::FROUND:\r
+ case ISD::FSIN:\r
+ case ISD::FSQRT:\r
+ case ISD::FTRUNC:\r
+ Res = WidenVecRes_Unary(N);\r
+ break;\r
+ case ISD::FMA:\r
+ Res = WidenVecRes_Ternary(N);\r
+ break;\r
+ }\r
+\r
+ // If Res is null, the sub-method took care of registering the result.\r
+ if (Res.getNode())\r
+ SetWidenedVector(SDValue(N, ResNo), Res);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {\r
+ // Ternary op widening.\r
+ SDLoc dl(N);\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(0));\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(1));\r
+ SDValue InOp3 = GetWidenedVector(N->getOperand(2));\r
+ return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {\r
+ // Binary op widening.\r
+ SDLoc dl(N);\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(0));\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(1));\r
+ return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {\r
+ // Binary op widening for operations that can trap.\r
+ unsigned Opcode = N->getOpcode();\r
+ SDLoc dl(N);\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ EVT WidenEltVT = WidenVT.getVectorElementType();\r
+ EVT VT = WidenVT;\r
+ unsigned NumElts = VT.getVectorNumElements();\r
+ while (!TLI.isTypeLegal(VT) && NumElts != 1) {\r
+ NumElts = NumElts / 2;\r
+ VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);\r
+ }\r
+\r
+ if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {\r
+ // Operation doesn't trap so just widen as normal.\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(0));\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(1));\r
+ return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);\r
+ }\r
+\r
+ // No legal vector version so unroll the vector operation and then widen.\r
+ if (NumElts == 1)\r
+ return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());\r
+\r
+ // Since the operation can trap, apply operation on the original vector.\r
+ EVT MaxVT = VT;\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(0));\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(1));\r
+ unsigned CurNumElts = N->getValueType(0).getVectorNumElements();\r
+\r
+ SmallVector<SDValue, 16> ConcatOps(CurNumElts);\r
+ unsigned ConcatEnd = 0; // Current ConcatOps index.\r
+ int Idx = 0; // Current Idx into input vectors.\r
+\r
+ // NumElts := greatest legal vector size (at most WidenVT)\r
+ // while (orig. vector has unhandled elements) {\r
+ // take munches of size NumElts from the beginning and add to ConcatOps\r
+ // NumElts := next smaller supported vector size or 1\r
+ // }\r
+ while (CurNumElts != 0) {\r
+ while (CurNumElts >= NumElts) {\r
+ SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,\r
+ DAG.getConstant(Idx, TLI.getVectorIdxTy()));\r
+ SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,\r
+ DAG.getConstant(Idx, TLI.getVectorIdxTy()));\r
+ ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);\r
+ Idx += NumElts;\r
+ CurNumElts -= NumElts;\r
+ }\r
+ do {\r
+ NumElts = NumElts / 2;\r
+ VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);\r
+ } while (!TLI.isTypeLegal(VT) && NumElts != 1);\r
+\r
+ if (NumElts == 1) {\r
+ for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {\r
+ SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,\r
+ InOp1, DAG.getConstant(Idx,\r
+ TLI.getVectorIdxTy()));\r
+ SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,\r
+ InOp2, DAG.getConstant(Idx,\r
+ TLI.getVectorIdxTy()));\r
+ ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,\r
+ EOp1, EOp2);\r
+ }\r
+ CurNumElts = 0;\r
+ }\r
+ }\r
+\r
+ // Check to see if we have a single operation with the widen type.\r
+ if (ConcatEnd == 1) {\r
+ VT = ConcatOps[0].getValueType();\r
+ if (VT == WidenVT)\r
+ return ConcatOps[0];\r
+ }\r
+\r
+ // while (Some element of ConcatOps is not of type MaxVT) {\r
+ // From the end of ConcatOps, collect elements of the same type and put\r
+ // them into an op of the next larger supported type\r
+ // }\r
+ while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {\r
+ Idx = ConcatEnd - 1;\r
+ VT = ConcatOps[Idx--].getValueType();\r
+ while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)\r
+ Idx--;\r
+\r
+ int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;\r
+ EVT NextVT;\r
+ do {\r
+ NextSize *= 2;\r
+ NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);\r
+ } while (!TLI.isTypeLegal(NextVT));\r
+\r
+ if (!VT.isVector()) {\r
+ // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT\r
+ SDValue VecOp = DAG.getUNDEF(NextVT);\r
+ unsigned NumToInsert = ConcatEnd - Idx - 1;\r
+ for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {\r
+ VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,\r
+ ConcatOps[OpIdx], DAG.getConstant(i,\r
+ TLI.getVectorIdxTy()));\r
+ }\r
+ ConcatOps[Idx+1] = VecOp;\r
+ ConcatEnd = Idx + 2;\r
+ } else {\r
+ // Vector type, create a CONCAT_VECTORS of type NextVT\r
+ SDValue undefVec = DAG.getUNDEF(VT);\r
+ unsigned OpsToConcat = NextSize/VT.getVectorNumElements();\r
+ SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);\r
+ unsigned RealVals = ConcatEnd - Idx - 1;\r
+ unsigned SubConcatEnd = 0;\r
+ unsigned SubConcatIdx = Idx + 1;\r
+ while (SubConcatEnd < RealVals)\r
+ SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];\r
+ while (SubConcatEnd < OpsToConcat)\r
+ SubConcatOps[SubConcatEnd++] = undefVec;\r
+ ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,\r
+ NextVT, SubConcatOps);\r
+ ConcatEnd = SubConcatIdx + 1;\r
+ }\r
+ }\r
+\r
+ // Check to see if we have a single operation with the widen type.\r
+ if (ConcatEnd == 1) {\r
+ VT = ConcatOps[0].getValueType();\r
+ if (VT == WidenVT)\r
+ return ConcatOps[0];\r
+ }\r
+\r
+ // add undefs of size MaxVT until ConcatOps grows to length of WidenVT\r
+ unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();\r
+ if (NumOps != ConcatEnd ) {\r
+ SDValue UndefVal = DAG.getUNDEF(MaxVT);\r
+ for (unsigned j = ConcatEnd; j < NumOps; ++j)\r
+ ConcatOps[j] = UndefVal;\r
+ }\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,\r
+ makeArrayRef(ConcatOps.data(), NumOps));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {\r
+ SDValue InOp = N->getOperand(0);\r
+ SDLoc DL(N);\r
+\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+\r
+ EVT InVT = InOp.getValueType();\r
+ EVT InEltVT = InVT.getVectorElementType();\r
+ EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);\r
+\r
+ unsigned Opcode = N->getOpcode();\r
+ unsigned InVTNumElts = InVT.getVectorNumElements();\r
+\r
+ if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {\r
+ InOp = GetWidenedVector(N->getOperand(0));\r
+ InVT = InOp.getValueType();\r
+ InVTNumElts = InVT.getVectorNumElements();\r
+ if (InVTNumElts == WidenNumElts) {\r
+ if (N->getNumOperands() == 1)\r
+ return DAG.getNode(Opcode, DL, WidenVT, InOp);\r
+ return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));\r
+ }\r
+ }\r
+\r
+ if (TLI.isTypeLegal(InWidenVT)) {\r
+ // Because the result and the input are different vector types, widening\r
+ // the result could create a legal type but widening the input might make\r
+ // it an illegal type that might lead to repeatedly splitting the input\r
+ // and then widening it. To avoid this, we widen the input only if\r
+ // it results in a legal type.\r
+ if (WidenNumElts % InVTNumElts == 0) {\r
+ // Widen the input and call convert on the widened input vector.\r
+ unsigned NumConcat = WidenNumElts/InVTNumElts;\r
+ SmallVector<SDValue, 16> Ops(NumConcat);\r
+ Ops[0] = InOp;\r
+ SDValue UndefVal = DAG.getUNDEF(InVT);\r
+ for (unsigned i = 1; i != NumConcat; ++i)\r
+ Ops[i] = UndefVal;\r
+ SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);\r
+ if (N->getNumOperands() == 1)\r
+ return DAG.getNode(Opcode, DL, WidenVT, InVec);\r
+ return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));\r
+ }\r
+\r
+ if (InVTNumElts % WidenNumElts == 0) {\r
+ SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,\r
+ InOp, DAG.getConstant(0,\r
+ TLI.getVectorIdxTy()));\r
+ // Extract the input and convert the shorten input vector.\r
+ if (N->getNumOperands() == 1)\r
+ return DAG.getNode(Opcode, DL, WidenVT, InVal);\r
+ return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));\r
+ }\r
+ }\r
+\r
+ // Otherwise unroll into some nasty scalar code and rebuild the vector.\r
+ SmallVector<SDValue, 16> Ops(WidenNumElts);\r
+ EVT EltVT = WidenVT.getVectorElementType();\r
+ unsigned MinElts = std::min(InVTNumElts, WidenNumElts);\r
+ unsigned i;\r
+ for (i=0; i < MinElts; ++i) {\r
+ SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,\r
+ DAG.getConstant(i, TLI.getVectorIdxTy()));\r
+ if (N->getNumOperands() == 1)\r
+ Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);\r
+ else\r
+ Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));\r
+ }\r
+\r
+ SDValue UndefVal = DAG.getUNDEF(EltVT);\r
+ for (; i < WidenNumElts; ++i)\r
+ Ops[i] = UndefVal;\r
+\r
+ return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ SDValue InOp = GetWidenedVector(N->getOperand(0));\r
+ SDValue ShOp = N->getOperand(1);\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ SDValue InOp = GetWidenedVector(N->getOperand(0));\r
+ SDValue ShOp = N->getOperand(1);\r
+\r
+ EVT ShVT = ShOp.getValueType();\r
+ if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {\r
+ ShOp = GetWidenedVector(ShOp);\r
+ ShVT = ShOp.getValueType();\r
+ }\r
+ EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),\r
+ ShVT.getVectorElementType(),\r
+ WidenVT.getVectorNumElements());\r
+ if (ShVT != ShWidenVT)\r
+ ShOp = ModifyToType(ShOp, ShWidenVT);\r
+\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {\r
+ // Unary op widening.\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ SDValue InOp = GetWidenedVector(N->getOperand(0));\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),\r
+ cast<VTSDNode>(N->getOperand(1))->getVT()\r
+ .getVectorElementType(),\r
+ WidenVT.getVectorNumElements());\r
+ SDValue WidenLHS = GetWidenedVector(N->getOperand(0));\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N),\r
+ WidenVT, WidenLHS, DAG.getValueType(ExtVT));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {\r
+ SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);\r
+ return GetWidenedVector(WidenVec);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {\r
+ SDValue InOp = N->getOperand(0);\r
+ EVT InVT = InOp.getValueType();\r
+ EVT VT = N->getValueType(0);\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);\r
+ SDLoc dl(N);\r
+\r
+ switch (getTypeAction(InVT)) {\r
+ case TargetLowering::TypeLegal:\r
+ break;\r
+ case TargetLowering::TypePromoteInteger:\r
+ // If the incoming type is a vector that is being promoted, then\r
+ // we know that the elements are arranged differently and that we\r
+ // must perform the conversion using a stack slot.\r
+ if (InVT.isVector())\r
+ break;\r
+\r
+ // If the InOp is promoted to the same size, convert it. Otherwise,\r
+ // fall out of the switch and widen the promoted input.\r
+ InOp = GetPromotedInteger(InOp);\r
+ InVT = InOp.getValueType();\r
+ if (WidenVT.bitsEq(InVT))\r
+ return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);\r
+ break;\r
+ case TargetLowering::TypeSoftenFloat:\r
+ case TargetLowering::TypeExpandInteger:\r
+ case TargetLowering::TypeExpandFloat:\r
+ case TargetLowering::TypeScalarizeVector:\r
+ case TargetLowering::TypeSplitVector:\r
+ break;\r
+ case TargetLowering::TypeWidenVector:\r
+ // If the InOp is widened to the same size, convert it. Otherwise, fall\r
+ // out of the switch and widen the widened input.\r
+ InOp = GetWidenedVector(InOp);\r
+ InVT = InOp.getValueType();\r
+ if (WidenVT.bitsEq(InVT))\r
+ // The input widens to the same size. Convert to the widen value.\r
+ return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);\r
+ break;\r
+ }\r
+\r
+ unsigned WidenSize = WidenVT.getSizeInBits();\r
+ unsigned InSize = InVT.getSizeInBits();\r
+ // x86mmx is not an acceptable vector element type, so don't try.\r
+ if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {\r
+ // Determine new input vector type. The new input vector type will use\r
+ // the same element type (if its a vector) or use the input type as a\r
+ // vector. It is the same size as the type to widen to.\r
+ EVT NewInVT;\r
+ unsigned NewNumElts = WidenSize / InSize;\r
+ if (InVT.isVector()) {\r
+ EVT InEltVT = InVT.getVectorElementType();\r
+ NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,\r
+ WidenSize / InEltVT.getSizeInBits());\r
+ } else {\r
+ NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);\r
+ }\r
+\r
+ if (TLI.isTypeLegal(NewInVT)) {\r
+ // Because the result and the input are different vector types, widening\r
+ // the result could create a legal type but widening the input might make\r
+ // it an illegal type that might lead to repeatedly splitting the input\r
+ // and then widening it. To avoid this, we widen the input only if\r
+ // it results in a legal type.\r
+ SmallVector<SDValue, 16> Ops(NewNumElts);\r
+ SDValue UndefVal = DAG.getUNDEF(InVT);\r
+ Ops[0] = InOp;\r
+ for (unsigned i = 1; i < NewNumElts; ++i)\r
+ Ops[i] = UndefVal;\r
+\r
+ SDValue NewVec;\r
+ if (InVT.isVector())\r
+ NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);\r
+ else\r
+ NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);\r
+ return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);\r
+ }\r
+ }\r
+\r
+ return CreateStackStoreLoad(InOp, WidenVT);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {\r
+ SDLoc dl(N);\r
+ // Build a vector with undefined for the new nodes.\r
+ EVT VT = N->getValueType(0);\r
+\r
+ // Integer BUILD_VECTOR operands may be larger than the node's vector element\r
+ // type. The UNDEFs need to have the same type as the existing operands.\r
+ EVT EltVT = N->getOperand(0).getValueType();\r
+ unsigned NumElts = VT.getVectorNumElements();\r
+\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+\r
+ SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());\r
+ assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");\r
+ NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));\r
+\r
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {\r
+ EVT InVT = N->getOperand(0).getValueType();\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ SDLoc dl(N);\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+ unsigned NumInElts = InVT.getVectorNumElements();\r
+ unsigned NumOperands = N->getNumOperands();\r
+\r
+ bool InputWidened = false; // Indicates we need to widen the input.\r
+ if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {\r
+ if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {\r
+ // Add undef vectors to widen to correct length.\r
+ unsigned NumConcat = WidenVT.getVectorNumElements() /\r
+ InVT.getVectorNumElements();\r
+ SDValue UndefVal = DAG.getUNDEF(InVT);\r
+ SmallVector<SDValue, 16> Ops(NumConcat);\r
+ for (unsigned i=0; i < NumOperands; ++i)\r
+ Ops[i] = N->getOperand(i);\r
+ for (unsigned i = NumOperands; i != NumConcat; ++i)\r
+ Ops[i] = UndefVal;\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);\r
+ }\r
+ } else {\r
+ InputWidened = true;\r
+ if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {\r
+ // The inputs and the result are widen to the same value.\r
+ unsigned i;\r
+ for (i=1; i < NumOperands; ++i)\r
+ if (N->getOperand(i).getOpcode() != ISD::UNDEF)\r
+ break;\r
+\r
+ if (i == NumOperands)\r
+ // Everything but the first operand is an UNDEF so just return the\r
+ // widened first operand.\r
+ return GetWidenedVector(N->getOperand(0));\r
+\r
+ if (NumOperands == 2) {\r
+ // Replace concat of two operands with a shuffle.\r
+ SmallVector<int, 16> MaskOps(WidenNumElts, -1);\r
+ for (unsigned i = 0; i < NumInElts; ++i) {\r
+ MaskOps[i] = i;\r
+ MaskOps[i + NumInElts] = i + WidenNumElts;\r
+ }\r
+ return DAG.getVectorShuffle(WidenVT, dl,\r
+ GetWidenedVector(N->getOperand(0)),\r
+ GetWidenedVector(N->getOperand(1)),\r
+ &MaskOps[0]);\r
+ }\r
+ }\r
+ }\r
+\r
+ // Fall back to use extracts and build vector.\r
+ EVT EltVT = WidenVT.getVectorElementType();\r
+ SmallVector<SDValue, 16> Ops(WidenNumElts);\r
+ unsigned Idx = 0;\r
+ for (unsigned i=0; i < NumOperands; ++i) {\r
+ SDValue InOp = N->getOperand(i);\r
+ if (InputWidened)\r
+ InOp = GetWidenedVector(InOp);\r
+ for (unsigned j=0; j < NumInElts; ++j)\r
+ Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,\r
+ DAG.getConstant(j, TLI.getVectorIdxTy()));\r
+ }\r
+ SDValue UndefVal = DAG.getUNDEF(EltVT);\r
+ for (; Idx < WidenNumElts; ++Idx)\r
+ Ops[Idx] = UndefVal;\r
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {\r
+ SDLoc dl(N);\r
+ SDValue InOp = N->getOperand(0);\r
+ SDValue RndOp = N->getOperand(3);\r
+ SDValue SatOp = N->getOperand(4);\r
+\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+\r
+ EVT InVT = InOp.getValueType();\r
+ EVT InEltVT = InVT.getVectorElementType();\r
+ EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);\r
+\r
+ SDValue DTyOp = DAG.getValueType(WidenVT);\r
+ SDValue STyOp = DAG.getValueType(InWidenVT);\r
+ ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();\r
+\r
+ unsigned InVTNumElts = InVT.getVectorNumElements();\r
+ if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {\r
+ InOp = GetWidenedVector(InOp);\r
+ InVT = InOp.getValueType();\r
+ InVTNumElts = InVT.getVectorNumElements();\r
+ if (InVTNumElts == WidenNumElts)\r
+ return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,\r
+ SatOp, CvtCode);\r
+ }\r
+\r
+ if (TLI.isTypeLegal(InWidenVT)) {\r
+ // Because the result and the input are different vector types, widening\r
+ // the result could create a legal type but widening the input might make\r
+ // it an illegal type that might lead to repeatedly splitting the input\r
+ // and then widening it. To avoid this, we widen the input only if\r
+ // it results in a legal type.\r
+ if (WidenNumElts % InVTNumElts == 0) {\r
+ // Widen the input and call convert on the widened input vector.\r
+ unsigned NumConcat = WidenNumElts/InVTNumElts;\r
+ SmallVector<SDValue, 16> Ops(NumConcat);\r
+ Ops[0] = InOp;\r
+ SDValue UndefVal = DAG.getUNDEF(InVT);\r
+ for (unsigned i = 1; i != NumConcat; ++i)\r
+ Ops[i] = UndefVal;\r
+\r
+ InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);\r
+ return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,\r
+ SatOp, CvtCode);\r
+ }\r
+\r
+ if (InVTNumElts % WidenNumElts == 0) {\r
+ // Extract the input and convert the shorten input vector.\r
+ InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,\r
+ SatOp, CvtCode);\r
+ }\r
+ }\r
+\r
+ // Otherwise unroll into some nasty scalar code and rebuild the vector.\r
+ SmallVector<SDValue, 16> Ops(WidenNumElts);\r
+ EVT EltVT = WidenVT.getVectorElementType();\r
+ DTyOp = DAG.getValueType(EltVT);\r
+ STyOp = DAG.getValueType(InEltVT);\r
+\r
+ unsigned MinElts = std::min(InVTNumElts, WidenNumElts);\r
+ unsigned i;\r
+ for (i=0; i < MinElts; ++i) {\r
+ SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,\r
+ DAG.getConstant(i, TLI.getVectorIdxTy()));\r
+ Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,\r
+ SatOp, CvtCode);\r
+ }\r
+\r
+ SDValue UndefVal = DAG.getUNDEF(EltVT);\r
+ for (; i < WidenNumElts; ++i)\r
+ Ops[i] = UndefVal;\r
+\r
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {\r
+ EVT VT = N->getValueType(0);\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+ SDValue InOp = N->getOperand(0);\r
+ SDValue Idx = N->getOperand(1);\r
+ SDLoc dl(N);\r
+\r
+ if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)\r
+ InOp = GetWidenedVector(InOp);\r
+\r
+ EVT InVT = InOp.getValueType();\r
+\r
+ // Check if we can just return the input vector after widening.\r
+ uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();\r
+ if (IdxVal == 0 && InVT == WidenVT)\r
+ return InOp;\r
+\r
+ // Check if we can extract from the vector.\r
+ unsigned InNumElts = InVT.getVectorNumElements();\r
+ if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)\r
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);\r
+\r
+ // We could try widening the input to the right length but for now, extract\r
+ // the original elements, fill the rest with undefs and build a vector.\r
+ SmallVector<SDValue, 16> Ops(WidenNumElts);\r
+ EVT EltVT = VT.getVectorElementType();\r
+ unsigned NumElts = VT.getVectorNumElements();\r
+ unsigned i;\r
+ for (i=0; i < NumElts; ++i)\r
+ Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,\r
+ DAG.getConstant(IdxVal+i, TLI.getVectorIdxTy()));\r
+\r
+ SDValue UndefVal = DAG.getUNDEF(EltVT);\r
+ for (; i < WidenNumElts; ++i)\r
+ Ops[i] = UndefVal;\r
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {\r
+ SDValue InOp = GetWidenedVector(N->getOperand(0));\r
+ return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),\r
+ InOp.getValueType(), InOp,\r
+ N->getOperand(1), N->getOperand(2));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {\r
+ LoadSDNode *LD = cast<LoadSDNode>(N);\r
+ ISD::LoadExtType ExtType = LD->getExtensionType();\r
+\r
+ SDValue Result;\r
+ SmallVector<SDValue, 16> LdChain; // Chain for the series of load\r
+ if (ExtType != ISD::NON_EXTLOAD)\r
+ Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);\r
+ else\r
+ Result = GenWidenVectorLoads(LdChain, LD);\r
+\r
+ // If we generate a single load, we can use that for the chain. Otherwise,\r
+ // build a factor node to remember the multiple loads are independent and\r
+ // chain to that.\r
+ SDValue NewChain;\r
+ if (LdChain.size() == 1)\r
+ NewChain = LdChain[0];\r
+ else\r
+ NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);\r
+\r
+ // Modified the chain - switch anything that used the old chain to use\r
+ // the new one.\r
+ ReplaceValueWith(SDValue(N, 1), NewChain);\r
+\r
+ return Result;\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),\r
+ WidenVT, N->getOperand(0));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+\r
+ SDValue Cond1 = N->getOperand(0);\r
+ EVT CondVT = Cond1.getValueType();\r
+ if (CondVT.isVector()) {\r
+ EVT CondEltVT = CondVT.getVectorElementType();\r
+ EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),\r
+ CondEltVT, WidenNumElts);\r
+ if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)\r
+ Cond1 = GetWidenedVector(Cond1);\r
+\r
+ // If we have to split the condition there is no point in widening the\r
+ // select. This would result in an cycle of widening the select ->\r
+ // widening the condition operand -> splitting the condition operand ->\r
+ // splitting the select -> widening the select. Instead split this select\r
+ // further and widen the resulting type.\r
+ if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {\r
+ SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);\r
+ SDValue Res = ModifyToType(SplitSelect, WidenVT);\r
+ return Res;\r
+ }\r
+\r
+ if (Cond1.getValueType() != CondWidenVT)\r
+ Cond1 = ModifyToType(Cond1, CondWidenVT);\r
+ }\r
+\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(1));\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(2));\r
+ assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);\r
+ return DAG.getNode(N->getOpcode(), SDLoc(N),\r
+ WidenVT, Cond1, InOp1, InOp2);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(2));\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(3));\r
+ return DAG.getNode(ISD::SELECT_CC, SDLoc(N),\r
+ InOp1.getValueType(), N->getOperand(0),\r
+ N->getOperand(1), InOp1, InOp2, N->getOperand(4));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {\r
+ assert(N->getValueType(0).isVector() ==\r
+ N->getOperand(0).getValueType().isVector() &&\r
+ "Scalar/Vector type mismatch");\r
+ if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);\r
+\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(0));\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(1));\r
+ return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,\r
+ InOp1, InOp2, N->getOperand(2));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ return DAG.getUNDEF(WidenVT);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {\r
+ EVT VT = N->getValueType(0);\r
+ SDLoc dl(N);\r
+\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);\r
+ unsigned NumElts = VT.getVectorNumElements();\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(0));\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(1));\r
+\r
+ // Adjust mask based on new input vector length.\r
+ SmallVector<int, 16> NewMask;\r
+ for (unsigned i = 0; i != NumElts; ++i) {\r
+ int Idx = N->getMaskElt(i);\r
+ if (Idx < (int)NumElts)\r
+ NewMask.push_back(Idx);\r
+ else\r
+ NewMask.push_back(Idx - NumElts + WidenNumElts);\r
+ }\r
+ for (unsigned i = NumElts; i != WidenNumElts; ++i)\r
+ NewMask.push_back(-1);\r
+ return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {\r
+ assert(N->getValueType(0).isVector() &&\r
+ N->getOperand(0).getValueType().isVector() &&\r
+ "Operands must be vectors");\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+\r
+ SDValue InOp1 = N->getOperand(0);\r
+ EVT InVT = InOp1.getValueType();\r
+ assert(InVT.isVector() && "can not widen non-vector type");\r
+ EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),\r
+ InVT.getVectorElementType(), WidenNumElts);\r
+ InOp1 = GetWidenedVector(InOp1);\r
+ SDValue InOp2 = GetWidenedVector(N->getOperand(1));\r
+\r
+ // Assume that the input and output will be widen appropriately. If not,\r
+ // we will have to unroll it at some point.\r
+ assert(InOp1.getValueType() == WidenInVT &&\r
+ InOp2.getValueType() == WidenInVT &&\r
+ "Input not widened to expected type!");\r
+ (void)WidenInVT;\r
+ return DAG.getNode(ISD::SETCC, SDLoc(N),\r
+ WidenVT, InOp1, InOp2, N->getOperand(2));\r
+}\r
+\r
+\r
+//===----------------------------------------------------------------------===//\r
+// Widen Vector Operand\r
+//===----------------------------------------------------------------------===//\r
+bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {\r
+ DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n");\r
+ SDValue Res = SDValue();\r
+\r
+ // See if the target wants to custom widen this node.\r
+ if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))\r
+ return false;\r
+\r
+ switch (N->getOpcode()) {\r
+ default:\r
+#ifndef NDEBUG\r
+ dbgs() << "WidenVectorOperand op #" << OpNo << ": ";\r
+ N->dump(&DAG);\r
+ dbgs() << "\n";\r
+#endif\r
+ llvm_unreachable("Do not know how to widen this operator's operand!");\r
+\r
+ case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;\r
+ case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;\r
+ case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;\r
+ case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;\r
+ case ISD::STORE: Res = WidenVecOp_STORE(N); break;\r
+ case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;\r
+\r
+ case ISD::ANY_EXTEND:\r
+ case ISD::SIGN_EXTEND:\r
+ case ISD::ZERO_EXTEND:\r
+ Res = WidenVecOp_EXTEND(N);\r
+ break;\r
+\r
+ case ISD::FP_EXTEND:\r
+ case ISD::FP_TO_SINT:\r
+ case ISD::FP_TO_UINT:\r
+ case ISD::SINT_TO_FP:\r
+ case ISD::UINT_TO_FP:\r
+ case ISD::TRUNCATE:\r
+ Res = WidenVecOp_Convert(N);\r
+ break;\r
+ }\r
+\r
+ // If Res is null, the sub-method took care of registering the result.\r
+ if (!Res.getNode()) return false;\r
+\r
+ // If the result is N, the sub-method updated N in place. Tell the legalizer\r
+ // core about this.\r
+ if (Res.getNode() == N)\r
+ return true;\r
+\r
+\r
+ assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&\r
+ "Invalid operand expansion");\r
+\r
+ ReplaceValueWith(SDValue(N, 0), Res);\r
+ return false;\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {\r
+ SDLoc DL(N);\r
+ EVT VT = N->getValueType(0);\r
+\r
+ SDValue InOp = N->getOperand(0);\r
+ // If some legalization strategy other than widening is used on the operand,\r
+ // we can't safely assume that just extending the low lanes is the correct\r
+ // transformation.\r
+ if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)\r
+ return WidenVecOp_Convert(N);\r
+ InOp = GetWidenedVector(InOp);\r
+ assert(VT.getVectorNumElements() <\r
+ InOp.getValueType().getVectorNumElements() &&\r
+ "Input wasn't widened!");\r
+\r
+ // We may need to further widen the operand until it has the same total\r
+ // vector size as the result.\r
+ EVT InVT = InOp.getValueType();\r
+ if (InVT.getSizeInBits() != VT.getSizeInBits()) {\r
+ EVT InEltVT = InVT.getVectorElementType();\r
+ for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {\r
+ EVT FixedVT = (MVT::SimpleValueType)i;\r
+ EVT FixedEltVT = FixedVT.getVectorElementType();\r
+ if (TLI.isTypeLegal(FixedVT) &&\r
+ FixedVT.getSizeInBits() == VT.getSizeInBits() &&\r
+ FixedEltVT == InEltVT) {\r
+ assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&\r
+ "Not enough elements in the fixed type for the operand!");\r
+ assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&\r
+ "We can't have the same type as we started with!");\r
+ if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())\r
+ InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,\r
+ DAG.getUNDEF(FixedVT), InOp,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ else\r
+ InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ break;\r
+ }\r
+ }\r
+ InVT = InOp.getValueType();\r
+ if (InVT.getSizeInBits() != VT.getSizeInBits())\r
+ // We couldn't find a legal vector type that was a widening of the input\r
+ // and could be extended in-register to the result type, so we have to\r
+ // scalarize.\r
+ return WidenVecOp_Convert(N);\r
+ }\r
+\r
+ // Use special DAG nodes to represent the operation of extending the\r
+ // low lanes.\r
+ switch (N->getOpcode()) {\r
+ default:\r
+ llvm_unreachable("Extend legalization on on extend operation!");\r
+ case ISD::ANY_EXTEND:\r
+ return DAG.getAnyExtendVectorInReg(InOp, DL, VT);\r
+ case ISD::SIGN_EXTEND:\r
+ return DAG.getSignExtendVectorInReg(InOp, DL, VT);\r
+ case ISD::ZERO_EXTEND:\r
+ return DAG.getZeroExtendVectorInReg(InOp, DL, VT);\r
+ }\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {\r
+ // Since the result is legal and the input is illegal, it is unlikely\r
+ // that we can fix the input to a legal type so unroll the convert\r
+ // into some scalar code and create a nasty build vector.\r
+ EVT VT = N->getValueType(0);\r
+ EVT EltVT = VT.getVectorElementType();\r
+ SDLoc dl(N);\r
+ unsigned NumElts = VT.getVectorNumElements();\r
+ SDValue InOp = N->getOperand(0);\r
+ if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)\r
+ InOp = GetWidenedVector(InOp);\r
+ EVT InVT = InOp.getValueType();\r
+ EVT InEltVT = InVT.getVectorElementType();\r
+\r
+ unsigned Opcode = N->getOpcode();\r
+ SmallVector<SDValue, 16> Ops(NumElts);\r
+ for (unsigned i=0; i < NumElts; ++i)\r
+ Ops[i] = DAG.getNode(Opcode, dl, EltVT,\r
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,\r
+ DAG.getConstant(i, TLI.getVectorIdxTy())));\r
+\r
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {\r
+ EVT VT = N->getValueType(0);\r
+ SDValue InOp = GetWidenedVector(N->getOperand(0));\r
+ EVT InWidenVT = InOp.getValueType();\r
+ SDLoc dl(N);\r
+\r
+ // Check if we can convert between two legal vector types and extract.\r
+ unsigned InWidenSize = InWidenVT.getSizeInBits();\r
+ unsigned Size = VT.getSizeInBits();\r
+ // x86mmx is not an acceptable vector element type, so don't try.\r
+ if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {\r
+ unsigned NewNumElts = InWidenSize / Size;\r
+ EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);\r
+ if (TLI.isTypeLegal(NewVT)) {\r
+ SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);\r
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ }\r
+ }\r
+\r
+ return CreateStackStoreLoad(InOp, VT);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {\r
+ // If the input vector is not legal, it is likely that we will not find a\r
+ // legal vector of the same size. Replace the concatenate vector with a\r
+ // nasty build vector.\r
+ EVT VT = N->getValueType(0);\r
+ EVT EltVT = VT.getVectorElementType();\r
+ SDLoc dl(N);\r
+ unsigned NumElts = VT.getVectorNumElements();\r
+ SmallVector<SDValue, 16> Ops(NumElts);\r
+\r
+ EVT InVT = N->getOperand(0).getValueType();\r
+ unsigned NumInElts = InVT.getVectorNumElements();\r
+\r
+ unsigned Idx = 0;\r
+ unsigned NumOperands = N->getNumOperands();\r
+ for (unsigned i=0; i < NumOperands; ++i) {\r
+ SDValue InOp = N->getOperand(i);\r
+ if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)\r
+ InOp = GetWidenedVector(InOp);\r
+ for (unsigned j=0; j < NumInElts; ++j)\r
+ Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,\r
+ DAG.getConstant(j, TLI.getVectorIdxTy()));\r
+ }\r
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {\r
+ SDValue InOp = GetWidenedVector(N->getOperand(0));\r
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),\r
+ N->getValueType(0), InOp, N->getOperand(1));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {\r
+ SDValue InOp = GetWidenedVector(N->getOperand(0));\r
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),\r
+ N->getValueType(0), InOp, N->getOperand(1));\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {\r
+ // We have to widen the value but we want only to store the original\r
+ // vector type.\r
+ StoreSDNode *ST = cast<StoreSDNode>(N);\r
+\r
+ SmallVector<SDValue, 16> StChain;\r
+ if (ST->isTruncatingStore())\r
+ GenWidenVectorTruncStores(StChain, ST);\r
+ else\r
+ GenWidenVectorStores(StChain, ST);\r
+\r
+ if (StChain.size() == 1)\r
+ return StChain[0];\r
+ else\r
+ return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {\r
+ SDValue InOp0 = GetWidenedVector(N->getOperand(0));\r
+ SDValue InOp1 = GetWidenedVector(N->getOperand(1));\r
+ SDLoc dl(N);\r
+\r
+ // WARNING: In this code we widen the compare instruction with garbage.\r
+ // This garbage may contain denormal floats which may be slow. Is this a real\r
+ // concern ? Should we zero the unused lanes if this is a float compare ?\r
+\r
+ // Get a new SETCC node to compare the newly widened operands.\r
+ // Only some of the compared elements are legal.\r
+ EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());\r
+ SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),\r
+ SVT, InOp0, InOp1, N->getOperand(2));\r
+\r
+ // Extract the needed results from the result vector.\r
+ EVT ResVT = EVT::getVectorVT(*DAG.getContext(),\r
+ SVT.getVectorElementType(),\r
+ N->getValueType(0).getVectorNumElements());\r
+ SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,\r
+ ResVT, WideSETCC, DAG.getConstant(0,\r
+ TLI.getVectorIdxTy()));\r
+\r
+ return PromoteTargetBoolean(CC, N->getValueType(0));\r
+}\r
+\r
+\r
+//===----------------------------------------------------------------------===//\r
+// Vector Widening Utilities\r
+//===----------------------------------------------------------------------===//\r
+\r
+// Utility function to find the type to chop up a widen vector for load/store\r
+// TLI: Target lowering used to determine legal types.\r
+// Width: Width left need to load/store.\r
+// WidenVT: The widen vector type to load to/store from\r
+// Align: If 0, don't allow use of a wider type\r
+// WidenEx: If Align is not 0, the amount additional we can load/store from.\r
+\r
+static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,\r
+ unsigned Width, EVT WidenVT,\r
+ unsigned Align = 0, unsigned WidenEx = 0) {\r
+ EVT WidenEltVT = WidenVT.getVectorElementType();\r
+ unsigned WidenWidth = WidenVT.getSizeInBits();\r
+ unsigned WidenEltWidth = WidenEltVT.getSizeInBits();\r
+ unsigned AlignInBits = Align*8;\r
+\r
+ // If we have one element to load/store, return it.\r
+ EVT RetVT = WidenEltVT;\r
+ if (Width == WidenEltWidth)\r
+ return RetVT;\r
+\r
+ // See if there is larger legal integer than the element type to load/store\r
+ unsigned VT;\r
+ for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;\r
+ VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {\r
+ EVT MemVT((MVT::SimpleValueType) VT);\r
+ unsigned MemVTWidth = MemVT.getSizeInBits();\r
+ if (MemVT.getSizeInBits() <= WidenEltWidth)\r
+ break;\r
+ if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&\r
+ isPowerOf2_32(WidenWidth / MemVTWidth) &&\r
+ (MemVTWidth <= Width ||\r
+ (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {\r
+ RetVT = MemVT;\r
+ break;\r
+ }\r
+ }\r
+\r
+ // See if there is a larger vector type to load/store that has the same vector\r
+ // element type and is evenly divisible with the WidenVT.\r
+ for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;\r
+ VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {\r
+ EVT MemVT = (MVT::SimpleValueType) VT;\r
+ unsigned MemVTWidth = MemVT.getSizeInBits();\r
+ if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&\r
+ (WidenWidth % MemVTWidth) == 0 &&\r
+ isPowerOf2_32(WidenWidth / MemVTWidth) &&\r
+ (MemVTWidth <= Width ||\r
+ (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {\r
+ if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)\r
+ return MemVT;\r
+ }\r
+ }\r
+\r
+ return RetVT;\r
+}\r
+\r
+// Builds a vector type from scalar loads\r
+// VecTy: Resulting Vector type\r
+// LDOps: Load operators to build a vector type\r
+// [Start,End) the list of loads to use.\r
+static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,\r
+ SmallVectorImpl<SDValue> &LdOps,\r
+ unsigned Start, unsigned End) {\r
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();\r
+ SDLoc dl(LdOps[Start]);\r
+ EVT LdTy = LdOps[Start].getValueType();\r
+ unsigned Width = VecTy.getSizeInBits();\r
+ unsigned NumElts = Width / LdTy.getSizeInBits();\r
+ EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);\r
+\r
+ unsigned Idx = 1;\r
+ SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);\r
+\r
+ for (unsigned i = Start + 1; i != End; ++i) {\r
+ EVT NewLdTy = LdOps[i].getValueType();\r
+ if (NewLdTy != LdTy) {\r
+ NumElts = Width / NewLdTy.getSizeInBits();\r
+ NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);\r
+ VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);\r
+ // Readjust position and vector position based on new load type\r
+ Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();\r
+ LdTy = NewLdTy;\r
+ }\r
+ VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],\r
+ DAG.getConstant(Idx++, TLI.getVectorIdxTy()));\r
+ }\r
+ return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);\r
+}\r
+\r
+SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,\r
+ LoadSDNode *LD) {\r
+ // The strategy assumes that we can efficiently load powers of two widths.\r
+ // The routines chops the vector into the largest vector loads with the same\r
+ // element type or scalar loads and then recombines it to the widen vector\r
+ // type.\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));\r
+ unsigned WidenWidth = WidenVT.getSizeInBits();\r
+ EVT LdVT = LD->getMemoryVT();\r
+ SDLoc dl(LD);\r
+ assert(LdVT.isVector() && WidenVT.isVector());\r
+ assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());\r
+\r
+ // Load information\r
+ SDValue Chain = LD->getChain();\r
+ SDValue BasePtr = LD->getBasePtr();\r
+ unsigned Align = LD->getAlignment();\r
+ bool isVolatile = LD->isVolatile();\r
+ bool isNonTemporal = LD->isNonTemporal();\r
+ bool isInvariant = LD->isInvariant();\r
+ AAMDNodes AAInfo = LD->getAAInfo();\r
+\r
+ int LdWidth = LdVT.getSizeInBits();\r
+ int WidthDiff = WidenWidth - LdWidth; // Difference\r
+ unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads\r
+\r
+ // Find the vector type that can load from.\r
+ EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);\r
+ int NewVTWidth = NewVT.getSizeInBits();\r
+ SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),\r
+ isVolatile, isNonTemporal, isInvariant, Align,\r
+ AAInfo);\r
+ LdChain.push_back(LdOp.getValue(1));\r
+\r
+ // Check if we can load the element with one instruction\r
+ if (LdWidth <= NewVTWidth) {\r
+ if (!NewVT.isVector()) {\r
+ unsigned NumElts = WidenWidth / NewVTWidth;\r
+ EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);\r
+ SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);\r
+ return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);\r
+ }\r
+ if (NewVT == WidenVT)\r
+ return LdOp;\r
+\r
+ assert(WidenWidth % NewVTWidth == 0);\r
+ unsigned NumConcat = WidenWidth / NewVTWidth;\r
+ SmallVector<SDValue, 16> ConcatOps(NumConcat);\r
+ SDValue UndefVal = DAG.getUNDEF(NewVT);\r
+ ConcatOps[0] = LdOp;\r
+ for (unsigned i = 1; i != NumConcat; ++i)\r
+ ConcatOps[i] = UndefVal;\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);\r
+ }\r
+\r
+ // Load vector by using multiple loads from largest vector to scalar\r
+ SmallVector<SDValue, 16> LdOps;\r
+ LdOps.push_back(LdOp);\r
+\r
+ LdWidth -= NewVTWidth;\r
+ unsigned Offset = 0;\r
+\r
+ while (LdWidth > 0) {\r
+ unsigned Increment = NewVTWidth / 8;\r
+ Offset += Increment;\r
+ BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,\r
+ DAG.getConstant(Increment, BasePtr.getValueType()));\r
+\r
+ SDValue L;\r
+ if (LdWidth < NewVTWidth) {\r
+ // Our current type we are using is too large, find a better size\r
+ NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);\r
+ NewVTWidth = NewVT.getSizeInBits();\r
+ L = DAG.getLoad(NewVT, dl, Chain, BasePtr,\r
+ LD->getPointerInfo().getWithOffset(Offset), isVolatile,\r
+ isNonTemporal, isInvariant, MinAlign(Align, Increment),\r
+ AAInfo);\r
+ LdChain.push_back(L.getValue(1));\r
+ if (L->getValueType(0).isVector()) {\r
+ SmallVector<SDValue, 16> Loads;\r
+ Loads.push_back(L);\r
+ unsigned size = L->getValueSizeInBits(0);\r
+ while (size < LdOp->getValueSizeInBits(0)) {\r
+ Loads.push_back(DAG.getUNDEF(L->getValueType(0)));\r
+ size += L->getValueSizeInBits(0);\r
+ }\r
+ L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);\r
+ }\r
+ } else {\r
+ L = DAG.getLoad(NewVT, dl, Chain, BasePtr,\r
+ LD->getPointerInfo().getWithOffset(Offset), isVolatile,\r
+ isNonTemporal, isInvariant, MinAlign(Align, Increment),\r
+ AAInfo);\r
+ LdChain.push_back(L.getValue(1));\r
+ }\r
+\r
+ LdOps.push_back(L);\r
+\r
+\r
+ LdWidth -= NewVTWidth;\r
+ }\r
+\r
+ // Build the vector from the loads operations\r
+ unsigned End = LdOps.size();\r
+ if (!LdOps[0].getValueType().isVector())\r
+ // All the loads are scalar loads.\r
+ return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);\r
+\r
+ // If the load contains vectors, build the vector using concat vector.\r
+ // All of the vectors used to loads are power of 2 and the scalars load\r
+ // can be combined to make a power of 2 vector.\r
+ SmallVector<SDValue, 16> ConcatOps(End);\r
+ int i = End - 1;\r
+ int Idx = End;\r
+ EVT LdTy = LdOps[i].getValueType();\r
+ // First combine the scalar loads to a vector\r
+ if (!LdTy.isVector()) {\r
+ for (--i; i >= 0; --i) {\r
+ LdTy = LdOps[i].getValueType();\r
+ if (LdTy.isVector())\r
+ break;\r
+ }\r
+ ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);\r
+ }\r
+ ConcatOps[--Idx] = LdOps[i];\r
+ for (--i; i >= 0; --i) {\r
+ EVT NewLdTy = LdOps[i].getValueType();\r
+ if (NewLdTy != LdTy) {\r
+ // Create a larger vector\r
+ ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,\r
+ makeArrayRef(&ConcatOps[Idx], End - Idx));\r
+ Idx = End - 1;\r
+ LdTy = NewLdTy;\r
+ }\r
+ ConcatOps[--Idx] = LdOps[i];\r
+ }\r
+\r
+ if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,\r
+ makeArrayRef(&ConcatOps[Idx], End - Idx));\r
+\r
+ // We need to fill the rest with undefs to build the vector\r
+ unsigned NumOps = WidenWidth / LdTy.getSizeInBits();\r
+ SmallVector<SDValue, 16> WidenOps(NumOps);\r
+ SDValue UndefVal = DAG.getUNDEF(LdTy);\r
+ {\r
+ unsigned i = 0;\r
+ for (; i != End-Idx; ++i)\r
+ WidenOps[i] = ConcatOps[Idx+i];\r
+ for (; i != NumOps; ++i)\r
+ WidenOps[i] = UndefVal;\r
+ }\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);\r
+}\r
+\r
+SDValue\r
+DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,\r
+ LoadSDNode *LD,\r
+ ISD::LoadExtType ExtType) {\r
+ // For extension loads, it may not be more efficient to chop up the vector\r
+ // and then extended it. Instead, we unroll the load and build a new vector.\r
+ EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));\r
+ EVT LdVT = LD->getMemoryVT();\r
+ SDLoc dl(LD);\r
+ assert(LdVT.isVector() && WidenVT.isVector());\r
+\r
+ // Load information\r
+ SDValue Chain = LD->getChain();\r
+ SDValue BasePtr = LD->getBasePtr();\r
+ unsigned Align = LD->getAlignment();\r
+ bool isVolatile = LD->isVolatile();\r
+ bool isNonTemporal = LD->isNonTemporal();\r
+ bool isInvariant = LD->isInvariant();\r
+ AAMDNodes AAInfo = LD->getAAInfo();\r
+\r
+ EVT EltVT = WidenVT.getVectorElementType();\r
+ EVT LdEltVT = LdVT.getVectorElementType();\r
+ unsigned NumElts = LdVT.getVectorNumElements();\r
+\r
+ // Load each element and widen\r
+ unsigned WidenNumElts = WidenVT.getVectorNumElements();\r
+ SmallVector<SDValue, 16> Ops(WidenNumElts);\r
+ unsigned Increment = LdEltVT.getSizeInBits() / 8;\r
+ Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,\r
+ LD->getPointerInfo(),\r
+ LdEltVT, isVolatile, isNonTemporal, isInvariant,\r
+ Align, AAInfo);\r
+ LdChain.push_back(Ops[0].getValue(1));\r
+ unsigned i = 0, Offset = Increment;\r
+ for (i=1; i < NumElts; ++i, Offset += Increment) {\r
+ SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),\r
+ BasePtr,\r
+ DAG.getConstant(Offset,\r
+ BasePtr.getValueType()));\r
+ Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,\r
+ LD->getPointerInfo().getWithOffset(Offset), LdEltVT,\r
+ isVolatile, isNonTemporal, isInvariant, Align,\r
+ AAInfo);\r
+ LdChain.push_back(Ops[i].getValue(1));\r
+ }\r
+\r
+ // Fill the rest with undefs\r
+ SDValue UndefVal = DAG.getUNDEF(EltVT);\r
+ for (; i != WidenNumElts; ++i)\r
+ Ops[i] = UndefVal;\r
+\r
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);\r
+}\r
+\r
+\r
+void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,\r
+ StoreSDNode *ST) {\r
+ // The strategy assumes that we can efficiently store powers of two widths.\r
+ // The routines chops the vector into the largest vector stores with the same\r
+ // element type or scalar stores.\r
+ SDValue Chain = ST->getChain();\r
+ SDValue BasePtr = ST->getBasePtr();\r
+ unsigned Align = ST->getAlignment();\r
+ bool isVolatile = ST->isVolatile();\r
+ bool isNonTemporal = ST->isNonTemporal();\r
+ AAMDNodes AAInfo = ST->getAAInfo();\r
+ SDValue ValOp = GetWidenedVector(ST->getValue());\r
+ SDLoc dl(ST);\r
+\r
+ EVT StVT = ST->getMemoryVT();\r
+ unsigned StWidth = StVT.getSizeInBits();\r
+ EVT ValVT = ValOp.getValueType();\r
+ unsigned ValWidth = ValVT.getSizeInBits();\r
+ EVT ValEltVT = ValVT.getVectorElementType();\r
+ unsigned ValEltWidth = ValEltVT.getSizeInBits();\r
+ assert(StVT.getVectorElementType() == ValEltVT);\r
+\r
+ int Idx = 0; // current index to store\r
+ unsigned Offset = 0; // offset from base to store\r
+ while (StWidth != 0) {\r
+ // Find the largest vector type we can store with\r
+ EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);\r
+ unsigned NewVTWidth = NewVT.getSizeInBits();\r
+ unsigned Increment = NewVTWidth / 8;\r
+ if (NewVT.isVector()) {\r
+ unsigned NumVTElts = NewVT.getVectorNumElements();\r
+ do {\r
+ SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,\r
+ DAG.getConstant(Idx, TLI.getVectorIdxTy()));\r
+ StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,\r
+ ST->getPointerInfo().getWithOffset(Offset),\r
+ isVolatile, isNonTemporal,\r
+ MinAlign(Align, Offset), AAInfo));\r
+ StWidth -= NewVTWidth;\r
+ Offset += Increment;\r
+ Idx += NumVTElts;\r
+ BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,\r
+ DAG.getConstant(Increment, BasePtr.getValueType()));\r
+ } while (StWidth != 0 && StWidth >= NewVTWidth);\r
+ } else {\r
+ // Cast the vector to the scalar type we can store\r
+ unsigned NumElts = ValWidth / NewVTWidth;\r
+ EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);\r
+ SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);\r
+ // Readjust index position based on new vector type\r
+ Idx = Idx * ValEltWidth / NewVTWidth;\r
+ do {\r
+ SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,\r
+ DAG.getConstant(Idx++, TLI.getVectorIdxTy()));\r
+ StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,\r
+ ST->getPointerInfo().getWithOffset(Offset),\r
+ isVolatile, isNonTemporal,\r
+ MinAlign(Align, Offset), AAInfo));\r
+ StWidth -= NewVTWidth;\r
+ Offset += Increment;\r
+ BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,\r
+ DAG.getConstant(Increment, BasePtr.getValueType()));\r
+ } while (StWidth != 0 && StWidth >= NewVTWidth);\r
+ // Restore index back to be relative to the original widen element type\r
+ Idx = Idx * NewVTWidth / ValEltWidth;\r
+ }\r
+ }\r
+}\r
+\r
+void\r
+DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,\r
+ StoreSDNode *ST) {\r
+ // For extension loads, it may not be more efficient to truncate the vector\r
+ // and then store it. Instead, we extract each element and then store it.\r
+ SDValue Chain = ST->getChain();\r
+ SDValue BasePtr = ST->getBasePtr();\r
+ unsigned Align = ST->getAlignment();\r
+ bool isVolatile = ST->isVolatile();\r
+ bool isNonTemporal = ST->isNonTemporal();\r
+ AAMDNodes AAInfo = ST->getAAInfo();\r
+ SDValue ValOp = GetWidenedVector(ST->getValue());\r
+ SDLoc dl(ST);\r
+\r
+ EVT StVT = ST->getMemoryVT();\r
+ EVT ValVT = ValOp.getValueType();\r
+\r
+ // It must be true that we the widen vector type is bigger than where\r
+ // we need to store.\r
+ assert(StVT.isVector() && ValOp.getValueType().isVector());\r
+ assert(StVT.bitsLT(ValOp.getValueType()));\r
+\r
+ // For truncating stores, we can not play the tricks of chopping legal\r
+ // vector types and bit cast it to the right type. Instead, we unroll\r
+ // the store.\r
+ EVT StEltVT = StVT.getVectorElementType();\r
+ EVT ValEltVT = ValVT.getVectorElementType();\r
+ unsigned Increment = ValEltVT.getSizeInBits() / 8;\r
+ unsigned NumElts = StVT.getVectorNumElements();\r
+ SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,\r
+ ST->getPointerInfo(), StEltVT,\r
+ isVolatile, isNonTemporal, Align,\r
+ AAInfo));\r
+ unsigned Offset = Increment;\r
+ for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {\r
+ SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),\r
+ BasePtr, DAG.getConstant(Offset,\r
+ BasePtr.getValueType()));\r
+ SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+ StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,\r
+ ST->getPointerInfo().getWithOffset(Offset),\r
+ StEltVT, isVolatile, isNonTemporal,\r
+ MinAlign(Align, Offset), AAInfo));\r
+ }\r
+}\r
+\r
+/// Modifies a vector input (widen or narrows) to a vector of NVT. The\r
+/// input vector must have the same element type as NVT.\r
+SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {\r
+ // Note that InOp might have been widened so it might already have\r
+ // the right width or it might need be narrowed.\r
+ EVT InVT = InOp.getValueType();\r
+ assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&\r
+ "input and widen element type must match");\r
+ SDLoc dl(InOp);\r
+\r
+ // Check if InOp already has the right width.\r
+ if (InVT == NVT)\r
+ return InOp;\r
+\r
+ unsigned InNumElts = InVT.getVectorNumElements();\r
+ unsigned WidenNumElts = NVT.getVectorNumElements();\r
+ if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {\r
+ unsigned NumConcat = WidenNumElts / InNumElts;\r
+ SmallVector<SDValue, 16> Ops(NumConcat);\r
+ SDValue UndefVal = DAG.getUNDEF(InVT);\r
+ Ops[0] = InOp;\r
+ for (unsigned i = 1; i != NumConcat; ++i)\r
+ Ops[i] = UndefVal;\r
+\r
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);\r
+ }\r
+\r
+ if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)\r
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,\r
+ DAG.getConstant(0, TLI.getVectorIdxTy()));\r
+\r
+ // Fall back to extract and build.\r
+ SmallVector<SDValue, 16> Ops(WidenNumElts);\r
+ EVT EltVT = NVT.getVectorElementType();\r
+ unsigned MinNumElts = std::min(WidenNumElts, InNumElts);\r
+ unsigned Idx;\r
+ for (Idx = 0; Idx < MinNumElts; ++Idx)\r
+ Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,\r
+ DAG.getConstant(Idx, TLI.getVectorIdxTy()));\r
+\r
+ SDValue UndefVal = DAG.getUNDEF(EltVT);\r
+ for ( ; Idx < WidenNumElts; ++Idx)\r
+ Ops[Idx] = UndefVal;\r
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);\r
+}\r
projects / oota-llvm.git / commitdiff