1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
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3 // The LLVM Compiler Infrastructure
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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8 //===----------------------------------------------------------------------===//
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10 // This file performs vector type splitting and scalarization for LegalizeTypes.
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11 // Scalarization is the act of changing a computation in an illegal one-element
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12 // vector type to be a computation in its scalar element type. For example,
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13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
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14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
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15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
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17 // Splitting is the act of changing a computation in an invalid vector type to
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18 // be a computation in two vectors of half the size. For example, implementing
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19 // <128 x f32> operations in terms of two <64 x f32> operations.
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21 //===----------------------------------------------------------------------===//
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23 #include "LegalizeTypes.h"
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24 #include "llvm/IR/DataLayout.h"
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25 #include "llvm/Support/ErrorHandling.h"
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26 #include "llvm/Support/raw_ostream.h"
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27 using namespace llvm;
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29 #define DEBUG_TYPE "legalize-types"
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31 //===----------------------------------------------------------------------===//
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32 // Result Vector Scalarization: <1 x ty> -> ty.
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33 //===----------------------------------------------------------------------===//
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35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
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36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
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39 SDValue R = SDValue();
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41 switch (N->getOpcode()) {
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44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
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48 report_fatal_error("Do not know how to scalarize the result of this "
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51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
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52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
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53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
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54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
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55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
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56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
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57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
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58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
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59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
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60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
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61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
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62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
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63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
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64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
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65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
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66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
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67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
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68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
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69 case ISD::ANY_EXTEND:
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72 case ISD::CTLZ_ZERO_UNDEF:
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75 case ISD::CTTZ_ZERO_UNDEF:
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85 case ISD::FNEARBYINT:
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87 case ISD::FP_EXTEND:
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88 case ISD::FP_TO_SINT:
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89 case ISD::FP_TO_UINT:
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95 case ISD::SIGN_EXTEND:
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96 case ISD::SINT_TO_FP:
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98 case ISD::UINT_TO_FP:
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99 case ISD::ZERO_EXTEND:
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100 R = ScalarizeVecRes_UnaryOp(N);
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106 case ISD::FCOPYSIGN:
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126 R = ScalarizeVecRes_BinOp(N);
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129 R = ScalarizeVecRes_TernaryOp(N);
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133 // If R is null, the sub-method took care of registering the result.
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135 SetScalarizedVector(SDValue(N, ResNo), R);
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138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
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139 SDValue LHS = GetScalarizedVector(N->getOperand(0));
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140 SDValue RHS = GetScalarizedVector(N->getOperand(1));
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141 return DAG.getNode(N->getOpcode(), SDLoc(N),
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142 LHS.getValueType(), LHS, RHS);
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145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
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146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
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147 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
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148 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
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149 return DAG.getNode(N->getOpcode(), SDLoc(N),
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150 Op0.getValueType(), Op0, Op1, Op2);
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153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
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155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
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156 return GetScalarizedVector(Op);
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159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
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160 EVT NewVT = N->getValueType(0).getVectorElementType();
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161 return DAG.getNode(ISD::BITCAST, SDLoc(N),
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162 NewVT, N->getOperand(0));
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165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
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166 EVT EltVT = N->getValueType(0).getVectorElementType();
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167 SDValue InOp = N->getOperand(0);
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168 // The BUILD_VECTOR operands may be of wider element types and
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169 // we may need to truncate them back to the requested return type.
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170 if (EltVT.isInteger())
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171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
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175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
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176 EVT NewVT = N->getValueType(0).getVectorElementType();
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177 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
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178 return DAG.getConvertRndSat(NewVT, SDLoc(N),
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179 Op0, DAG.getValueType(NewVT),
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180 DAG.getValueType(Op0.getValueType()),
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183 cast<CvtRndSatSDNode>(N)->getCvtCode());
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186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
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187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
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188 N->getValueType(0).getVectorElementType(),
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189 N->getOperand(0), N->getOperand(1));
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192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
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193 EVT NewVT = N->getValueType(0).getVectorElementType();
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194 SDValue Op = GetScalarizedVector(N->getOperand(0));
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195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
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196 NewVT, Op, N->getOperand(1));
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199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
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200 SDValue Op = GetScalarizedVector(N->getOperand(0));
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201 return DAG.getNode(ISD::FPOWI, SDLoc(N),
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202 Op.getValueType(), Op, N->getOperand(1));
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205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
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206 // The value to insert may have a wider type than the vector element type,
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207 // so be sure to truncate it to the element type if necessary.
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208 SDValue Op = N->getOperand(1);
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209 EVT EltVT = N->getValueType(0).getVectorElementType();
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210 if (Op.getValueType() != EltVT)
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211 // FIXME: Can this happen for floating point types?
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212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
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216 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
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217 assert(N->isUnindexed() && "Indexed vector load?");
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219 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
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220 N->getExtensionType(),
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221 N->getValueType(0).getVectorElementType(),
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223 N->getChain(), N->getBasePtr(),
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224 DAG.getUNDEF(N->getBasePtr().getValueType()),
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225 N->getPointerInfo(),
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226 N->getMemoryVT().getVectorElementType(),
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227 N->isVolatile(), N->isNonTemporal(),
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228 N->isInvariant(), N->getOriginalAlignment(),
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231 // Legalized the chain result - switch anything that used the old chain to
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232 // use the new one.
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233 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
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237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
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238 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
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239 EVT DestVT = N->getValueType(0).getVectorElementType();
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240 SDValue Op = N->getOperand(0);
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241 EVT OpVT = Op.getValueType();
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243 // The result needs scalarizing, but it's not a given that the source does.
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244 // This is a workaround for targets where it's impossible to scalarize the
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245 // result of a conversion, because the source type is legal.
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246 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
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247 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
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248 // legal and was not scalarized.
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249 // See the similar logic in ScalarizeVecRes_VSETCC
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250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
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251 Op = GetScalarizedVector(Op);
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253 EVT VT = OpVT.getVectorElementType();
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254 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
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255 DAG.getConstant(0, TLI.getVectorIdxTy()));
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257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
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260 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
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261 EVT EltVT = N->getValueType(0).getVectorElementType();
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262 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
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263 SDValue LHS = GetScalarizedVector(N->getOperand(0));
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264 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
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265 LHS, DAG.getValueType(ExtVT));
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268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
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269 // If the operand is wider than the vector element type then it is implicitly
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270 // truncated. Make that explicit here.
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271 EVT EltVT = N->getValueType(0).getVectorElementType();
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272 SDValue InOp = N->getOperand(0);
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273 if (InOp.getValueType() != EltVT)
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274 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
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278 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
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279 SDValue Cond = GetScalarizedVector(N->getOperand(0));
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280 SDValue LHS = GetScalarizedVector(N->getOperand(1));
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281 TargetLowering::BooleanContent ScalarBool =
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282 TLI.getBooleanContents(false, false);
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283 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
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285 // If integer and float booleans have different contents then we can't
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286 // reliably optimize in all cases. There is a full explanation for this in
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287 // DAGCombiner::visitSELECT() where the same issue affects folding
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288 // (select C, 0, 1) to (xor C, 1).
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289 if (TLI.getBooleanContents(false, false) !=
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290 TLI.getBooleanContents(false, true)) {
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291 // At least try the common case where the boolean is generated by a
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293 if (Cond->getOpcode() == ISD::SETCC) {
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294 EVT OpVT = Cond->getOperand(0)->getValueType(0);
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295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
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296 VecBool = TLI.getBooleanContents(OpVT);
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298 ScalarBool = TargetLowering::UndefinedBooleanContent;
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301 if (ScalarBool != VecBool) {
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302 EVT CondVT = Cond.getValueType();
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303 switch (ScalarBool) {
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304 case TargetLowering::UndefinedBooleanContent:
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306 case TargetLowering::ZeroOrOneBooleanContent:
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307 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
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308 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
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309 // Vector read from all ones, scalar expects a single 1 so mask.
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310 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
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311 Cond, DAG.getConstant(1, CondVT));
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313 case TargetLowering::ZeroOrNegativeOneBooleanContent:
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314 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
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315 VecBool == TargetLowering::ZeroOrOneBooleanContent);
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316 // Vector reads from a one, scalar from all ones so sign extend.
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317 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
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318 Cond, DAG.getValueType(MVT::i1));
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323 return DAG.getSelect(SDLoc(N),
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324 LHS.getValueType(), Cond, LHS,
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325 GetScalarizedVector(N->getOperand(2)));
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328 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
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329 SDValue LHS = GetScalarizedVector(N->getOperand(1));
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330 return DAG.getSelect(SDLoc(N),
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331 LHS.getValueType(), N->getOperand(0), LHS,
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332 GetScalarizedVector(N->getOperand(2)));
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335 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
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336 SDValue LHS = GetScalarizedVector(N->getOperand(2));
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337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
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338 N->getOperand(0), N->getOperand(1),
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339 LHS, GetScalarizedVector(N->getOperand(3)),
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343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
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344 assert(N->getValueType(0).isVector() ==
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345 N->getOperand(0).getValueType().isVector() &&
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346 "Scalar/Vector type mismatch");
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348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
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350 SDValue LHS = GetScalarizedVector(N->getOperand(0));
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351 SDValue RHS = GetScalarizedVector(N->getOperand(1));
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354 // Turn it into a scalar SETCC.
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355 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
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358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
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359 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
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362 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
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363 // Figure out if the scalar is the LHS or RHS and return it.
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364 SDValue Arg = N->getOperand(2).getOperand(0);
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365 if (Arg.getOpcode() == ISD::UNDEF)
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366 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
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367 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
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368 return GetScalarizedVector(N->getOperand(Op));
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371 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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372 assert(N->getValueType(0).isVector() &&
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373 N->getOperand(0).getValueType().isVector() &&
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374 "Operand types must be vectors");
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375 SDValue LHS = N->getOperand(0);
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376 SDValue RHS = N->getOperand(1);
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377 EVT OpVT = LHS.getValueType();
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378 EVT NVT = N->getValueType(0).getVectorElementType();
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381 // The result needs scalarizing, but it's not a given that the source does.
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382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
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383 LHS = GetScalarizedVector(LHS);
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384 RHS = GetScalarizedVector(RHS);
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386 EVT VT = OpVT.getVectorElementType();
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387 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
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388 DAG.getConstant(0, TLI.getVectorIdxTy()));
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389 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
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390 DAG.getConstant(0, TLI.getVectorIdxTy()));
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393 // Turn it into a scalar SETCC.
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394 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
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396 // Vectors may have a different boolean contents to scalars. Promote the
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397 // value appropriately.
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398 ISD::NodeType ExtendCode =
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399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
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400 return DAG.getNode(ExtendCode, DL, NVT, Res);
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404 //===----------------------------------------------------------------------===//
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405 // Operand Vector Scalarization <1 x ty> -> ty.
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406 //===----------------------------------------------------------------------===//
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408 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
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409 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
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412 SDValue Res = SDValue();
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414 if (!Res.getNode()) {
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415 switch (N->getOpcode()) {
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418 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
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422 llvm_unreachable("Do not know how to scalarize this operator's operand!");
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424 Res = ScalarizeVecOp_BITCAST(N);
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426 case ISD::ANY_EXTEND:
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427 case ISD::ZERO_EXTEND:
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428 case ISD::SIGN_EXTEND:
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429 case ISD::TRUNCATE:
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430 case ISD::FP_TO_SINT:
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431 case ISD::FP_TO_UINT:
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432 case ISD::SINT_TO_FP:
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433 case ISD::UINT_TO_FP:
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434 Res = ScalarizeVecOp_UnaryOp(N);
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436 case ISD::CONCAT_VECTORS:
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437 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
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439 case ISD::EXTRACT_VECTOR_ELT:
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440 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
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443 Res = ScalarizeVecOp_VSELECT(N);
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446 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
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448 case ISD::FP_ROUND:
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449 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
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454 // If the result is null, the sub-method took care of registering results etc.
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455 if (!Res.getNode()) return false;
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457 // If the result is N, the sub-method updated N in place. Tell the legalizer
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458 // core about this.
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459 if (Res.getNode() == N)
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462 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
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463 "Invalid operand expansion");
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465 ReplaceValueWith(SDValue(N, 0), Res);
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469 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
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470 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
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471 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
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472 SDValue Elt = GetScalarizedVector(N->getOperand(0));
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473 return DAG.getNode(ISD::BITCAST, SDLoc(N),
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474 N->getValueType(0), Elt);
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477 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
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478 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
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479 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
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480 assert(N->getValueType(0).getVectorNumElements() == 1 &&
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481 "Unexpected vector type!");
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482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
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483 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
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484 N->getValueType(0).getScalarType(), Elt);
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485 // Revectorize the result so the types line up with what the uses of this
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486 // expression expect.
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487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
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490 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
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491 /// use a BUILD_VECTOR instead.
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492 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
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493 SmallVector<SDValue, 8> Ops(N->getNumOperands());
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494 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
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495 Ops[i] = GetScalarizedVector(N->getOperand(i));
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496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
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499 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
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500 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
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502 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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503 SDValue Res = GetScalarizedVector(N->getOperand(0));
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504 if (Res.getValueType() != N->getValueType(0))
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505 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
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511 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
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512 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
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513 /// (still with vector output type since that was acceptable if we got here).
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514 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
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515 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
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516 EVT VT = N->getValueType(0);
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518 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
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522 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
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523 /// scalarized, it must be <1 x ty>. Just store the element.
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524 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
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525 assert(N->isUnindexed() && "Indexed store of one-element vector?");
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526 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
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529 if (N->isTruncatingStore())
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530 return DAG.getTruncStore(N->getChain(), dl,
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531 GetScalarizedVector(N->getOperand(1)),
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532 N->getBasePtr(), N->getPointerInfo(),
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533 N->getMemoryVT().getVectorElementType(),
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534 N->isVolatile(), N->isNonTemporal(),
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535 N->getAlignment(), N->getAAInfo());
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537 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
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538 N->getBasePtr(), N->getPointerInfo(),
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539 N->isVolatile(), N->isNonTemporal(),
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540 N->getOriginalAlignment(), N->getAAInfo());
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543 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
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544 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
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545 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
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546 SDValue Elt = GetScalarizedVector(N->getOperand(0));
\r
547 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
\r
548 N->getValueType(0).getVectorElementType(), Elt,
\r
550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
\r
553 //===----------------------------------------------------------------------===//
\r
554 // Result Vector Splitting
\r
555 //===----------------------------------------------------------------------===//
\r
557 /// SplitVectorResult - This method is called when the specified result of the
\r
558 /// specified node is found to need vector splitting. At this point, the node
\r
559 /// may also have invalid operands or may have other results that need
\r
560 /// legalization, we just know that (at least) one result needs vector
\r
562 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
\r
563 DEBUG(dbgs() << "Split node result: ";
\r
568 // See if the target wants to custom expand this node.
\r
569 if (CustomLowerNode(N, N->getValueType(ResNo), true))
\r
572 switch (N->getOpcode()) {
\r
575 dbgs() << "SplitVectorResult #" << ResNo << ": ";
\r
579 report_fatal_error("Do not know how to split the result of this "
\r
582 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
\r
584 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
\r
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
\r
586 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
\r
587 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
\r
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
\r
589 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
\r
590 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
\r
591 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
\r
592 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
\r
593 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
\r
594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
\r
595 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
\r
596 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
\r
598 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
\r
601 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
\r
604 SplitVecRes_SETCC(N, Lo, Hi);
\r
606 case ISD::VECTOR_SHUFFLE:
\r
607 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
\r
611 case ISD::CONVERT_RNDSAT:
\r
614 case ISD::CTLZ_ZERO_UNDEF:
\r
615 case ISD::CTTZ_ZERO_UNDEF:
\r
626 case ISD::FNEARBYINT:
\r
628 case ISD::FP_EXTEND:
\r
629 case ISD::FP_ROUND:
\r
630 case ISD::FP_TO_SINT:
\r
631 case ISD::FP_TO_UINT:
\r
637 case ISD::SINT_TO_FP:
\r
638 case ISD::TRUNCATE:
\r
639 case ISD::UINT_TO_FP:
\r
640 SplitVecRes_UnaryOp(N, Lo, Hi);
\r
643 case ISD::ANY_EXTEND:
\r
644 case ISD::SIGN_EXTEND:
\r
645 case ISD::ZERO_EXTEND:
\r
646 SplitVecRes_ExtendOp(N, Lo, Hi);
\r
653 case ISD::FCOPYSIGN:
\r
671 SplitVecRes_BinOp(N, Lo, Hi);
\r
674 SplitVecRes_TernaryOp(N, Lo, Hi);
\r
678 // If Lo/Hi is null, the sub-method took care of registering results etc.
\r
680 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
\r
683 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
\r
685 SDValue LHSLo, LHSHi;
\r
686 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
\r
687 SDValue RHSLo, RHSHi;
\r
688 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
\r
691 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
\r
692 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
\r
695 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
\r
697 SDValue Op0Lo, Op0Hi;
\r
698 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
\r
699 SDValue Op1Lo, Op1Hi;
\r
700 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
\r
701 SDValue Op2Lo, Op2Hi;
\r
702 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
\r
705 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
\r
706 Op0Lo, Op1Lo, Op2Lo);
\r
707 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
\r
708 Op0Hi, Op1Hi, Op2Hi);
\r
711 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
\r
713 // We know the result is a vector. The input may be either a vector or a
\r
716 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
\r
719 SDValue InOp = N->getOperand(0);
\r
720 EVT InVT = InOp.getValueType();
\r
722 // Handle some special cases efficiently.
\r
723 switch (getTypeAction(InVT)) {
\r
724 case TargetLowering::TypeLegal:
\r
725 case TargetLowering::TypePromoteInteger:
\r
726 case TargetLowering::TypeSoftenFloat:
\r
727 case TargetLowering::TypeScalarizeVector:
\r
728 case TargetLowering::TypeWidenVector:
\r
730 case TargetLowering::TypeExpandInteger:
\r
731 case TargetLowering::TypeExpandFloat:
\r
732 // A scalar to vector conversion, where the scalar needs expansion.
\r
733 // If the vector is being split in two then we can just convert the
\r
734 // expanded pieces.
\r
735 if (LoVT == HiVT) {
\r
736 GetExpandedOp(InOp, Lo, Hi);
\r
737 if (TLI.isBigEndian())
\r
739 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
\r
740 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
\r
744 case TargetLowering::TypeSplitVector:
\r
745 // If the input is a vector that needs to be split, convert each split
\r
746 // piece of the input now.
\r
747 GetSplitVector(InOp, Lo, Hi);
\r
748 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
\r
749 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
\r
753 // In the general case, convert the input to an integer and split it by hand.
\r
754 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
\r
755 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
\r
756 if (TLI.isBigEndian())
\r
757 std::swap(LoIntVT, HiIntVT);
\r
759 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
\r
761 if (TLI.isBigEndian())
\r
763 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
\r
764 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
\r
767 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
\r
771 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
\r
772 unsigned LoNumElts = LoVT.getVectorNumElements();
\r
773 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
\r
774 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
\r
776 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
\r
777 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
\r
780 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
\r
782 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
\r
784 unsigned NumSubvectors = N->getNumOperands() / 2;
\r
785 if (NumSubvectors == 1) {
\r
786 Lo = N->getOperand(0);
\r
787 Hi = N->getOperand(1);
\r
792 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
\r
794 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
\r
795 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
\r
797 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
\r
798 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
\r
801 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
\r
803 SDValue Vec = N->getOperand(0);
\r
804 SDValue Idx = N->getOperand(1);
\r
808 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
\r
810 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
\r
811 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
\r
812 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
\r
813 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(),
\r
814 TLI.getVectorIdxTy()));
\r
817 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
\r
819 SDValue Vec = N->getOperand(0);
\r
820 SDValue SubVec = N->getOperand(1);
\r
821 SDValue Idx = N->getOperand(2);
\r
823 GetSplitVector(Vec, Lo, Hi);
\r
825 // Spill the vector to the stack.
\r
826 EVT VecVT = Vec.getValueType();
\r
827 EVT SubVecVT = VecVT.getVectorElementType();
\r
828 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
\r
829 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
\r
830 MachinePointerInfo(), false, false, 0);
\r
832 // Store the new subvector into the specified index.
\r
833 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
\r
834 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
\r
835 unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
\r
836 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
\r
839 // Load the Lo part from the stack slot.
\r
840 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
\r
841 false, false, false, 0);
\r
843 // Increment the pointer to the other part.
\r
844 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
\r
846 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
\r
847 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
\r
849 // Load the Hi part from the stack slot.
\r
850 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
\r
851 false, false, false, MinAlign(Alignment, IncrementSize));
\r
854 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
\r
857 GetSplitVector(N->getOperand(0), Lo, Hi);
\r
858 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
\r
859 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
\r
862 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
\r
864 SDValue LHSLo, LHSHi;
\r
865 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
\r
869 std::tie(LoVT, HiVT) =
\r
870 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
\r
872 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
\r
873 DAG.getValueType(LoVT));
\r
874 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
\r
875 DAG.getValueType(HiVT));
\r
878 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
\r
880 SDValue Vec = N->getOperand(0);
\r
881 SDValue Elt = N->getOperand(1);
\r
882 SDValue Idx = N->getOperand(2);
\r
884 GetSplitVector(Vec, Lo, Hi);
\r
886 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
\r
887 unsigned IdxVal = CIdx->getZExtValue();
\r
888 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
\r
889 if (IdxVal < LoNumElts)
\r
890 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
\r
891 Lo.getValueType(), Lo, Elt, Idx);
\r
893 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
\r
894 DAG.getConstant(IdxVal - LoNumElts,
\r
895 TLI.getVectorIdxTy()));
\r
899 // See if the target wants to custom expand this node.
\r
900 if (CustomLowerNode(N, N->getValueType(0), true))
\r
903 // Spill the vector to the stack.
\r
904 EVT VecVT = Vec.getValueType();
\r
905 EVT EltVT = VecVT.getVectorElementType();
\r
906 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
\r
907 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
\r
908 MachinePointerInfo(), false, false, 0);
\r
910 // Store the new element. This may be larger than the vector element type,
\r
911 // so use a truncating store.
\r
912 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
\r
913 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
\r
914 unsigned Alignment =
\r
915 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
\r
916 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
\r
919 // Load the Lo part from the stack slot.
\r
920 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
\r
921 false, false, false, 0);
\r
923 // Increment the pointer to the other part.
\r
924 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
\r
925 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
\r
926 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
\r
928 // Load the Hi part from the stack slot.
\r
929 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
\r
930 false, false, false, MinAlign(Alignment, IncrementSize));
\r
933 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
\r
937 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
\r
938 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
\r
939 Hi = DAG.getUNDEF(HiVT);
\r
942 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
\r
944 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
\r
947 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
\r
949 ISD::LoadExtType ExtType = LD->getExtensionType();
\r
950 SDValue Ch = LD->getChain();
\r
951 SDValue Ptr = LD->getBasePtr();
\r
952 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
\r
953 EVT MemoryVT = LD->getMemoryVT();
\r
954 unsigned Alignment = LD->getOriginalAlignment();
\r
955 bool isVolatile = LD->isVolatile();
\r
956 bool isNonTemporal = LD->isNonTemporal();
\r
957 bool isInvariant = LD->isInvariant();
\r
958 AAMDNodes AAInfo = LD->getAAInfo();
\r
960 EVT LoMemVT, HiMemVT;
\r
961 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
\r
963 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
\r
964 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
\r
965 isInvariant, Alignment, AAInfo);
\r
967 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
\r
968 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
\r
969 DAG.getConstant(IncrementSize, Ptr.getValueType()));
\r
970 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
\r
971 LD->getPointerInfo().getWithOffset(IncrementSize),
\r
972 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
\r
975 // Build a factor node to remember that this load is independent of the
\r
977 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
\r
980 // Legalized the chain result - switch anything that used the old chain to
\r
981 // use the new one.
\r
982 ReplaceValueWith(SDValue(LD, 1), Ch);
\r
985 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
\r
986 SDValue &Lo, SDValue &Hi) {
\r
989 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
\r
991 SDValue Ch = MLD->getChain();
\r
992 SDValue Ptr = MLD->getBasePtr();
\r
993 SDValue Mask = MLD->getMask();
\r
994 unsigned Alignment = MLD->getOriginalAlignment();
\r
996 // if Alignment is equal to the vector size,
\r
997 // take the half of it for the second part
\r
998 unsigned SecondHalfAlignment =
\r
999 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
\r
1000 Alignment/2 : Alignment;
\r
1002 SDValue MaskLo, MaskHi;
\r
1003 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
\r
1005 EVT MemoryVT = MLD->getMemoryVT();
\r
1006 EVT LoMemVT, HiMemVT;
\r
1007 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
\r
1009 SDValue Src0 = MLD->getSrc0();
\r
1010 SDValue Src0Lo, Src0Hi;
\r
1011 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
\r
1013 MachineMemOperand *MMO = DAG.getMachineFunction().
\r
1014 getMachineMemOperand(MLD->getPointerInfo(),
\r
1015 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
\r
1016 Alignment, MLD->getAAInfo(), MLD->getRanges());
\r
1018 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, MMO);
\r
1020 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
\r
1021 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
\r
1022 DAG.getConstant(IncrementSize, Ptr.getValueType()));
\r
1024 MMO = DAG.getMachineFunction().
\r
1025 getMachineMemOperand(MLD->getPointerInfo(),
\r
1026 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
\r
1027 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
\r
1029 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, MMO);
\r
1032 // Build a factor node to remember that this load is independent of the
\r
1034 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
\r
1037 // Legalized the chain result - switch anything that used the old chain to
\r
1038 // use the new one.
\r
1039 ReplaceValueWith(SDValue(MLD, 1), Ch);
\r
1043 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
\r
1044 assert(N->getValueType(0).isVector() &&
\r
1045 N->getOperand(0).getValueType().isVector() &&
\r
1046 "Operand types must be vectors");
\r
1050 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
\r
1052 // Split the input.
\r
1053 SDValue LL, LH, RL, RH;
\r
1054 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
\r
1055 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
\r
1057 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
\r
1058 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
\r
1061 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
\r
1063 // Get the dest types - they may not match the input types, e.g. int_to_fp.
\r
1066 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
\r
1068 // If the input also splits, handle it directly for a compile time speedup.
\r
1069 // Otherwise split it by hand.
\r
1070 EVT InVT = N->getOperand(0).getValueType();
\r
1071 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
\r
1072 GetSplitVector(N->getOperand(0), Lo, Hi);
\r
1074 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
\r
1076 if (N->getOpcode() == ISD::FP_ROUND) {
\r
1077 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
\r
1078 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
\r
1079 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
\r
1080 SDValue DTyOpLo = DAG.getValueType(LoVT);
\r
1081 SDValue DTyOpHi = DAG.getValueType(HiVT);
\r
1082 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
\r
1083 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
\r
1084 SDValue RndOp = N->getOperand(3);
\r
1085 SDValue SatOp = N->getOperand(4);
\r
1086 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
\r
1087 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
\r
1089 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
\r
1092 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
\r
1093 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
\r
1097 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
\r
1100 EVT SrcVT = N->getOperand(0).getValueType();
\r
1101 EVT DestVT = N->getValueType(0);
\r
1103 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
\r
1105 // We can do better than a generic split operation if the extend is doing
\r
1106 // more than just doubling the width of the elements and the following are
\r
1108 // - The number of vector elements is even,
\r
1109 // - the source type is legal,
\r
1110 // - the type of a split source is illegal,
\r
1111 // - the type of an extended (by doubling element size) source is legal, and
\r
1112 // - the type of that extended source when split is legal.
\r
1114 // This won't necessarily completely legalize the operation, but it will
\r
1115 // more effectively move in the right direction and prevent falling down
\r
1116 // to scalarization in many cases due to the input vector being split too
\r
1118 unsigned NumElements = SrcVT.getVectorNumElements();
\r
1119 if ((NumElements & 1) == 0 &&
\r
1120 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
\r
1121 LLVMContext &Ctx = *DAG.getContext();
\r
1122 EVT NewSrcVT = EVT::getVectorVT(
\r
1123 Ctx, EVT::getIntegerVT(
\r
1124 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
\r
1127 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
\r
1128 EVT SplitLoVT, SplitHiVT;
\r
1129 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
\r
1130 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
\r
1131 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
\r
1132 DEBUG(dbgs() << "Split vector extend via incremental extend:";
\r
1133 N->dump(&DAG); dbgs() << "\n");
\r
1134 // Extend the source vector by one step.
\r
1136 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
\r
1137 // Get the low and high halves of the new, extended one step, vector.
\r
1138 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
\r
1139 // Extend those vector halves the rest of the way.
\r
1140 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
\r
1141 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
\r
1145 // Fall back to the generic unary operator splitting otherwise.
\r
1146 SplitVecRes_UnaryOp(N, Lo, Hi);
\r
1149 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
\r
1150 SDValue &Lo, SDValue &Hi) {
\r
1151 // The low and high parts of the original input give four input vectors.
\r
1152 SDValue Inputs[4];
\r
1154 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
\r
1155 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
\r
1156 EVT NewVT = Inputs[0].getValueType();
\r
1157 unsigned NewElts = NewVT.getVectorNumElements();
\r
1159 // If Lo or Hi uses elements from at most two of the four input vectors, then
\r
1160 // express it as a vector shuffle of those two inputs. Otherwise extract the
\r
1161 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
\r
1162 SmallVector<int, 16> Ops;
\r
1163 for (unsigned High = 0; High < 2; ++High) {
\r
1164 SDValue &Output = High ? Hi : Lo;
\r
1166 // Build a shuffle mask for the output, discovering on the fly which
\r
1167 // input vectors to use as shuffle operands (recorded in InputUsed).
\r
1168 // If building a suitable shuffle vector proves too hard, then bail
\r
1169 // out with useBuildVector set.
\r
1170 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
\r
1171 unsigned FirstMaskIdx = High * NewElts;
\r
1172 bool useBuildVector = false;
\r
1173 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
\r
1174 // The mask element. This indexes into the input.
\r
1175 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
\r
1177 // The input vector this mask element indexes into.
\r
1178 unsigned Input = (unsigned)Idx / NewElts;
\r
1180 if (Input >= array_lengthof(Inputs)) {
\r
1181 // The mask element does not index into any input vector.
\r
1182 Ops.push_back(-1);
\r
1186 // Turn the index into an offset from the start of the input vector.
\r
1187 Idx -= Input * NewElts;
\r
1189 // Find or create a shuffle vector operand to hold this input.
\r
1191 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
\r
1192 if (InputUsed[OpNo] == Input) {
\r
1193 // This input vector is already an operand.
\r
1195 } else if (InputUsed[OpNo] == -1U) {
\r
1196 // Create a new operand for this input vector.
\r
1197 InputUsed[OpNo] = Input;
\r
1202 if (OpNo >= array_lengthof(InputUsed)) {
\r
1203 // More than two input vectors used! Give up on trying to create a
\r
1204 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
\r
1205 useBuildVector = true;
\r
1209 // Add the mask index for the new shuffle vector.
\r
1210 Ops.push_back(Idx + OpNo * NewElts);
\r
1213 if (useBuildVector) {
\r
1214 EVT EltVT = NewVT.getVectorElementType();
\r
1215 SmallVector<SDValue, 16> SVOps;
\r
1217 // Extract the input elements by hand.
\r
1218 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
\r
1219 // The mask element. This indexes into the input.
\r
1220 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
\r
1222 // The input vector this mask element indexes into.
\r
1223 unsigned Input = (unsigned)Idx / NewElts;
\r
1225 if (Input >= array_lengthof(Inputs)) {
\r
1226 // The mask element is "undef" or indexes off the end of the input.
\r
1227 SVOps.push_back(DAG.getUNDEF(EltVT));
\r
1231 // Turn the index into an offset from the start of the input vector.
\r
1232 Idx -= Input * NewElts;
\r
1234 // Extract the vector element by hand.
\r
1235 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
\r
1236 Inputs[Input], DAG.getConstant(Idx,
\r
1237 TLI.getVectorIdxTy())));
\r
1240 // Construct the Lo/Hi output using a BUILD_VECTOR.
\r
1241 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
\r
1242 } else if (InputUsed[0] == -1U) {
\r
1243 // No input vectors were used! The result is undefined.
\r
1244 Output = DAG.getUNDEF(NewVT);
\r
1246 SDValue Op0 = Inputs[InputUsed[0]];
\r
1247 // If only one input was used, use an undefined vector for the other.
\r
1248 SDValue Op1 = InputUsed[1] == -1U ?
\r
1249 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
\r
1250 // At least one input vector was used. Create a new shuffle vector.
\r
1251 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
\r
1259 //===----------------------------------------------------------------------===//
\r
1260 // Operand Vector Splitting
\r
1261 //===----------------------------------------------------------------------===//
\r
1263 /// SplitVectorOperand - This method is called when the specified operand of the
\r
1264 /// specified node is found to need vector splitting. At this point, all of the
\r
1265 /// result types of the node are known to be legal, but other operands of the
\r
1266 /// node may need legalization as well as the specified one.
\r
1267 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
\r
1268 DEBUG(dbgs() << "Split node operand: ";
\r
1271 SDValue Res = SDValue();
\r
1273 // See if the target wants to custom split this node.
\r
1274 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
\r
1277 if (!Res.getNode()) {
\r
1278 switch (N->getOpcode()) {
\r
1281 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
\r
1285 report_fatal_error("Do not know how to split this operator's "
\r
1288 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
\r
1289 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
\r
1290 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
\r
1291 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
\r
1292 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
\r
1293 case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break;
\r
1294 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
\r
1296 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
\r
1299 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
\r
1301 case ISD::VSELECT:
\r
1302 Res = SplitVecOp_VSELECT(N, OpNo);
\r
1307 case ISD::FP_EXTEND:
\r
1308 case ISD::FP_TO_SINT:
\r
1309 case ISD::FP_TO_UINT:
\r
1310 case ISD::SINT_TO_FP:
\r
1311 case ISD::UINT_TO_FP:
\r
1313 case ISD::SIGN_EXTEND:
\r
1314 case ISD::ZERO_EXTEND:
\r
1315 case ISD::ANY_EXTEND:
\r
1316 Res = SplitVecOp_UnaryOp(N);
\r
1321 // If the result is null, the sub-method took care of registering results etc.
\r
1322 if (!Res.getNode()) return false;
\r
1324 // If the result is N, the sub-method updated N in place. Tell the legalizer
\r
1325 // core about this.
\r
1326 if (Res.getNode() == N)
\r
1329 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
\r
1330 "Invalid operand expansion");
\r
1332 ReplaceValueWith(SDValue(N, 0), Res);
\r
1336 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
\r
1337 // The only possibility for an illegal operand is the mask, since result type
\r
1338 // legalization would have handled this node already otherwise.
\r
1339 assert(OpNo == 0 && "Illegal operand must be mask");
\r
1341 SDValue Mask = N->getOperand(0);
\r
1342 SDValue Src0 = N->getOperand(1);
\r
1343 SDValue Src1 = N->getOperand(2);
\r
1344 EVT Src0VT = Src0.getValueType();
\r
1346 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
\r
1349 GetSplitVector(N->getOperand(0), Lo, Hi);
\r
1350 assert(Lo.getValueType() == Hi.getValueType() &&
\r
1351 "Lo and Hi have differing types");
\r
1353 EVT LoOpVT, HiOpVT;
\r
1354 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
\r
1355 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
\r
1357 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
\r
1358 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
\r
1359 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
\r
1360 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
\r
1362 SDValue LoSelect =
\r
1363 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
\r
1364 SDValue HiSelect =
\r
1365 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
\r
1367 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
\r
1370 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
\r
1371 // The result has a legal vector type, but the input needs splitting.
\r
1372 EVT ResVT = N->getValueType(0);
\r
1375 GetSplitVector(N->getOperand(0), Lo, Hi);
\r
1376 EVT InVT = Lo.getValueType();
\r
1378 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
\r
1379 InVT.getVectorNumElements());
\r
1381 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
\r
1382 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
\r
1384 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
\r
1387 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
\r
1388 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
\r
1389 // end up being split all the way down to individual components. Convert the
\r
1390 // split pieces into integers and reassemble.
\r
1392 GetSplitVector(N->getOperand(0), Lo, Hi);
\r
1393 Lo = BitConvertToInteger(Lo);
\r
1394 Hi = BitConvertToInteger(Hi);
\r
1396 if (TLI.isBigEndian())
\r
1397 std::swap(Lo, Hi);
\r
1399 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
\r
1400 JoinIntegers(Lo, Hi));
\r
1403 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
\r
1404 // We know that the extracted result type is legal.
\r
1405 EVT SubVT = N->getValueType(0);
\r
1406 SDValue Idx = N->getOperand(1);
\r
1409 GetSplitVector(N->getOperand(0), Lo, Hi);
\r
1411 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
\r
1412 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
\r
1414 if (IdxVal < LoElts) {
\r
1415 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
\r
1416 "Extracted subvector crosses vector split!");
\r
1417 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
\r
1419 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
\r
1420 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
\r
1424 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
\r
1425 SDValue Vec = N->getOperand(0);
\r
1426 SDValue Idx = N->getOperand(1);
\r
1427 EVT VecVT = Vec.getValueType();
\r
1429 if (isa<ConstantSDNode>(Idx)) {
\r
1430 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
\r
1431 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
\r
1434 GetSplitVector(Vec, Lo, Hi);
\r
1436 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
\r
1438 if (IdxVal < LoElts)
\r
1439 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
\r
1440 return SDValue(DAG.UpdateNodeOperands(N, Hi,
\r
1441 DAG.getConstant(IdxVal - LoElts,
\r
1442 Idx.getValueType())), 0);
\r
1445 // See if the target wants to custom expand this node.
\r
1446 if (CustomLowerNode(N, N->getValueType(0), true))
\r
1449 // Store the vector to the stack.
\r
1450 EVT EltVT = VecVT.getVectorElementType();
\r
1452 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
\r
1453 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
\r
1454 MachinePointerInfo(), false, false, 0);
\r
1456 // Load back the required element.
\r
1457 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
\r
1458 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
\r
1459 MachinePointerInfo(), EltVT, false, false, false, 0);
\r
1462 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
\r
1464 SDValue Ch = N->getChain();
\r
1465 SDValue Ptr = N->getBasePtr();
\r
1466 SDValue Mask = N->getMask();
\r
1467 SDValue Data = N->getData();
\r
1468 EVT MemoryVT = N->getMemoryVT();
\r
1469 unsigned Alignment = N->getOriginalAlignment();
\r
1472 EVT LoMemVT, HiMemVT;
\r
1473 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
\r
1475 SDValue DataLo, DataHi;
\r
1476 GetSplitVector(Data, DataLo, DataHi);
\r
1477 SDValue MaskLo, MaskHi;
\r
1478 GetSplitVector(Mask, MaskLo, MaskHi);
\r
1480 // if Alignment is equal to the vector size,
\r
1481 // take the half of it for the second part
\r
1482 unsigned SecondHalfAlignment =
\r
1483 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
\r
1484 Alignment/2 : Alignment;
\r
1487 MachineMemOperand *MMO = DAG.getMachineFunction().
\r
1488 getMachineMemOperand(N->getPointerInfo(),
\r
1489 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
\r
1490 Alignment, N->getAAInfo(), N->getRanges());
\r
1492 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, MMO);
\r
1494 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
\r
1495 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
\r
1496 DAG.getConstant(IncrementSize, Ptr.getValueType()));
\r
1498 MMO = DAG.getMachineFunction().
\r
1499 getMachineMemOperand(N->getPointerInfo(),
\r
1500 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
\r
1501 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
\r
1503 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, MMO);
\r
1506 // Build a factor node to remember that this store is independent of the
\r
1508 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
\r
1512 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
\r
1513 assert(N->isUnindexed() && "Indexed store of vector?");
\r
1514 assert(OpNo == 1 && "Can only split the stored value");
\r
1517 bool isTruncating = N->isTruncatingStore();
\r
1518 SDValue Ch = N->getChain();
\r
1519 SDValue Ptr = N->getBasePtr();
\r
1520 EVT MemoryVT = N->getMemoryVT();
\r
1521 unsigned Alignment = N->getOriginalAlignment();
\r
1522 bool isVol = N->isVolatile();
\r
1523 bool isNT = N->isNonTemporal();
\r
1524 AAMDNodes AAInfo = N->getAAInfo();
\r
1526 GetSplitVector(N->getOperand(1), Lo, Hi);
\r
1528 EVT LoMemVT, HiMemVT;
\r
1529 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
\r
1531 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
\r
1534 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
\r
1535 LoMemVT, isVol, isNT, Alignment, AAInfo);
\r
1537 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
\r
1538 isVol, isNT, Alignment, AAInfo);
\r
1540 // Increment the pointer to the other half.
\r
1541 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
\r
1542 DAG.getConstant(IncrementSize, Ptr.getValueType()));
\r
1545 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
\r
1546 N->getPointerInfo().getWithOffset(IncrementSize),
\r
1547 HiMemVT, isVol, isNT, Alignment, AAInfo);
\r
1549 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
\r
1550 N->getPointerInfo().getWithOffset(IncrementSize),
\r
1551 isVol, isNT, Alignment, AAInfo);
\r
1553 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
\r
1556 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
\r
1559 // The input operands all must have the same type, and we know the result
\r
1560 // type is valid. Convert this to a buildvector which extracts all the
\r
1561 // input elements.
\r
1562 // TODO: If the input elements are power-two vectors, we could convert this to
\r
1563 // a new CONCAT_VECTORS node with elements that are half-wide.
\r
1564 SmallVector<SDValue, 32> Elts;
\r
1565 EVT EltVT = N->getValueType(0).getVectorElementType();
\r
1566 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
\r
1567 SDValue Op = N->getOperand(op);
\r
1568 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
\r
1570 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
\r
1571 Op, DAG.getConstant(i, TLI.getVectorIdxTy())));
\r
1576 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
\r
1579 SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) {
\r
1580 // The result type is legal, but the input type is illegal. If splitting
\r
1581 // ends up with the result type of each half still being legal, just
\r
1582 // do that. If, however, that would result in an illegal result type,
\r
1583 // we can try to get more clever with power-two vectors. Specifically,
\r
1584 // split the input type, but also widen the result element size, then
\r
1585 // concatenate the halves and truncate again. For example, consider a target
\r
1586 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
\r
1587 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
\r
1588 // %inlo = v4i32 extract_subvector %in, 0
\r
1589 // %inhi = v4i32 extract_subvector %in, 4
\r
1590 // %lo16 = v4i16 trunc v4i32 %inlo
\r
1591 // %hi16 = v4i16 trunc v4i32 %inhi
\r
1592 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
\r
1593 // %res = v8i8 trunc v8i16 %in16
\r
1595 // Without this transform, the original truncate would end up being
\r
1596 // scalarized, which is pretty much always a last resort.
\r
1597 SDValue InVec = N->getOperand(0);
\r
1598 EVT InVT = InVec->getValueType(0);
\r
1599 EVT OutVT = N->getValueType(0);
\r
1600 unsigned NumElements = OutVT.getVectorNumElements();
\r
1601 // Widening should have already made sure this is a power-two vector
\r
1602 // if we're trying to split it at all. assert() that's true, just in case.
\r
1603 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
\r
1605 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
\r
1606 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
\r
1608 // If the input elements are only 1/2 the width of the result elements,
\r
1609 // just use the normal splitting. Our trick only work if there's room
\r
1610 // to split more than once.
\r
1611 if (InElementSize <= OutElementSize * 2)
\r
1612 return SplitVecOp_UnaryOp(N);
\r
1615 // Extract the halves of the input via extract_subvector.
\r
1616 SDValue InLoVec, InHiVec;
\r
1617 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
\r
1618 // Truncate them to 1/2 the element size.
\r
1619 EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
\r
1620 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
\r
1622 SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec);
\r
1623 SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec);
\r
1624 // Concatenate them to get the full intermediate truncation result.
\r
1625 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
\r
1626 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
\r
1628 // Now finish up by truncating all the way down to the original result
\r
1629 // type. This should normally be something that ends up being legal directly,
\r
1630 // but in theory if a target has very wide vectors and an annoyingly
\r
1631 // restricted set of legal types, this split can chain to build things up.
\r
1632 return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
\r
1635 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
\r
1636 assert(N->getValueType(0).isVector() &&
\r
1637 N->getOperand(0).getValueType().isVector() &&
\r
1638 "Operand types must be vectors");
\r
1639 // The result has a legal vector type, but the input needs splitting.
\r
1640 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
\r
1642 GetSplitVector(N->getOperand(0), Lo0, Hi0);
\r
1643 GetSplitVector(N->getOperand(1), Lo1, Hi1);
\r
1644 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
\r
1645 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
\r
1646 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
\r
1648 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
\r
1649 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
\r
1650 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
\r
1651 return PromoteTargetBoolean(Con, N->getValueType(0));
\r
1655 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
\r
1656 // The result has a legal vector type, but the input needs splitting.
\r
1657 EVT ResVT = N->getValueType(0);
\r
1660 GetSplitVector(N->getOperand(0), Lo, Hi);
\r
1661 EVT InVT = Lo.getValueType();
\r
1663 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
\r
1664 InVT.getVectorNumElements());
\r
1666 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
\r
1667 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
\r
1669 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
\r
1674 //===----------------------------------------------------------------------===//
\r
1675 // Result Vector Widening
\r
1676 //===----------------------------------------------------------------------===//
\r
1678 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
\r
1679 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
\r
1683 // See if the target wants to custom widen this node.
\r
1684 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
\r
1687 SDValue Res = SDValue();
\r
1688 switch (N->getOpcode()) {
\r
1691 dbgs() << "WidenVectorResult #" << ResNo << ": ";
\r
1695 llvm_unreachable("Do not know how to widen the result of this operator!");
\r
1697 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
\r
1698 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
\r
1699 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
\r
1700 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
\r
1701 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
\r
1702 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
\r
1703 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
\r
1704 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
\r
1705 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
\r
1706 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
\r
1707 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
\r
1708 case ISD::VSELECT:
\r
1709 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
\r
1710 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
\r
1711 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
\r
1712 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
\r
1713 case ISD::VECTOR_SHUFFLE:
\r
1714 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
\r
1725 case ISD::FMINNUM:
\r
1726 case ISD::FMAXNUM:
\r
1727 Res = WidenVecRes_Binary(N);
\r
1731 case ISD::FCOPYSIGN:
\r
1741 Res = WidenVecRes_BinaryCanTrap(N);
\r
1745 Res = WidenVecRes_POWI(N);
\r
1751 Res = WidenVecRes_Shift(N);
\r
1754 case ISD::ANY_EXTEND:
\r
1755 case ISD::FP_EXTEND:
\r
1756 case ISD::FP_ROUND:
\r
1757 case ISD::FP_TO_SINT:
\r
1758 case ISD::FP_TO_UINT:
\r
1759 case ISD::SIGN_EXTEND:
\r
1760 case ISD::SINT_TO_FP:
\r
1761 case ISD::TRUNCATE:
\r
1762 case ISD::UINT_TO_FP:
\r
1763 case ISD::ZERO_EXTEND:
\r
1764 Res = WidenVecRes_Convert(N);
\r
1780 case ISD::FNEARBYINT:
\r
1787 Res = WidenVecRes_Unary(N);
\r
1790 Res = WidenVecRes_Ternary(N);
\r
1794 // If Res is null, the sub-method took care of registering the result.
\r
1795 if (Res.getNode())
\r
1796 SetWidenedVector(SDValue(N, ResNo), Res);
\r
1799 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
\r
1800 // Ternary op widening.
\r
1802 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
1803 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
\r
1804 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
\r
1805 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
\r
1806 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
\r
1809 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
\r
1810 // Binary op widening.
\r
1812 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
1813 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
\r
1814 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
\r
1815 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
\r
1818 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
\r
1819 // Binary op widening for operations that can trap.
\r
1820 unsigned Opcode = N->getOpcode();
\r
1822 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
1823 EVT WidenEltVT = WidenVT.getVectorElementType();
\r
1825 unsigned NumElts = VT.getVectorNumElements();
\r
1826 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
\r
1827 NumElts = NumElts / 2;
\r
1828 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
\r
1831 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
\r
1832 // Operation doesn't trap so just widen as normal.
\r
1833 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
\r
1834 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
\r
1835 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
\r
1838 // No legal vector version so unroll the vector operation and then widen.
\r
1840 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
\r
1842 // Since the operation can trap, apply operation on the original vector.
\r
1844 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
\r
1845 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
\r
1846 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
\r
1848 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
\r
1849 unsigned ConcatEnd = 0; // Current ConcatOps index.
\r
1850 int Idx = 0; // Current Idx into input vectors.
\r
1852 // NumElts := greatest legal vector size (at most WidenVT)
\r
1853 // while (orig. vector has unhandled elements) {
\r
1854 // take munches of size NumElts from the beginning and add to ConcatOps
\r
1855 // NumElts := next smaller supported vector size or 1
\r
1857 while (CurNumElts != 0) {
\r
1858 while (CurNumElts >= NumElts) {
\r
1859 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
\r
1860 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
\r
1861 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
\r
1862 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
\r
1863 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
\r
1865 CurNumElts -= NumElts;
\r
1868 NumElts = NumElts / 2;
\r
1869 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
\r
1870 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
\r
1872 if (NumElts == 1) {
\r
1873 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
\r
1874 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
\r
1875 InOp1, DAG.getConstant(Idx,
\r
1876 TLI.getVectorIdxTy()));
\r
1877 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
\r
1878 InOp2, DAG.getConstant(Idx,
\r
1879 TLI.getVectorIdxTy()));
\r
1880 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
\r
1887 // Check to see if we have a single operation with the widen type.
\r
1888 if (ConcatEnd == 1) {
\r
1889 VT = ConcatOps[0].getValueType();
\r
1890 if (VT == WidenVT)
\r
1891 return ConcatOps[0];
\r
1894 // while (Some element of ConcatOps is not of type MaxVT) {
\r
1895 // From the end of ConcatOps, collect elements of the same type and put
\r
1896 // them into an op of the next larger supported type
\r
1898 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
\r
1899 Idx = ConcatEnd - 1;
\r
1900 VT = ConcatOps[Idx--].getValueType();
\r
1901 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
\r
1904 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
\r
1908 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
\r
1909 } while (!TLI.isTypeLegal(NextVT));
\r
1911 if (!VT.isVector()) {
\r
1912 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
\r
1913 SDValue VecOp = DAG.getUNDEF(NextVT);
\r
1914 unsigned NumToInsert = ConcatEnd - Idx - 1;
\r
1915 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
\r
1916 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
\r
1917 ConcatOps[OpIdx], DAG.getConstant(i,
\r
1918 TLI.getVectorIdxTy()));
\r
1920 ConcatOps[Idx+1] = VecOp;
\r
1921 ConcatEnd = Idx + 2;
\r
1923 // Vector type, create a CONCAT_VECTORS of type NextVT
\r
1924 SDValue undefVec = DAG.getUNDEF(VT);
\r
1925 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
\r
1926 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
\r
1927 unsigned RealVals = ConcatEnd - Idx - 1;
\r
1928 unsigned SubConcatEnd = 0;
\r
1929 unsigned SubConcatIdx = Idx + 1;
\r
1930 while (SubConcatEnd < RealVals)
\r
1931 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
\r
1932 while (SubConcatEnd < OpsToConcat)
\r
1933 SubConcatOps[SubConcatEnd++] = undefVec;
\r
1934 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
\r
1935 NextVT, SubConcatOps);
\r
1936 ConcatEnd = SubConcatIdx + 1;
\r
1940 // Check to see if we have a single operation with the widen type.
\r
1941 if (ConcatEnd == 1) {
\r
1942 VT = ConcatOps[0].getValueType();
\r
1943 if (VT == WidenVT)
\r
1944 return ConcatOps[0];
\r
1947 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
\r
1948 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
\r
1949 if (NumOps != ConcatEnd ) {
\r
1950 SDValue UndefVal = DAG.getUNDEF(MaxVT);
\r
1951 for (unsigned j = ConcatEnd; j < NumOps; ++j)
\r
1952 ConcatOps[j] = UndefVal;
\r
1954 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
\r
1955 makeArrayRef(ConcatOps.data(), NumOps));
\r
1958 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
\r
1959 SDValue InOp = N->getOperand(0);
\r
1962 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
1963 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
1965 EVT InVT = InOp.getValueType();
\r
1966 EVT InEltVT = InVT.getVectorElementType();
\r
1967 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
\r
1969 unsigned Opcode = N->getOpcode();
\r
1970 unsigned InVTNumElts = InVT.getVectorNumElements();
\r
1972 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
\r
1973 InOp = GetWidenedVector(N->getOperand(0));
\r
1974 InVT = InOp.getValueType();
\r
1975 InVTNumElts = InVT.getVectorNumElements();
\r
1976 if (InVTNumElts == WidenNumElts) {
\r
1977 if (N->getNumOperands() == 1)
\r
1978 return DAG.getNode(Opcode, DL, WidenVT, InOp);
\r
1979 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
\r
1983 if (TLI.isTypeLegal(InWidenVT)) {
\r
1984 // Because the result and the input are different vector types, widening
\r
1985 // the result could create a legal type but widening the input might make
\r
1986 // it an illegal type that might lead to repeatedly splitting the input
\r
1987 // and then widening it. To avoid this, we widen the input only if
\r
1988 // it results in a legal type.
\r
1989 if (WidenNumElts % InVTNumElts == 0) {
\r
1990 // Widen the input and call convert on the widened input vector.
\r
1991 unsigned NumConcat = WidenNumElts/InVTNumElts;
\r
1992 SmallVector<SDValue, 16> Ops(NumConcat);
\r
1994 SDValue UndefVal = DAG.getUNDEF(InVT);
\r
1995 for (unsigned i = 1; i != NumConcat; ++i)
\r
1996 Ops[i] = UndefVal;
\r
1997 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
\r
1998 if (N->getNumOperands() == 1)
\r
1999 return DAG.getNode(Opcode, DL, WidenVT, InVec);
\r
2000 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
\r
2003 if (InVTNumElts % WidenNumElts == 0) {
\r
2004 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
\r
2005 InOp, DAG.getConstant(0,
\r
2006 TLI.getVectorIdxTy()));
\r
2007 // Extract the input and convert the shorten input vector.
\r
2008 if (N->getNumOperands() == 1)
\r
2009 return DAG.getNode(Opcode, DL, WidenVT, InVal);
\r
2010 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
\r
2014 // Otherwise unroll into some nasty scalar code and rebuild the vector.
\r
2015 SmallVector<SDValue, 16> Ops(WidenNumElts);
\r
2016 EVT EltVT = WidenVT.getVectorElementType();
\r
2017 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
\r
2019 for (i=0; i < MinElts; ++i) {
\r
2020 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
\r
2021 DAG.getConstant(i, TLI.getVectorIdxTy()));
\r
2022 if (N->getNumOperands() == 1)
\r
2023 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
\r
2025 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
\r
2028 SDValue UndefVal = DAG.getUNDEF(EltVT);
\r
2029 for (; i < WidenNumElts; ++i)
\r
2030 Ops[i] = UndefVal;
\r
2032 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
\r
2035 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
\r
2036 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2037 SDValue InOp = GetWidenedVector(N->getOperand(0));
\r
2038 SDValue ShOp = N->getOperand(1);
\r
2039 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
\r
2042 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
\r
2043 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2044 SDValue InOp = GetWidenedVector(N->getOperand(0));
\r
2045 SDValue ShOp = N->getOperand(1);
\r
2047 EVT ShVT = ShOp.getValueType();
\r
2048 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
\r
2049 ShOp = GetWidenedVector(ShOp);
\r
2050 ShVT = ShOp.getValueType();
\r
2052 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
\r
2053 ShVT.getVectorElementType(),
\r
2054 WidenVT.getVectorNumElements());
\r
2055 if (ShVT != ShWidenVT)
\r
2056 ShOp = ModifyToType(ShOp, ShWidenVT);
\r
2058 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
\r
2061 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
\r
2062 // Unary op widening.
\r
2063 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2064 SDValue InOp = GetWidenedVector(N->getOperand(0));
\r
2065 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
\r
2068 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
\r
2069 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2070 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
\r
2071 cast<VTSDNode>(N->getOperand(1))->getVT()
\r
2072 .getVectorElementType(),
\r
2073 WidenVT.getVectorNumElements());
\r
2074 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
\r
2075 return DAG.getNode(N->getOpcode(), SDLoc(N),
\r
2076 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
\r
2079 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
\r
2080 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
\r
2081 return GetWidenedVector(WidenVec);
\r
2084 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
\r
2085 SDValue InOp = N->getOperand(0);
\r
2086 EVT InVT = InOp.getValueType();
\r
2087 EVT VT = N->getValueType(0);
\r
2088 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
\r
2091 switch (getTypeAction(InVT)) {
\r
2092 case TargetLowering::TypeLegal:
\r
2094 case TargetLowering::TypePromoteInteger:
\r
2095 // If the incoming type is a vector that is being promoted, then
\r
2096 // we know that the elements are arranged differently and that we
\r
2097 // must perform the conversion using a stack slot.
\r
2098 if (InVT.isVector())
\r
2101 // If the InOp is promoted to the same size, convert it. Otherwise,
\r
2102 // fall out of the switch and widen the promoted input.
\r
2103 InOp = GetPromotedInteger(InOp);
\r
2104 InVT = InOp.getValueType();
\r
2105 if (WidenVT.bitsEq(InVT))
\r
2106 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
\r
2108 case TargetLowering::TypeSoftenFloat:
\r
2109 case TargetLowering::TypeExpandInteger:
\r
2110 case TargetLowering::TypeExpandFloat:
\r
2111 case TargetLowering::TypeScalarizeVector:
\r
2112 case TargetLowering::TypeSplitVector:
\r
2114 case TargetLowering::TypeWidenVector:
\r
2115 // If the InOp is widened to the same size, convert it. Otherwise, fall
\r
2116 // out of the switch and widen the widened input.
\r
2117 InOp = GetWidenedVector(InOp);
\r
2118 InVT = InOp.getValueType();
\r
2119 if (WidenVT.bitsEq(InVT))
\r
2120 // The input widens to the same size. Convert to the widen value.
\r
2121 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
\r
2125 unsigned WidenSize = WidenVT.getSizeInBits();
\r
2126 unsigned InSize = InVT.getSizeInBits();
\r
2127 // x86mmx is not an acceptable vector element type, so don't try.
\r
2128 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
\r
2129 // Determine new input vector type. The new input vector type will use
\r
2130 // the same element type (if its a vector) or use the input type as a
\r
2131 // vector. It is the same size as the type to widen to.
\r
2133 unsigned NewNumElts = WidenSize / InSize;
\r
2134 if (InVT.isVector()) {
\r
2135 EVT InEltVT = InVT.getVectorElementType();
\r
2136 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
\r
2137 WidenSize / InEltVT.getSizeInBits());
\r
2139 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
\r
2142 if (TLI.isTypeLegal(NewInVT)) {
\r
2143 // Because the result and the input are different vector types, widening
\r
2144 // the result could create a legal type but widening the input might make
\r
2145 // it an illegal type that might lead to repeatedly splitting the input
\r
2146 // and then widening it. To avoid this, we widen the input only if
\r
2147 // it results in a legal type.
\r
2148 SmallVector<SDValue, 16> Ops(NewNumElts);
\r
2149 SDValue UndefVal = DAG.getUNDEF(InVT);
\r
2151 for (unsigned i = 1; i < NewNumElts; ++i)
\r
2152 Ops[i] = UndefVal;
\r
2155 if (InVT.isVector())
\r
2156 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
\r
2158 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
\r
2159 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
\r
2163 return CreateStackStoreLoad(InOp, WidenVT);
\r
2166 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
\r
2168 // Build a vector with undefined for the new nodes.
\r
2169 EVT VT = N->getValueType(0);
\r
2171 // Integer BUILD_VECTOR operands may be larger than the node's vector element
\r
2172 // type. The UNDEFs need to have the same type as the existing operands.
\r
2173 EVT EltVT = N->getOperand(0).getValueType();
\r
2174 unsigned NumElts = VT.getVectorNumElements();
\r
2176 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
\r
2177 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
2179 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
\r
2180 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
\r
2181 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
\r
2183 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
\r
2186 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
\r
2187 EVT InVT = N->getOperand(0).getValueType();
\r
2188 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2190 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
2191 unsigned NumInElts = InVT.getVectorNumElements();
\r
2192 unsigned NumOperands = N->getNumOperands();
\r
2194 bool InputWidened = false; // Indicates we need to widen the input.
\r
2195 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
\r
2196 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
\r
2197 // Add undef vectors to widen to correct length.
\r
2198 unsigned NumConcat = WidenVT.getVectorNumElements() /
\r
2199 InVT.getVectorNumElements();
\r
2200 SDValue UndefVal = DAG.getUNDEF(InVT);
\r
2201 SmallVector<SDValue, 16> Ops(NumConcat);
\r
2202 for (unsigned i=0; i < NumOperands; ++i)
\r
2203 Ops[i] = N->getOperand(i);
\r
2204 for (unsigned i = NumOperands; i != NumConcat; ++i)
\r
2205 Ops[i] = UndefVal;
\r
2206 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
\r
2209 InputWidened = true;
\r
2210 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
\r
2211 // The inputs and the result are widen to the same value.
\r
2213 for (i=1; i < NumOperands; ++i)
\r
2214 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
\r
2217 if (i == NumOperands)
\r
2218 // Everything but the first operand is an UNDEF so just return the
\r
2219 // widened first operand.
\r
2220 return GetWidenedVector(N->getOperand(0));
\r
2222 if (NumOperands == 2) {
\r
2223 // Replace concat of two operands with a shuffle.
\r
2224 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
\r
2225 for (unsigned i = 0; i < NumInElts; ++i) {
\r
2227 MaskOps[i + NumInElts] = i + WidenNumElts;
\r
2229 return DAG.getVectorShuffle(WidenVT, dl,
\r
2230 GetWidenedVector(N->getOperand(0)),
\r
2231 GetWidenedVector(N->getOperand(1)),
\r
2237 // Fall back to use extracts and build vector.
\r
2238 EVT EltVT = WidenVT.getVectorElementType();
\r
2239 SmallVector<SDValue, 16> Ops(WidenNumElts);
\r
2241 for (unsigned i=0; i < NumOperands; ++i) {
\r
2242 SDValue InOp = N->getOperand(i);
\r
2244 InOp = GetWidenedVector(InOp);
\r
2245 for (unsigned j=0; j < NumInElts; ++j)
\r
2246 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
\r
2247 DAG.getConstant(j, TLI.getVectorIdxTy()));
\r
2249 SDValue UndefVal = DAG.getUNDEF(EltVT);
\r
2250 for (; Idx < WidenNumElts; ++Idx)
\r
2251 Ops[Idx] = UndefVal;
\r
2252 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
\r
2255 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
\r
2257 SDValue InOp = N->getOperand(0);
\r
2258 SDValue RndOp = N->getOperand(3);
\r
2259 SDValue SatOp = N->getOperand(4);
\r
2261 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2262 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
2264 EVT InVT = InOp.getValueType();
\r
2265 EVT InEltVT = InVT.getVectorElementType();
\r
2266 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
\r
2268 SDValue DTyOp = DAG.getValueType(WidenVT);
\r
2269 SDValue STyOp = DAG.getValueType(InWidenVT);
\r
2270 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
\r
2272 unsigned InVTNumElts = InVT.getVectorNumElements();
\r
2273 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
\r
2274 InOp = GetWidenedVector(InOp);
\r
2275 InVT = InOp.getValueType();
\r
2276 InVTNumElts = InVT.getVectorNumElements();
\r
2277 if (InVTNumElts == WidenNumElts)
\r
2278 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
\r
2282 if (TLI.isTypeLegal(InWidenVT)) {
\r
2283 // Because the result and the input are different vector types, widening
\r
2284 // the result could create a legal type but widening the input might make
\r
2285 // it an illegal type that might lead to repeatedly splitting the input
\r
2286 // and then widening it. To avoid this, we widen the input only if
\r
2287 // it results in a legal type.
\r
2288 if (WidenNumElts % InVTNumElts == 0) {
\r
2289 // Widen the input and call convert on the widened input vector.
\r
2290 unsigned NumConcat = WidenNumElts/InVTNumElts;
\r
2291 SmallVector<SDValue, 16> Ops(NumConcat);
\r
2293 SDValue UndefVal = DAG.getUNDEF(InVT);
\r
2294 for (unsigned i = 1; i != NumConcat; ++i)
\r
2295 Ops[i] = UndefVal;
\r
2297 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
\r
2298 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
\r
2302 if (InVTNumElts % WidenNumElts == 0) {
\r
2303 // Extract the input and convert the shorten input vector.
\r
2304 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
\r
2305 DAG.getConstant(0, TLI.getVectorIdxTy()));
\r
2306 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
\r
2311 // Otherwise unroll into some nasty scalar code and rebuild the vector.
\r
2312 SmallVector<SDValue, 16> Ops(WidenNumElts);
\r
2313 EVT EltVT = WidenVT.getVectorElementType();
\r
2314 DTyOp = DAG.getValueType(EltVT);
\r
2315 STyOp = DAG.getValueType(InEltVT);
\r
2317 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
\r
2319 for (i=0; i < MinElts; ++i) {
\r
2320 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
\r
2321 DAG.getConstant(i, TLI.getVectorIdxTy()));
\r
2322 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
\r
2326 SDValue UndefVal = DAG.getUNDEF(EltVT);
\r
2327 for (; i < WidenNumElts; ++i)
\r
2328 Ops[i] = UndefVal;
\r
2330 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
\r
2333 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
\r
2334 EVT VT = N->getValueType(0);
\r
2335 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
\r
2336 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
2337 SDValue InOp = N->getOperand(0);
\r
2338 SDValue Idx = N->getOperand(1);
\r
2341 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
\r
2342 InOp = GetWidenedVector(InOp);
\r
2344 EVT InVT = InOp.getValueType();
\r
2346 // Check if we can just return the input vector after widening.
\r
2347 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
\r
2348 if (IdxVal == 0 && InVT == WidenVT)
\r
2351 // Check if we can extract from the vector.
\r
2352 unsigned InNumElts = InVT.getVectorNumElements();
\r
2353 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
\r
2354 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
\r
2356 // We could try widening the input to the right length but for now, extract
\r
2357 // the original elements, fill the rest with undefs and build a vector.
\r
2358 SmallVector<SDValue, 16> Ops(WidenNumElts);
\r
2359 EVT EltVT = VT.getVectorElementType();
\r
2360 unsigned NumElts = VT.getVectorNumElements();
\r
2362 for (i=0; i < NumElts; ++i)
\r
2363 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
\r
2364 DAG.getConstant(IdxVal+i, TLI.getVectorIdxTy()));
\r
2366 SDValue UndefVal = DAG.getUNDEF(EltVT);
\r
2367 for (; i < WidenNumElts; ++i)
\r
2368 Ops[i] = UndefVal;
\r
2369 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
\r
2372 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
\r
2373 SDValue InOp = GetWidenedVector(N->getOperand(0));
\r
2374 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
\r
2375 InOp.getValueType(), InOp,
\r
2376 N->getOperand(1), N->getOperand(2));
\r
2379 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
\r
2380 LoadSDNode *LD = cast<LoadSDNode>(N);
\r
2381 ISD::LoadExtType ExtType = LD->getExtensionType();
\r
2384 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
\r
2385 if (ExtType != ISD::NON_EXTLOAD)
\r
2386 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
\r
2388 Result = GenWidenVectorLoads(LdChain, LD);
\r
2390 // If we generate a single load, we can use that for the chain. Otherwise,
\r
2391 // build a factor node to remember the multiple loads are independent and
\r
2394 if (LdChain.size() == 1)
\r
2395 NewChain = LdChain[0];
\r
2397 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
\r
2399 // Modified the chain - switch anything that used the old chain to use
\r
2401 ReplaceValueWith(SDValue(N, 1), NewChain);
\r
2406 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
\r
2407 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2408 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
\r
2409 WidenVT, N->getOperand(0));
\r
2412 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
\r
2413 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2414 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
2416 SDValue Cond1 = N->getOperand(0);
\r
2417 EVT CondVT = Cond1.getValueType();
\r
2418 if (CondVT.isVector()) {
\r
2419 EVT CondEltVT = CondVT.getVectorElementType();
\r
2420 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
\r
2421 CondEltVT, WidenNumElts);
\r
2422 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
\r
2423 Cond1 = GetWidenedVector(Cond1);
\r
2425 // If we have to split the condition there is no point in widening the
\r
2426 // select. This would result in an cycle of widening the select ->
\r
2427 // widening the condition operand -> splitting the condition operand ->
\r
2428 // splitting the select -> widening the select. Instead split this select
\r
2429 // further and widen the resulting type.
\r
2430 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
\r
2431 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
\r
2432 SDValue Res = ModifyToType(SplitSelect, WidenVT);
\r
2436 if (Cond1.getValueType() != CondWidenVT)
\r
2437 Cond1 = ModifyToType(Cond1, CondWidenVT);
\r
2440 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
\r
2441 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
\r
2442 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
\r
2443 return DAG.getNode(N->getOpcode(), SDLoc(N),
\r
2444 WidenVT, Cond1, InOp1, InOp2);
\r
2447 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
\r
2448 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
\r
2449 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
\r
2450 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
\r
2451 InOp1.getValueType(), N->getOperand(0),
\r
2452 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
\r
2455 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
\r
2456 assert(N->getValueType(0).isVector() ==
\r
2457 N->getOperand(0).getValueType().isVector() &&
\r
2458 "Scalar/Vector type mismatch");
\r
2459 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
\r
2461 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2462 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
\r
2463 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
\r
2464 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
\r
2465 InOp1, InOp2, N->getOperand(2));
\r
2468 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
\r
2469 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2470 return DAG.getUNDEF(WidenVT);
\r
2473 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
\r
2474 EVT VT = N->getValueType(0);
\r
2477 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
\r
2478 unsigned NumElts = VT.getVectorNumElements();
\r
2479 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
2481 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
\r
2482 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
\r
2484 // Adjust mask based on new input vector length.
\r
2485 SmallVector<int, 16> NewMask;
\r
2486 for (unsigned i = 0; i != NumElts; ++i) {
\r
2487 int Idx = N->getMaskElt(i);
\r
2488 if (Idx < (int)NumElts)
\r
2489 NewMask.push_back(Idx);
\r
2491 NewMask.push_back(Idx - NumElts + WidenNumElts);
\r
2493 for (unsigned i = NumElts; i != WidenNumElts; ++i)
\r
2494 NewMask.push_back(-1);
\r
2495 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
\r
2498 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
\r
2499 assert(N->getValueType(0).isVector() &&
\r
2500 N->getOperand(0).getValueType().isVector() &&
\r
2501 "Operands must be vectors");
\r
2502 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
\r
2503 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
2505 SDValue InOp1 = N->getOperand(0);
\r
2506 EVT InVT = InOp1.getValueType();
\r
2507 assert(InVT.isVector() && "can not widen non-vector type");
\r
2508 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
\r
2509 InVT.getVectorElementType(), WidenNumElts);
\r
2510 InOp1 = GetWidenedVector(InOp1);
\r
2511 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
\r
2513 // Assume that the input and output will be widen appropriately. If not,
\r
2514 // we will have to unroll it at some point.
\r
2515 assert(InOp1.getValueType() == WidenInVT &&
\r
2516 InOp2.getValueType() == WidenInVT &&
\r
2517 "Input not widened to expected type!");
\r
2519 return DAG.getNode(ISD::SETCC, SDLoc(N),
\r
2520 WidenVT, InOp1, InOp2, N->getOperand(2));
\r
2524 //===----------------------------------------------------------------------===//
\r
2525 // Widen Vector Operand
\r
2526 //===----------------------------------------------------------------------===//
\r
2527 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
\r
2528 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
\r
2531 SDValue Res = SDValue();
\r
2533 // See if the target wants to custom widen this node.
\r
2534 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
\r
2537 switch (N->getOpcode()) {
\r
2540 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
\r
2544 llvm_unreachable("Do not know how to widen this operator's operand!");
\r
2546 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
\r
2547 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
\r
2548 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
\r
2549 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
\r
2550 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
\r
2551 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
\r
2553 case ISD::ANY_EXTEND:
\r
2554 case ISD::SIGN_EXTEND:
\r
2555 case ISD::ZERO_EXTEND:
\r
2556 Res = WidenVecOp_EXTEND(N);
\r
2559 case ISD::FP_EXTEND:
\r
2560 case ISD::FP_TO_SINT:
\r
2561 case ISD::FP_TO_UINT:
\r
2562 case ISD::SINT_TO_FP:
\r
2563 case ISD::UINT_TO_FP:
\r
2564 case ISD::TRUNCATE:
\r
2565 Res = WidenVecOp_Convert(N);
\r
2569 // If Res is null, the sub-method took care of registering the result.
\r
2570 if (!Res.getNode()) return false;
\r
2572 // If the result is N, the sub-method updated N in place. Tell the legalizer
\r
2573 // core about this.
\r
2574 if (Res.getNode() == N)
\r
2578 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
\r
2579 "Invalid operand expansion");
\r
2581 ReplaceValueWith(SDValue(N, 0), Res);
\r
2585 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
\r
2587 EVT VT = N->getValueType(0);
\r
2589 SDValue InOp = N->getOperand(0);
\r
2590 // If some legalization strategy other than widening is used on the operand,
\r
2591 // we can't safely assume that just extending the low lanes is the correct
\r
2592 // transformation.
\r
2593 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
\r
2594 return WidenVecOp_Convert(N);
\r
2595 InOp = GetWidenedVector(InOp);
\r
2596 assert(VT.getVectorNumElements() <
\r
2597 InOp.getValueType().getVectorNumElements() &&
\r
2598 "Input wasn't widened!");
\r
2600 // We may need to further widen the operand until it has the same total
\r
2601 // vector size as the result.
\r
2602 EVT InVT = InOp.getValueType();
\r
2603 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
\r
2604 EVT InEltVT = InVT.getVectorElementType();
\r
2605 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
\r
2606 EVT FixedVT = (MVT::SimpleValueType)i;
\r
2607 EVT FixedEltVT = FixedVT.getVectorElementType();
\r
2608 if (TLI.isTypeLegal(FixedVT) &&
\r
2609 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
\r
2610 FixedEltVT == InEltVT) {
\r
2611 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
\r
2612 "Not enough elements in the fixed type for the operand!");
\r
2613 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
\r
2614 "We can't have the same type as we started with!");
\r
2615 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
\r
2616 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
\r
2617 DAG.getUNDEF(FixedVT), InOp,
\r
2618 DAG.getConstant(0, TLI.getVectorIdxTy()));
\r
2620 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
\r
2621 DAG.getConstant(0, TLI.getVectorIdxTy()));
\r
2625 InVT = InOp.getValueType();
\r
2626 if (InVT.getSizeInBits() != VT.getSizeInBits())
\r
2627 // We couldn't find a legal vector type that was a widening of the input
\r
2628 // and could be extended in-register to the result type, so we have to
\r
2630 return WidenVecOp_Convert(N);
\r
2633 // Use special DAG nodes to represent the operation of extending the
\r
2635 switch (N->getOpcode()) {
\r
2637 llvm_unreachable("Extend legalization on on extend operation!");
\r
2638 case ISD::ANY_EXTEND:
\r
2639 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
\r
2640 case ISD::SIGN_EXTEND:
\r
2641 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
\r
2642 case ISD::ZERO_EXTEND:
\r
2643 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
\r
2647 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
\r
2648 // Since the result is legal and the input is illegal, it is unlikely
\r
2649 // that we can fix the input to a legal type so unroll the convert
\r
2650 // into some scalar code and create a nasty build vector.
\r
2651 EVT VT = N->getValueType(0);
\r
2652 EVT EltVT = VT.getVectorElementType();
\r
2654 unsigned NumElts = VT.getVectorNumElements();
\r
2655 SDValue InOp = N->getOperand(0);
\r
2656 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
\r
2657 InOp = GetWidenedVector(InOp);
\r
2658 EVT InVT = InOp.getValueType();
\r
2659 EVT InEltVT = InVT.getVectorElementType();
\r
2661 unsigned Opcode = N->getOpcode();
\r
2662 SmallVector<SDValue, 16> Ops(NumElts);
\r
2663 for (unsigned i=0; i < NumElts; ++i)
\r
2664 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
\r
2665 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
\r
2666 DAG.getConstant(i, TLI.getVectorIdxTy())));
\r
2668 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
\r
2671 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
\r
2672 EVT VT = N->getValueType(0);
\r
2673 SDValue InOp = GetWidenedVector(N->getOperand(0));
\r
2674 EVT InWidenVT = InOp.getValueType();
\r
2677 // Check if we can convert between two legal vector types and extract.
\r
2678 unsigned InWidenSize = InWidenVT.getSizeInBits();
\r
2679 unsigned Size = VT.getSizeInBits();
\r
2680 // x86mmx is not an acceptable vector element type, so don't try.
\r
2681 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
\r
2682 unsigned NewNumElts = InWidenSize / Size;
\r
2683 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
\r
2684 if (TLI.isTypeLegal(NewVT)) {
\r
2685 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
\r
2686 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
\r
2687 DAG.getConstant(0, TLI.getVectorIdxTy()));
\r
2691 return CreateStackStoreLoad(InOp, VT);
\r
2694 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
\r
2695 // If the input vector is not legal, it is likely that we will not find a
\r
2696 // legal vector of the same size. Replace the concatenate vector with a
\r
2697 // nasty build vector.
\r
2698 EVT VT = N->getValueType(0);
\r
2699 EVT EltVT = VT.getVectorElementType();
\r
2701 unsigned NumElts = VT.getVectorNumElements();
\r
2702 SmallVector<SDValue, 16> Ops(NumElts);
\r
2704 EVT InVT = N->getOperand(0).getValueType();
\r
2705 unsigned NumInElts = InVT.getVectorNumElements();
\r
2708 unsigned NumOperands = N->getNumOperands();
\r
2709 for (unsigned i=0; i < NumOperands; ++i) {
\r
2710 SDValue InOp = N->getOperand(i);
\r
2711 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
\r
2712 InOp = GetWidenedVector(InOp);
\r
2713 for (unsigned j=0; j < NumInElts; ++j)
\r
2714 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
\r
2715 DAG.getConstant(j, TLI.getVectorIdxTy()));
\r
2717 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
\r
2720 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
\r
2721 SDValue InOp = GetWidenedVector(N->getOperand(0));
\r
2722 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
\r
2723 N->getValueType(0), InOp, N->getOperand(1));
\r
2726 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
\r
2727 SDValue InOp = GetWidenedVector(N->getOperand(0));
\r
2728 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
\r
2729 N->getValueType(0), InOp, N->getOperand(1));
\r
2732 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
\r
2733 // We have to widen the value but we want only to store the original
\r
2735 StoreSDNode *ST = cast<StoreSDNode>(N);
\r
2737 SmallVector<SDValue, 16> StChain;
\r
2738 if (ST->isTruncatingStore())
\r
2739 GenWidenVectorTruncStores(StChain, ST);
\r
2741 GenWidenVectorStores(StChain, ST);
\r
2743 if (StChain.size() == 1)
\r
2744 return StChain[0];
\r
2746 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
\r
2749 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
\r
2750 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
\r
2751 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
\r
2754 // WARNING: In this code we widen the compare instruction with garbage.
\r
2755 // This garbage may contain denormal floats which may be slow. Is this a real
\r
2756 // concern ? Should we zero the unused lanes if this is a float compare ?
\r
2758 // Get a new SETCC node to compare the newly widened operands.
\r
2759 // Only some of the compared elements are legal.
\r
2760 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
\r
2761 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
\r
2762 SVT, InOp0, InOp1, N->getOperand(2));
\r
2764 // Extract the needed results from the result vector.
\r
2765 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
\r
2766 SVT.getVectorElementType(),
\r
2767 N->getValueType(0).getVectorNumElements());
\r
2768 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
\r
2769 ResVT, WideSETCC, DAG.getConstant(0,
\r
2770 TLI.getVectorIdxTy()));
\r
2772 return PromoteTargetBoolean(CC, N->getValueType(0));
\r
2776 //===----------------------------------------------------------------------===//
\r
2777 // Vector Widening Utilities
\r
2778 //===----------------------------------------------------------------------===//
\r
2780 // Utility function to find the type to chop up a widen vector for load/store
\r
2781 // TLI: Target lowering used to determine legal types.
\r
2782 // Width: Width left need to load/store.
\r
2783 // WidenVT: The widen vector type to load to/store from
\r
2784 // Align: If 0, don't allow use of a wider type
\r
2785 // WidenEx: If Align is not 0, the amount additional we can load/store from.
\r
2787 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
\r
2788 unsigned Width, EVT WidenVT,
\r
2789 unsigned Align = 0, unsigned WidenEx = 0) {
\r
2790 EVT WidenEltVT = WidenVT.getVectorElementType();
\r
2791 unsigned WidenWidth = WidenVT.getSizeInBits();
\r
2792 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
\r
2793 unsigned AlignInBits = Align*8;
\r
2795 // If we have one element to load/store, return it.
\r
2796 EVT RetVT = WidenEltVT;
\r
2797 if (Width == WidenEltWidth)
\r
2800 // See if there is larger legal integer than the element type to load/store
\r
2802 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
\r
2803 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
\r
2804 EVT MemVT((MVT::SimpleValueType) VT);
\r
2805 unsigned MemVTWidth = MemVT.getSizeInBits();
\r
2806 if (MemVT.getSizeInBits() <= WidenEltWidth)
\r
2808 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
\r
2809 isPowerOf2_32(WidenWidth / MemVTWidth) &&
\r
2810 (MemVTWidth <= Width ||
\r
2811 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
\r
2817 // See if there is a larger vector type to load/store that has the same vector
\r
2818 // element type and is evenly divisible with the WidenVT.
\r
2819 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
\r
2820 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
\r
2821 EVT MemVT = (MVT::SimpleValueType) VT;
\r
2822 unsigned MemVTWidth = MemVT.getSizeInBits();
\r
2823 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
\r
2824 (WidenWidth % MemVTWidth) == 0 &&
\r
2825 isPowerOf2_32(WidenWidth / MemVTWidth) &&
\r
2826 (MemVTWidth <= Width ||
\r
2827 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
\r
2828 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
\r
2836 // Builds a vector type from scalar loads
\r
2837 // VecTy: Resulting Vector type
\r
2838 // LDOps: Load operators to build a vector type
\r
2839 // [Start,End) the list of loads to use.
\r
2840 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
\r
2841 SmallVectorImpl<SDValue> &LdOps,
\r
2842 unsigned Start, unsigned End) {
\r
2843 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
\r
2844 SDLoc dl(LdOps[Start]);
\r
2845 EVT LdTy = LdOps[Start].getValueType();
\r
2846 unsigned Width = VecTy.getSizeInBits();
\r
2847 unsigned NumElts = Width / LdTy.getSizeInBits();
\r
2848 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
\r
2851 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
\r
2853 for (unsigned i = Start + 1; i != End; ++i) {
\r
2854 EVT NewLdTy = LdOps[i].getValueType();
\r
2855 if (NewLdTy != LdTy) {
\r
2856 NumElts = Width / NewLdTy.getSizeInBits();
\r
2857 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
\r
2858 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
\r
2859 // Readjust position and vector position based on new load type
\r
2860 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
\r
2863 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
\r
2864 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
\r
2866 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
\r
2869 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
\r
2871 // The strategy assumes that we can efficiently load powers of two widths.
\r
2872 // The routines chops the vector into the largest vector loads with the same
\r
2873 // element type or scalar loads and then recombines it to the widen vector
\r
2875 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
\r
2876 unsigned WidenWidth = WidenVT.getSizeInBits();
\r
2877 EVT LdVT = LD->getMemoryVT();
\r
2879 assert(LdVT.isVector() && WidenVT.isVector());
\r
2880 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
\r
2882 // Load information
\r
2883 SDValue Chain = LD->getChain();
\r
2884 SDValue BasePtr = LD->getBasePtr();
\r
2885 unsigned Align = LD->getAlignment();
\r
2886 bool isVolatile = LD->isVolatile();
\r
2887 bool isNonTemporal = LD->isNonTemporal();
\r
2888 bool isInvariant = LD->isInvariant();
\r
2889 AAMDNodes AAInfo = LD->getAAInfo();
\r
2891 int LdWidth = LdVT.getSizeInBits();
\r
2892 int WidthDiff = WidenWidth - LdWidth; // Difference
\r
2893 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
\r
2895 // Find the vector type that can load from.
\r
2896 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
\r
2897 int NewVTWidth = NewVT.getSizeInBits();
\r
2898 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
\r
2899 isVolatile, isNonTemporal, isInvariant, Align,
\r
2901 LdChain.push_back(LdOp.getValue(1));
\r
2903 // Check if we can load the element with one instruction
\r
2904 if (LdWidth <= NewVTWidth) {
\r
2905 if (!NewVT.isVector()) {
\r
2906 unsigned NumElts = WidenWidth / NewVTWidth;
\r
2907 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
\r
2908 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
\r
2909 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
\r
2911 if (NewVT == WidenVT)
\r
2914 assert(WidenWidth % NewVTWidth == 0);
\r
2915 unsigned NumConcat = WidenWidth / NewVTWidth;
\r
2916 SmallVector<SDValue, 16> ConcatOps(NumConcat);
\r
2917 SDValue UndefVal = DAG.getUNDEF(NewVT);
\r
2918 ConcatOps[0] = LdOp;
\r
2919 for (unsigned i = 1; i != NumConcat; ++i)
\r
2920 ConcatOps[i] = UndefVal;
\r
2921 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
\r
2924 // Load vector by using multiple loads from largest vector to scalar
\r
2925 SmallVector<SDValue, 16> LdOps;
\r
2926 LdOps.push_back(LdOp);
\r
2928 LdWidth -= NewVTWidth;
\r
2929 unsigned Offset = 0;
\r
2931 while (LdWidth > 0) {
\r
2932 unsigned Increment = NewVTWidth / 8;
\r
2933 Offset += Increment;
\r
2934 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
\r
2935 DAG.getConstant(Increment, BasePtr.getValueType()));
\r
2938 if (LdWidth < NewVTWidth) {
\r
2939 // Our current type we are using is too large, find a better size
\r
2940 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
\r
2941 NewVTWidth = NewVT.getSizeInBits();
\r
2942 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
\r
2943 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
\r
2944 isNonTemporal, isInvariant, MinAlign(Align, Increment),
\r
2946 LdChain.push_back(L.getValue(1));
\r
2947 if (L->getValueType(0).isVector()) {
\r
2948 SmallVector<SDValue, 16> Loads;
\r
2949 Loads.push_back(L);
\r
2950 unsigned size = L->getValueSizeInBits(0);
\r
2951 while (size < LdOp->getValueSizeInBits(0)) {
\r
2952 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
\r
2953 size += L->getValueSizeInBits(0);
\r
2955 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
\r
2958 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
\r
2959 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
\r
2960 isNonTemporal, isInvariant, MinAlign(Align, Increment),
\r
2962 LdChain.push_back(L.getValue(1));
\r
2965 LdOps.push_back(L);
\r
2968 LdWidth -= NewVTWidth;
\r
2971 // Build the vector from the loads operations
\r
2972 unsigned End = LdOps.size();
\r
2973 if (!LdOps[0].getValueType().isVector())
\r
2974 // All the loads are scalar loads.
\r
2975 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
\r
2977 // If the load contains vectors, build the vector using concat vector.
\r
2978 // All of the vectors used to loads are power of 2 and the scalars load
\r
2979 // can be combined to make a power of 2 vector.
\r
2980 SmallVector<SDValue, 16> ConcatOps(End);
\r
2983 EVT LdTy = LdOps[i].getValueType();
\r
2984 // First combine the scalar loads to a vector
\r
2985 if (!LdTy.isVector()) {
\r
2986 for (--i; i >= 0; --i) {
\r
2987 LdTy = LdOps[i].getValueType();
\r
2988 if (LdTy.isVector())
\r
2991 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
\r
2993 ConcatOps[--Idx] = LdOps[i];
\r
2994 for (--i; i >= 0; --i) {
\r
2995 EVT NewLdTy = LdOps[i].getValueType();
\r
2996 if (NewLdTy != LdTy) {
\r
2997 // Create a larger vector
\r
2998 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
\r
2999 makeArrayRef(&ConcatOps[Idx], End - Idx));
\r
3003 ConcatOps[--Idx] = LdOps[i];
\r
3006 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
\r
3007 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
\r
3008 makeArrayRef(&ConcatOps[Idx], End - Idx));
\r
3010 // We need to fill the rest with undefs to build the vector
\r
3011 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
\r
3012 SmallVector<SDValue, 16> WidenOps(NumOps);
\r
3013 SDValue UndefVal = DAG.getUNDEF(LdTy);
\r
3016 for (; i != End-Idx; ++i)
\r
3017 WidenOps[i] = ConcatOps[Idx+i];
\r
3018 for (; i != NumOps; ++i)
\r
3019 WidenOps[i] = UndefVal;
\r
3021 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
\r
3025 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
\r
3027 ISD::LoadExtType ExtType) {
\r
3028 // For extension loads, it may not be more efficient to chop up the vector
\r
3029 // and then extended it. Instead, we unroll the load and build a new vector.
\r
3030 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
\r
3031 EVT LdVT = LD->getMemoryVT();
\r
3033 assert(LdVT.isVector() && WidenVT.isVector());
\r
3035 // Load information
\r
3036 SDValue Chain = LD->getChain();
\r
3037 SDValue BasePtr = LD->getBasePtr();
\r
3038 unsigned Align = LD->getAlignment();
\r
3039 bool isVolatile = LD->isVolatile();
\r
3040 bool isNonTemporal = LD->isNonTemporal();
\r
3041 bool isInvariant = LD->isInvariant();
\r
3042 AAMDNodes AAInfo = LD->getAAInfo();
\r
3044 EVT EltVT = WidenVT.getVectorElementType();
\r
3045 EVT LdEltVT = LdVT.getVectorElementType();
\r
3046 unsigned NumElts = LdVT.getVectorNumElements();
\r
3048 // Load each element and widen
\r
3049 unsigned WidenNumElts = WidenVT.getVectorNumElements();
\r
3050 SmallVector<SDValue, 16> Ops(WidenNumElts);
\r
3051 unsigned Increment = LdEltVT.getSizeInBits() / 8;
\r
3052 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
\r
3053 LD->getPointerInfo(),
\r
3054 LdEltVT, isVolatile, isNonTemporal, isInvariant,
\r
3056 LdChain.push_back(Ops[0].getValue(1));
\r
3057 unsigned i = 0, Offset = Increment;
\r
3058 for (i=1; i < NumElts; ++i, Offset += Increment) {
\r
3059 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
\r
3061 DAG.getConstant(Offset,
\r
3062 BasePtr.getValueType()));
\r
3063 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
\r
3064 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
\r
3065 isVolatile, isNonTemporal, isInvariant, Align,
\r
3067 LdChain.push_back(Ops[i].getValue(1));
\r
3070 // Fill the rest with undefs
\r
3071 SDValue UndefVal = DAG.getUNDEF(EltVT);
\r
3072 for (; i != WidenNumElts; ++i)
\r
3073 Ops[i] = UndefVal;
\r
3075 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
\r
3079 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
\r
3080 StoreSDNode *ST) {
\r
3081 // The strategy assumes that we can efficiently store powers of two widths.
\r
3082 // The routines chops the vector into the largest vector stores with the same
\r
3083 // element type or scalar stores.
\r
3084 SDValue Chain = ST->getChain();
\r
3085 SDValue BasePtr = ST->getBasePtr();
\r
3086 unsigned Align = ST->getAlignment();
\r
3087 bool isVolatile = ST->isVolatile();
\r
3088 bool isNonTemporal = ST->isNonTemporal();
\r
3089 AAMDNodes AAInfo = ST->getAAInfo();
\r
3090 SDValue ValOp = GetWidenedVector(ST->getValue());
\r
3093 EVT StVT = ST->getMemoryVT();
\r
3094 unsigned StWidth = StVT.getSizeInBits();
\r
3095 EVT ValVT = ValOp.getValueType();
\r
3096 unsigned ValWidth = ValVT.getSizeInBits();
\r
3097 EVT ValEltVT = ValVT.getVectorElementType();
\r
3098 unsigned ValEltWidth = ValEltVT.getSizeInBits();
\r
3099 assert(StVT.getVectorElementType() == ValEltVT);
\r
3101 int Idx = 0; // current index to store
\r
3102 unsigned Offset = 0; // offset from base to store
\r
3103 while (StWidth != 0) {
\r
3104 // Find the largest vector type we can store with
\r
3105 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
\r
3106 unsigned NewVTWidth = NewVT.getSizeInBits();
\r
3107 unsigned Increment = NewVTWidth / 8;
\r
3108 if (NewVT.isVector()) {
\r
3109 unsigned NumVTElts = NewVT.getVectorNumElements();
\r
3111 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
\r
3112 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
\r
3113 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
\r
3114 ST->getPointerInfo().getWithOffset(Offset),
\r
3115 isVolatile, isNonTemporal,
\r
3116 MinAlign(Align, Offset), AAInfo));
\r
3117 StWidth -= NewVTWidth;
\r
3118 Offset += Increment;
\r
3120 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
\r
3121 DAG.getConstant(Increment, BasePtr.getValueType()));
\r
3122 } while (StWidth != 0 && StWidth >= NewVTWidth);
\r
3124 // Cast the vector to the scalar type we can store
\r
3125 unsigned NumElts = ValWidth / NewVTWidth;
\r
3126 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
\r
3127 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
\r
3128 // Readjust index position based on new vector type
\r
3129 Idx = Idx * ValEltWidth / NewVTWidth;
\r
3131 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
\r
3132 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
\r
3133 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
\r
3134 ST->getPointerInfo().getWithOffset(Offset),
\r
3135 isVolatile, isNonTemporal,
\r
3136 MinAlign(Align, Offset), AAInfo));
\r
3137 StWidth -= NewVTWidth;
\r
3138 Offset += Increment;
\r
3139 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
\r
3140 DAG.getConstant(Increment, BasePtr.getValueType()));
\r
3141 } while (StWidth != 0 && StWidth >= NewVTWidth);
\r
3142 // Restore index back to be relative to the original widen element type
\r
3143 Idx = Idx * NewVTWidth / ValEltWidth;
\r
3149 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
\r
3150 StoreSDNode *ST) {
\r
3151 // For extension loads, it may not be more efficient to truncate the vector
\r
3152 // and then store it. Instead, we extract each element and then store it.
\r
3153 SDValue Chain = ST->getChain();
\r
3154 SDValue BasePtr = ST->getBasePtr();
\r
3155 unsigned Align = ST->getAlignment();
\r
3156 bool isVolatile = ST->isVolatile();
\r
3157 bool isNonTemporal = ST->isNonTemporal();
\r
3158 AAMDNodes AAInfo = ST->getAAInfo();
\r
3159 SDValue ValOp = GetWidenedVector(ST->getValue());
\r
3162 EVT StVT = ST->getMemoryVT();
\r
3163 EVT ValVT = ValOp.getValueType();
\r
3165 // It must be true that we the widen vector type is bigger than where
\r
3166 // we need to store.
\r
3167 assert(StVT.isVector() && ValOp.getValueType().isVector());
\r
3168 assert(StVT.bitsLT(ValOp.getValueType()));
\r
3170 // For truncating stores, we can not play the tricks of chopping legal
\r
3171 // vector types and bit cast it to the right type. Instead, we unroll
\r
3173 EVT StEltVT = StVT.getVectorElementType();
\r
3174 EVT ValEltVT = ValVT.getVectorElementType();
\r
3175 unsigned Increment = ValEltVT.getSizeInBits() / 8;
\r
3176 unsigned NumElts = StVT.getVectorNumElements();
\r
3177 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
\r
3178 DAG.getConstant(0, TLI.getVectorIdxTy()));
\r
3179 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
\r
3180 ST->getPointerInfo(), StEltVT,
\r
3181 isVolatile, isNonTemporal, Align,
\r
3183 unsigned Offset = Increment;
\r
3184 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
\r
3185 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
\r
3186 BasePtr, DAG.getConstant(Offset,
\r
3187 BasePtr.getValueType()));
\r
3188 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
\r
3189 DAG.getConstant(0, TLI.getVectorIdxTy()));
\r
3190 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
\r
3191 ST->getPointerInfo().getWithOffset(Offset),
\r
3192 StEltVT, isVolatile, isNonTemporal,
\r
3193 MinAlign(Align, Offset), AAInfo));
\r
3197 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
\r
3198 /// input vector must have the same element type as NVT.
\r
3199 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
\r
3200 // Note that InOp might have been widened so it might already have
\r
3201 // the right width or it might need be narrowed.
\r
3202 EVT InVT = InOp.getValueType();
\r
3203 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
\r
3204 "input and widen element type must match");
\r
3207 // Check if InOp already has the right width.
\r
3211 unsigned InNumElts = InVT.getVectorNumElements();
\r
3212 unsigned WidenNumElts = NVT.getVectorNumElements();
\r
3213 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
\r
3214 unsigned NumConcat = WidenNumElts / InNumElts;
\r
3215 SmallVector<SDValue, 16> Ops(NumConcat);
\r
3216 SDValue UndefVal = DAG.getUNDEF(InVT);
\r
3218 for (unsigned i = 1; i != NumConcat; ++i)
\r
3219 Ops[i] = UndefVal;
\r
3221 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
\r
3224 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
\r
3225 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
\r
3226 DAG.getConstant(0, TLI.getVectorIdxTy()));
\r
3228 // Fall back to extract and build.
\r
3229 SmallVector<SDValue, 16> Ops(WidenNumElts);
\r
3230 EVT EltVT = NVT.getVectorElementType();
\r
3231 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
\r
3233 for (Idx = 0; Idx < MinNumElts; ++Idx)
\r
3234 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
\r
3235 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
\r
3237 SDValue UndefVal = DAG.getUNDEF(EltVT);
\r
3238 for ( ; Idx < WidenNumElts; ++Idx)
\r
3239 Ops[Idx] = UndefVal;
\r
3240 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
\r