[Hexagon] Adding sxth instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222577 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index dc58c426e94024a5e3c1c5020cf773faa03390a7..e527ab1163c463167805d1fc94b5dbfbc971a4bf 100644 (file)
--- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -934,7 +934,7 @@ SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
             if (N000 == N2 &&
                 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
                 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
-              SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl,
+              SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
                                                         MVT::i32, N000);
               SDNode *Result = CurDAG->getMachineNode(Hexagon::MAXw_rr, dl,
                                                       MVT::i32,
@@ -958,7 +958,7 @@ SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
             if (N000 == N2 &&
                 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
                 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
-              SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl,
+              SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
                                                         MVT::i32, N000);
               SDNode *Result = CurDAG->getMachineNode(Hexagon::MINw_rr, dl,
                                                       MVT::i32,

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 3c7d63487cb293935d88b0b4bbd0bc54163af8a2..29502eea267dc5fc06a07075feea792722c3d2eb 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -716,7 +716,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
   case Hexagon::ASLH:
   case Hexagon::ASRH:
   case Hexagon::A2_sxtb:
-  case Hexagon::SXTH:
+  case Hexagon::A2_sxth:
   case Hexagon::ZXTB:
   case Hexagon::ZXTH:
     return Subtarget.hasV4TOps();
@@ -1315,6 +1315,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
     case Hexagon::A2_pxorfnew:
     case Hexagon::A2_pxort:
     case Hexagon::A2_pxortnew:
+    case Hexagon::A4_psxthf:
+    case Hexagon::A4_psxthfnew:
+    case Hexagon::A4_psxtht:
+    case Hexagon::A4_psxthtnew:
     case Hexagon::A4_psxtbf:
     case Hexagon::A4_psxtbfnew:
     case Hexagon::A4_psxtbt:
@@ -1328,8 +1332,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
     case Hexagon::ASLH_cNotPt_V4:
     case Hexagon::ASRH_cPt_V4:
     case Hexagon::ASRH_cNotPt_V4:
-    case Hexagon::SXTH_cPt_V4:
-    case Hexagon::SXTH_cNotPt_V4:
     case Hexagon::ZXTB_cPt_V4:
     case Hexagon::ZXTB_cNotPt_V4:
     case Hexagon::ZXTH_cPt_V4:

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index 0e6e69f088b3fe32b0d98244f6fecabe9d1654b0..99db1801052aea17cf8c3e3283a85399d7d47e43 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -266,6 +266,7 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
 }
 
 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
+defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
 
 // Combines the two integer registers SRC1 and SRC2 into a double register.
 let isPredicable = 1 in
@@ -597,7 +598,6 @@ multiclass ALU32_2op_base2<string mnemonic> {
 
 defm ASLH : ALU32_2op_base2<"aslh">, PredNewRel;
 defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel;
-defm SXTH : ALU32_2op_base2<"sxth">,  PredNewRel;
 defm ZXTB : ALU32_2op_base2<"zxtb">, PredNewRel;
 defm ZXTH : ALU32_2op_base2<"zxth">,  PredNewRel;
 
@@ -611,7 +611,7 @@ def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
            (A2_sxtb IntRegs:$src1)>;
 
 def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
-           (SXTH IntRegs:$src1)>;
+           (A2_sxth IntRegs:$src1)>;
 
 //===----------------------------------------------------------------------===//
 // ALU32/PERM -
@@ -2350,7 +2350,7 @@ def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
 
 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
-      (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
+      (i64 (SXTW (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
                                                  subreg_loreg))))))>;
 
 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).

diff --git a/test/MC/Hexagon/inst_sxth.ll b/test/MC/Hexagon/inst_sxth.ll
new file mode 100644 (file)
index 0000000..ad0c13b
--- /dev/null
+++ b/test/MC/Hexagon/inst_sxth.ll
@@ -0,0 +1,10 @@
+;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
+;; RUN: | llvm-objdump -s - | FileCheck %s
+
+define i32 @foo (i16 %a)
+{
+  %1 = sext i16 %a to i32
+  ret i32 %1
+}
+
+; CHECK:   0000 0040e070 00c09f52
\ No newline at end of file