+++ /dev/null
-if ARCH_ROCKCHIP
-
-config RK_LAST_LOG
- bool "Save the last kernel log on /proc/last_log"
- depends on DEBUG_KERNEL && PRINTK
- default y
- help
- It is only intended for debugging.
-
-config RK_DEBUG_UART
- int "Debug UART"
- default 2
- help
- Select a UART for debugging. -1 disable.
-
-config RK_USB_UART
- bool "Support USB UART Bypass Function"
- depends on (RK_DEBUG_UART = 2)
-
-config RK_CONSOLE_THREAD
- bool "Console write by thread"
- default y
- help
- Normal kernel printk will write out to UART by "kconsole" kthread
-
-config BLOCK_RKNAND
- tristate "RK NAND Device Support"
- default n
- help
- RK NAND Device Support.
-
-config RK_FPGA
- bool "FPGA Board"
-
-config DVFS
- bool "Enable dvfs"
- default y
- select PM_OPP
- select CPU_FREQ
-
-config RK_PM_TESTS
- bool "/sys/pm_tests/ support"
- default n
- select DVFS
- select WATCHDOG
-
-config DDR_TEST
- bool "DDR Test"
- select CRC32
- default n
-
-config RK_VCODEC
- tristate "VCODEC (VPU HEVC) service driver in kernel"
- depends on ARCH_ROCKCHIP
- default y
-
-config RK_PL330_DMA_TEST
- bool "pl330 DMA memcpy test"
-
-endif
+++ /dev/null
-/*
- * Copyright (C) 2013-2014 ROCKCHIP, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/genalloc.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/of_fdt.h>
-#include <asm/cputype.h>
-#ifdef CONFIG_CACHE_L2X0
-#include <asm/hardware/cache-l2x0.h>
-#endif
-#include <linux/rockchip/common.h>
-#include <linux/rockchip/cpu_axi.h>
-#include <linux/rockchip/pmu.h>
-#include <linux/memblock.h>
-#include "loader.h"
-#include "sram.h"
-
-static int __init rockchip_cpu_axi_init(void)
-{
- struct device_node *np, *gp, *cp;
- void __iomem *base;
-
- np = of_find_compatible_node(NULL, NULL, "rockchip,cpu_axi_bus");
- if (!np)
- return -ENODEV;
-
-#define MAP(base) if (!base) base = of_iomap(cp, 0); if (!base) continue;
-
- gp = of_get_child_by_name(np, "qos");
- if (gp) {
- for_each_child_of_node(gp, cp) {
- u32 priority[2], mode, bandwidth, saturation, extcontrol;
- base = NULL;
-#ifdef DEBUG
- {
- struct resource r;
- of_address_to_resource(cp, 0, &r);
- pr_debug("qos: %s [%x ~ %x]\n", cp->name, r.start, r.end);
- }
-#endif
- if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) {
- MAP(base);
- CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], base);
- pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]);
- }
- if (!of_property_read_u32(cp, "rockchip,mode", &mode)) {
- MAP(base);
- CPU_AXI_SET_QOS_MODE(mode, base);
- pr_debug("qos: %s mode %x\n", cp->name, mode);
- }
- if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) {
- MAP(base);
- CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base);
- pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth);
- }
- if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) {
- MAP(base);
- CPU_AXI_SET_QOS_SATURATION(saturation, base);
- pr_debug("qos: %s saturation %x\n", cp->name, saturation);
- }
- if (!of_property_read_u32(cp, "rockchip,extcontrol", &extcontrol)) {
- MAP(base);
- CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base);
- pr_debug("qos: %s extcontrol %x\n", cp->name, extcontrol);
- }
- if (base)
- iounmap(base);
- }
- };
-
- gp = of_get_child_by_name(np, "msch");
- if (gp) {
- for_each_child_of_node(gp, cp) {
- u32 val;
- base = NULL;
-#ifdef DEBUG
- {
- struct resource r;
- of_address_to_resource(cp, 0, &r);
- pr_debug("msch: %s [%x ~ %x]\n", cp->name, r.start, r.end);
- }
-#endif
- if (!of_property_read_u32(cp, "rockchip,read-latency", &val)) {
- MAP(base);
- writel_relaxed(val, base + 0x0014); // memory scheduler read latency
- pr_debug("msch: %s read latency %x\n", cp->name, val);
- }
- if (base)
- iounmap(base);
- }
- }
- dsb(sy);
-
-#undef MAP
-
- return 0;
-}
-early_initcall(rockchip_cpu_axi_init);
-
-#ifdef CONFIG_CACHE_L2X0
-static int __init rockchip_pl330_l2_cache_init(void)
-{
- struct device_node *np;
- void __iomem *base;
- u32 aux[2] = { 0, ~0 }, prefetch, power;
-
- if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9)
- return -ENODEV;
-
- np = of_find_compatible_node(NULL, NULL, "rockchip,pl310-cache");
- if (!np)
- return -ENODEV;
-
- base = of_iomap(np, 0);
- if (!base)
- return -EINVAL;
-
- if (!of_property_read_u32(np, "rockchip,prefetch-ctrl", &prefetch)) {
- /* L2X0 Prefetch Control */
- writel_relaxed(prefetch, base + L2X0_PREFETCH_CTRL);
- pr_debug("l2c: prefetch %x\n", prefetch);
- }
-
- if (!of_property_read_u32(np, "rockchip,power-ctrl", &power)) {
- /* L2X0 Power Control */
- writel_relaxed(power, base + L2X0_POWER_CTRL);
- pr_debug("l2c: power %x\n", power);
- }
-
- iounmap(base);
-
- of_property_read_u32_array(np, "rockchip,aux-ctrl", aux, ARRAY_SIZE(aux));
- pr_debug("l2c: aux %08x mask %08x\n", aux[0], aux[1]);
-
- l2x0_of_init(aux[0], aux[1]);
-
- return 0;
-}
-early_initcall(rockchip_pl330_l2_cache_init);
-#endif
-
-struct gen_pool *rockchip_sram_pool = NULL;
-struct pie_chunk *rockchip_pie_chunk = NULL;
-void *rockchip_sram_virt = NULL;
-size_t rockchip_sram_size = 0;
-char *rockchip_sram_stack = NULL;
-
-#ifdef CONFIG_PIE
-int __init rockchip_pie_init(void)
-{
- struct device_node *np;
-
- np = of_find_node_by_path("/");
- if (!np)
- return -ENODEV;
-
- rockchip_sram_pool = of_get_named_gen_pool(np, "rockchip,sram", 0);
- if (!rockchip_sram_pool) {
- pr_err("%s: failed to get sram pool\n", __func__);
- return -ENODEV;
- }
- rockchip_sram_size = gen_pool_size(rockchip_sram_pool);
-
- return 0;
-}
-#endif
-
-static bool is_panic = false;
-extern void console_disable_suspend(void);
-
-static int panic_event(struct notifier_block *this, unsigned long event, void *ptr)
-{
-#if CONFIG_RK_DEBUG_UART >= 0
- console_disable_suspend();
-#endif
- is_panic = true;
- return NOTIFY_DONE;
-}
-
-static struct notifier_block panic_block = {
- .notifier_call = panic_event,
-};
-
-static int boot_mode;
-
-int rockchip_boot_mode(void)
-{
- return boot_mode;
-}
-EXPORT_SYMBOL(rockchip_boot_mode);
-
-static inline const char *boot_flag_name(u32 flag)
-{
- flag -= SYS_KERNRL_REBOOT_FLAG;
- switch (flag) {
- case BOOT_NORMAL: return "NORMAL";
- case BOOT_LOADER: return "LOADER";
- case BOOT_MASKROM: return "MASKROM";
- case BOOT_RECOVER: return "RECOVER";
- case BOOT_NORECOVER: return "NORECOVER";
- case BOOT_SECONDOS: return "SECONDOS";
- case BOOT_WIPEDATA: return "WIPEDATA";
- case BOOT_WIPEALL: return "WIPEALL";
- case BOOT_CHECKIMG: return "CHECKIMG";
- case BOOT_FASTBOOT: return "FASTBOOT";
- case BOOT_CHARGING: return "CHARGING";
- default: return "";
- }
-}
-
-static inline const char *boot_mode_name(u32 mode)
-{
- switch (mode) {
- case BOOT_MODE_NORMAL: return "NORMAL";
- case BOOT_MODE_FACTORY2: return "FACTORY2";
- case BOOT_MODE_RECOVERY: return "RECOVERY";
- case BOOT_MODE_CHARGE: return "CHARGE";
- case BOOT_MODE_POWER_TEST: return "POWER_TEST";
- case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
- case BOOT_MODE_REBOOT: return "REBOOT";
- case BOOT_MODE_PANIC: return "PANIC";
- case BOOT_MODE_WATCHDOG: return "WATCHDOG";
- case BOOT_MODE_TSADC: return "TSADC";
- default: return "";
- }
-}
-
-void __init rockchip_boot_mode_init(u32 flag, u32 mode)
-{
- boot_mode = mode;
- if (mode || ((flag & 0xff) && ((flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
- printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(mode), mode, boot_flag_name(flag), flag);
- atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
-}
-
-void rockchip_restart_get_boot_mode(const char *cmd, u32 *flag, u32 *mode)
-{
- *flag = SYS_LOADER_REBOOT_FLAG + BOOT_NORMAL;
- *mode = BOOT_MODE_REBOOT;
-
- if (cmd) {
- if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
- *flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
- else if(!strcmp(cmd, "recovery"))
- *flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
- else if (!strcmp(cmd, "fastboot"))
- *flag = SYS_LOADER_REBOOT_FLAG + BOOT_FASTBOOT;
- else if (!strcmp(cmd, "charge")) {
- *flag = SYS_LOADER_REBOOT_FLAG + BOOT_CHARGING;
- *mode = BOOT_MODE_CHARGE;
- }
- } else {
- if (is_panic)
- *mode = BOOT_MODE_PANIC;
- }
-}
-
-struct rockchip_pmu_operations rockchip_pmu_ops;
-void (*ddr_bandwidth_get)(struct ddr_bw_info *ddr_bw_ch0,
- struct ddr_bw_info *ddr_bw_ch1);
-int (*ddr_change_freq)(uint32_t nMHz) = NULL;
-long (*ddr_round_rate)(uint32_t nMHz) = NULL;
-void (*ddr_set_auto_self_refresh)(bool en) = NULL;
-int (*ddr_recalc_rate)(void) = NULL;
-
-extern struct ion_platform_data ion_pdata;
-extern void __init ion_reserve(struct ion_platform_data *data);
-extern int __init rockchip_ion_find_heap(unsigned long node,
- const char *uname, int depth, void *data);
-void __init rockchip_ion_reserve(void)
-{
-#ifdef CONFIG_ION_ROCKCHIP
- printk("%s\n", __func__);
- of_scan_flat_dt(rockchip_ion_find_heap, (void*)&ion_pdata);
- ion_reserve(&ion_pdata);
-#endif
-}
-
-bool rockchip_jtag_enabled = false;
-static int __init rockchip_jtag_enable(char *__unused)
-{
- rockchip_jtag_enabled = true;
- printk("rockchip jtag enabled\n");
- return 1;
-}
-__setup("rockchip_jtag", rockchip_jtag_enable);
-
-phys_addr_t uboot_logo_base=0;
-phys_addr_t uboot_logo_size=0;
-phys_addr_t uboot_logo_offset=0;
-
-void __init rockchip_uboot_mem_reserve(void)
-{
- if (uboot_logo_size==0)
- return;
-
- if (!memblock_is_region_reserved(uboot_logo_base, uboot_logo_size)
- && !memblock_reserve(uboot_logo_base, uboot_logo_size)){
- pr_info("%s: reserve %pa@%pa for uboot logo\n", __func__,
- &uboot_logo_size, &uboot_logo_base);
- } else {
- pr_err("%s: reserve of %pa@%pa failed\n", __func__,
- &uboot_logo_size, &uboot_logo_base);
- }
-}
-
-static int __init rockchip_uboot_logo_setup(char *p)
-{
- char *endp;
-
- uboot_logo_size = memparse(p, &endp);
- if (*endp == '@') {
- uboot_logo_base = memparse(endp + 1, &endp);
- if (*endp == ':') {
- uboot_logo_offset = memparse(endp + 1, NULL);
- }
- }
-
- pr_info("%s: mem: %pa@%pa, offset:%pa\n", __func__,
- &uboot_logo_size, &uboot_logo_base, &uboot_logo_offset);
-
- return 0;
-}
-early_param("uboot_logo", rockchip_uboot_logo_setup);
-
-static int __init rockchip_uboot_mem_late_init(void)
-{
- phys_addr_t addr = 0;
- phys_addr_t end = 0;
-
- if (uboot_logo_size) {
- addr = PAGE_ALIGN(uboot_logo_base);
- end = (uboot_logo_base+uboot_logo_size)&PAGE_MASK;
-
- pr_info("%s: Freeing uboot logo memory: %pa@%pa\n", __func__,
- &uboot_logo_size, &uboot_logo_base);
-
- memblock_free(uboot_logo_base, uboot_logo_size);
-
- for (; addr < end; addr += PAGE_SIZE)
- free_reserved_page(pfn_to_page(addr >> PAGE_SHIFT));
- }
-
- return 0;
-}
-late_initcall(rockchip_uboot_mem_late_init);
+++ /dev/null
-#include <linux/kernel.h>
-#include <linux/cpu.h>
-#include <linux/rockchip/cpu.h>
-
-unsigned long rockchip_soc_id;
-EXPORT_SYMBOL(rockchip_soc_id);
-
-static ssize_t type_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- const char *type;
-
- if (cpu_is_rk3288())
- type = "rk3288";
- else if (cpu_is_rk319x())
- type = "rk319x";
- else if (cpu_is_rk3188())
- type = "rk3188";
- else if (cpu_is_rk3066b())
- type = "rk3066b";
- else if (cpu_is_rk3026())
- type = "rk3026";
- else if (cpu_is_rk30xx())
- type = "rk30xx";
- else if (cpu_is_rk2928())
- type = "rk2928";
- else if (cpu_is_rk312x())
- type = "rk312x";
- else
- type = "";
-
- if (rockchip_get_cpu_version())
- return sprintf(buf, "%sv%lu\n", type,
- rockchip_get_cpu_version());
-
- return sprintf(buf, "%s\n", type);
-}
-
-static struct device_attribute type_attr = __ATTR_RO(type);
-
-static ssize_t soc_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
- const char *soc;
-
- if (soc_is_rk3288())
- soc = "rk3288";
- else if (soc_is_rk3190())
- soc = "rk3190";
- else if (soc_is_rk3188plus())
- soc = "rk3188+";
- else if (soc_is_rk3188())
- soc = "rk3188";
- else if (soc_is_rk3168())
- soc = "rk3168";
- else if (soc_is_rk3028())
- soc = "rk3028";
- else if (soc_is_rk3066b())
- soc = "rk3066b";
- else if (soc_is_rk3028a())
- soc = "rk3028a";
- else if (soc_is_rk3026())
- soc = "rk3026";
- else if (soc_is_rk2928g())
- soc = "rk2928g";
- else if (soc_is_rk2928l())
- soc = "rk2928l";
- else if (soc_is_rk2926())
- soc = "rk2926";
- else if (soc_is_rk3066())
- soc = "rk3066";
- else if (soc_is_rk3068())
- soc = "rk3068";
- else if (soc_is_rk3000())
- soc = "rk3000";
- else if (soc_is_rk3126() || soc_is_rk3126b())
- soc = "rk3126";
- else if (soc_is_rk3128())
- soc = "rk3128";
- else
- soc = "";
-
- return sprintf(buf, "%s\n", soc);
-}
-
-static struct device_attribute soc_attr = __ATTR_RO(soc);
-
-static int __init rockchip_cpu_lateinit(void)
-{
- int err;
-
- err = device_create_file(cpu_subsys.dev_root, &type_attr);
- err = device_create_file(cpu_subsys.dev_root, &soc_attr);
-
- return err;
-}
-late_initcall(rockchip_cpu_lateinit);
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 ROCKCHIP, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/cpuidle.h>
-#include <linux/export.h>
-#include <linux/suspend.h>
-#include <linux/err.h>
-#include <linux/irqchip/arm-gic.h>
-#include <asm/cpuidle.h>
-#include <asm/cputype.h>
-#include <asm/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/rockchip/cpu.h>
-
-static void __iomem *gic_cpu_base;
-
-static int rockchip_ca9_cpuidle_enter(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
-{
- do {
- cpu_do_idle();
- } while (readl_relaxed(gic_cpu_base + GIC_CPU_HIGHPRI) == 0x3FF);
- return 0;
-}
-
-static struct cpuidle_driver rockchip_ca9_cpuidle_driver = {
- .name = "rockchip_ca9_cpuidle",
- .owner = THIS_MODULE,
- .states[0] = ARM_CPUIDLE_WFI_STATE,
- .state_count = 1,
-};
-
-static int __init rockchip_ca9_cpuidle_init(void)
-{
- struct device_node *np;
- int ret;
-
- if (!cpu_is_rockchip())
- return -ENODEV;
- if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9)
- return -ENODEV;
- np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
- if (!np)
- return -ENODEV;
- gic_cpu_base = of_iomap(np, 1);
- if (!gic_cpu_base) {
- pr_err("%s: failed to map gic cpu registers\n", __func__);
- return -EINVAL;
- }
- rockchip_ca9_cpuidle_driver.states[0].enter = rockchip_ca9_cpuidle_enter;
- ret = cpuidle_register(&rockchip_ca9_cpuidle_driver, NULL);
- if (ret)
- pr_err("%s: failed to register cpuidle driver: %d\n", __func__, ret);
-
- return ret;
-}
-
-device_initcall(rockchip_ca9_cpuidle_init);
+++ /dev/null
-#define pr_fmt(fmt) "ddrfreq: " fmt
-#define DEBUG
-#include <linux/clk.h>
-#include <linux/fb.h>
-#include <linux/cpu.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-#include <linux/freezer.h>
-#include <linux/fs.h>
-#include <linux/kthread.h>
-#include <linux/miscdevice.h>
-#include <linux/module.h>
-#include <linux/reboot.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-#include <linux/sched/rt.h>
-#include <linux/of.h>
-#include <linux/fb.h>
-#include <linux/input.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <linux/vmalloc.h>
-#include <linux/rockchip/common.h>
-#include <linux/rockchip/cpu_axi.h>
-#include <linux/rockchip/dvfs.h>
-#include <dt-bindings/clock/ddr.h>
-#include <dt-bindings/clock/rk_system_status.h>
-#include <asm/io.h>
-#include <linux/rockchip/grf.h>
-#include <linux/rockchip/iomap.h>
-#include <linux/clk-private.h>
-#include <linux/rockchip/cpu.h>
-#include "../../../drivers/clk/rockchip/clk-pd.h"
-
-static DECLARE_COMPLETION(ddrfreq_completion);
-static DEFINE_MUTEX(ddrfreq_mutex);
-
-#define VOP_REQ_BLOCK
-#ifdef VOP_REQ_BLOCK
-static DECLARE_COMPLETION(vop_req_completion);
-#endif
-
-static struct dvfs_node *clk_cpu_dvfs_node = NULL;
-static int ddr_boost = 0;
-static int print=0;
-static int watch=0;
-static int high_load = 70;
-static int low_load = 60;
-static int auto_freq_interval_ms = 20;
-static int down_rate_delay_ms = 500;
-static unsigned long *auto_freq_table = NULL;
-static int cur_freq_index;
-static int auto_freq_table_size;
-static unsigned long vop_bandwidth_update_jiffies = 0, vop_bandwidth = 0;
-static int vop_bandwidth_update_flag = 0;
-static struct ddr_bw_info ddr_bw_ch0 = {0}, ddr_bw_ch1 = {0};
-static struct cpufreq_frequency_table *bd_freq_table;
-
-enum {
- DEBUG_DDR = 1U << 0,
- DEBUG_VIDEO_STATE = 1U << 1,
- DEBUG_SUSPEND = 1U << 2,
- DEBUG_VERBOSE = 1U << 3,
-};
-static int debug_mask;
-
-module_param(debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
-#define dprintk(mask, fmt, ...) do { if (mask & debug_mask) pr_debug(fmt, ##__VA_ARGS__); } while (0)
-
-#define MHZ (1000*1000)
-#define KHZ 1000
-
-struct video_info {
- int width;
- int height;
- int ishevc;
- int videoFramerate;
- int streamBitrate;
-
- struct list_head node;
-};
-struct vop_info {
- int state;
- int zone_num;
- int reserve;
- int reserve2;
-};
-
-struct bpvopinfo {
- struct vop_info vopinfo[4];
- int bp_size;
- int bp_vop_size;
-};
-
-struct ddr {
- struct dvfs_node *clk_dvfs_node;
- struct list_head video_info_list;
- unsigned long normal_rate;
- unsigned long video_1080p_rate;
- unsigned long video_4k_rate;
- unsigned long performance_rate;
- unsigned long dualview_rate;
- unsigned long hdmi_rate;
- unsigned long idle_rate;
- unsigned long suspend_rate;
- unsigned long reboot_rate;
- unsigned long boost_rate;
- unsigned long isp_rate;
- bool auto_freq;
- bool auto_self_refresh;
- char *mode;
- unsigned long sys_status;
- struct task_struct *task;
- wait_queue_head_t wait;
-};
-static struct ddr ddr;
-
-module_param_named(sys_status, ddr.sys_status, ulong, S_IRUGO);
-module_param_named(auto_self_refresh, ddr.auto_self_refresh, bool, S_IRUGO);
-module_param_named(mode, ddr.mode, charp, S_IRUGO);
-
-static unsigned long auto_freq_round(unsigned long freq)
-{
- int i;
-
- if (!auto_freq_table)
- return -EINVAL;
-
- for (i = 0; auto_freq_table[i] != 0; i++) {
- if (auto_freq_table[i] >= freq) {
- return auto_freq_table[i];
- }
- }
-
- return auto_freq_table[i-1];
-}
-
-static unsigned long auto_freq_get_index(unsigned long freq)
-{
- int i;
-
- if (!auto_freq_table)
- return 0;
-
- for (i = 0; auto_freq_table[i] != 0; i++) {
- if (auto_freq_table[i] >= freq) {
- return i;
- }
- }
- return i-1;
-}
-
-static unsigned int auto_freq_update_index(unsigned long freq)
-{
- cur_freq_index = auto_freq_get_index(freq);
-
- return cur_freq_index;
-}
-
-
-static unsigned long auto_freq_get_next_step(void)
-{
- if (cur_freq_index < auto_freq_table_size-1) {
- return auto_freq_table[cur_freq_index+1];
- }
-
- return auto_freq_table[cur_freq_index];
-}
-
-static void ddrfreq_mode(bool auto_self_refresh, unsigned long target_rate, char *name)
-{
- unsigned int min_rate, max_rate;
- int freq_limit_en;
-
- ddr.mode = name;
- if (auto_self_refresh != ddr.auto_self_refresh) {
- ddr_set_auto_self_refresh(auto_self_refresh);
- ddr.auto_self_refresh = auto_self_refresh;
- dprintk(DEBUG_DDR, "change auto self refresh to %d when %s\n", auto_self_refresh, name);
- }
-
- if (target_rate != dvfs_clk_get_last_set_rate(ddr.clk_dvfs_node)) {
- if (clk_cpu_dvfs_node) {
- freq_limit_en = dvfs_clk_get_limit(clk_cpu_dvfs_node,
- &min_rate,
- &max_rate);
-
- dvfs_clk_enable_limit(clk_cpu_dvfs_node, 600000000, -1);
- }
- if (dvfs_clk_set_rate(ddr.clk_dvfs_node, target_rate) == 0) {
- target_rate = dvfs_clk_get_rate(ddr.clk_dvfs_node);
- auto_freq_update_index(target_rate);
- dprintk(DEBUG_DDR, "change freq to %lu MHz when %s\n", target_rate / MHZ, name);
- }
- if (clk_cpu_dvfs_node) {
- if (freq_limit_en) {
- dvfs_clk_enable_limit(clk_cpu_dvfs_node,
- min_rate, max_rate);
- } else {
- dvfs_clk_disable_limit(clk_cpu_dvfs_node);
- }
- }
- }
-}
-
-unsigned long req_freq_by_vop(unsigned long bandwidth)
-{
- unsigned int i = 0;
-
- if (time_after(jiffies, vop_bandwidth_update_jiffies +
- msecs_to_jiffies(down_rate_delay_ms)))
- return 0;
-
- if (bd_freq_table == NULL)
- return 0;
- for (i = 0; bd_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
- if (bandwidth >= bd_freq_table[i].index)
- return bd_freq_table[i].frequency * 1000;
- }
-
- return 0;
-}
-
-static void ddr_auto_freq(void)
-{
- unsigned long freq, new_freq=0, vop_req_freq=0, total_bw_req_freq=0;
- u32 ddr_percent, target_load;
- static unsigned long local_jiffies=0, max_ddr_percent=0;
-
- if (!local_jiffies)
- local_jiffies = jiffies;
- freq = dvfs_clk_get_rate(ddr.clk_dvfs_node);
-
- ddr_bandwidth_get(&ddr_bw_ch0, &ddr_bw_ch1);
- ddr_percent = ddr_bw_ch0.ddr_percent;
-
- if ((watch)||(print)) {
- if((watch == 2)&& (ddr_bw_ch0.ddr_percent < max_ddr_percent)) {
- return;
- } else if(watch == 2) {
- max_ddr_percent = ddr_bw_ch0.ddr_percent;
- }
- printk("Unit:MB/s total use%% rd wr cpum gpu peri video vio0 vio1 vio2\n");
- printk("%3u(ms): %5u %5u %5u %5u %5u %5u %5u %5u %5u %5u %5u\n",
- ddr_bw_ch0.ddr_time,
- ddr_bw_ch0.ddr_total,
- ddr_bw_ch0.ddr_percent,
- ddr_bw_ch0.ddr_rd,
- ddr_bw_ch0.ddr_wr,
- ddr_bw_ch0.cpum,
- ddr_bw_ch0.gpu,
- ddr_bw_ch0.peri,
- ddr_bw_ch0.video,
- ddr_bw_ch0.vio0,
- ddr_bw_ch0.vio1,
- ddr_bw_ch0.vio2);
-
- if (watch)
- return;
- }
-
- if (ddr_boost) {
- ddr_boost = 0;
- new_freq = max(ddr.boost_rate, new_freq);
- }
-
- if(ddr_percent > high_load){
- total_bw_req_freq = auto_freq_get_next_step();
- } else if (ddr_percent < low_load){
- target_load = (low_load+high_load)/2;
- total_bw_req_freq = ddr_percent*(freq/target_load);
- }
- new_freq = max(total_bw_req_freq, new_freq);
-
- vop_req_freq = req_freq_by_vop(vop_bandwidth);
- new_freq = max(vop_req_freq, new_freq);
- if (new_freq == 0)
- return;
-
- new_freq = auto_freq_round(new_freq);
-
- if (new_freq < freq) {
- if (time_after(jiffies, local_jiffies+down_rate_delay_ms/10)) {
- local_jiffies = jiffies;
- ddrfreq_mode(false, new_freq, "auto down rate");
- }
- } else if(new_freq > freq){
- local_jiffies = jiffies;
- ddrfreq_mode(false, new_freq, "auto up rate");
- }
-}
-
-static noinline long ddrfreq_work(unsigned long sys_status)
-{
- long timeout = MAX_SCHEDULE_TIMEOUT;
- unsigned long target_rate = 0;
- unsigned long s = sys_status;
- bool auto_self_refresh = false;
- char *mode = NULL;
-
- dprintk(DEBUG_VERBOSE, "sys_status %02lx\n", sys_status);
-
- if (ddr.reboot_rate && (s & SYS_STATUS_REBOOT)) {
- ddrfreq_mode(false, ddr.reboot_rate, "shutdown/reboot");
-
- return timeout;
- }
-
- if (ddr.suspend_rate && (s & SYS_STATUS_SUSPEND)) {
- if (ddr.suspend_rate > target_rate) {
- target_rate = ddr.suspend_rate;
- auto_self_refresh = true;
- mode = "suspend";
- }
- }
-
- if (ddr.performance_rate && (s & SYS_STATUS_PERFORMANCE)) {
- if (ddr.performance_rate > target_rate) {
- target_rate = ddr.performance_rate;
- auto_self_refresh = false;
- mode = "performance";
- }
- }
-
- if (ddr.dualview_rate &&
- (s & SYS_STATUS_LCDC0) && (s & SYS_STATUS_LCDC1)) {
- if (ddr.dualview_rate > target_rate) {
- target_rate = ddr.dualview_rate;
- auto_self_refresh = false;
- mode = "dual-view";
- }
- }
-
- if (ddr.hdmi_rate &&
- (s & SYS_STATUS_HDMI)) {
- if (ddr.hdmi_rate > target_rate) {
- target_rate = ddr.hdmi_rate;
- auto_self_refresh = false;
- mode = "hdmi";
- }
- }
-
- if (ddr.video_4k_rate && (s & SYS_STATUS_VIDEO_4K) && !(s & SYS_STATUS_SUSPEND)) {
- if (ddr.video_4k_rate > target_rate) {
- target_rate = ddr.video_4k_rate;
- auto_self_refresh = false;
- mode = "video_4k";
- }
- }
-
- if (ddr.video_1080p_rate && (s & SYS_STATUS_VIDEO_1080P)) {
- if (ddr.video_1080p_rate > target_rate) {
- target_rate = ddr.video_1080p_rate;
- auto_self_refresh = false;
- mode = "video_1080p";
- }
- }
-
- if (ddr.isp_rate && (s & SYS_STATUS_ISP)) {
- if (ddr.isp_rate > target_rate) {
- target_rate = ddr.isp_rate;
- auto_self_refresh = false;
- mode = "isp";
- }
- }
-
- if (target_rate > 0) {
- ddrfreq_mode(auto_self_refresh, target_rate, mode);
- } else {
- if (ddr.auto_freq) {
- ddr_auto_freq();
- timeout = auto_freq_interval_ms/10;
- }
- else {
- ddrfreq_mode(false, ddr.normal_rate, "normal");
- }
- }
-
- return timeout;
-#if 0
-
- if (ddr.reboot_rate && (s & SYS_STATUS_REBOOT)) {
- ddrfreq_mode(false, &ddr.reboot_rate, "shutdown/reboot");
- rockchip_cpufreq_reboot_limit_freq();
- reboot_config_done = 1;
- } else if (ddr.suspend_rate && (s & SYS_STATUS_SUSPEND)) {
- ddrfreq_mode(true, &ddr.suspend_rate, "suspend");
- } else if (ddr.dualview_rate &&
- (s & SYS_STATUS_LCDC0) && (s & SYS_STATUS_LCDC1)) {
- ddrfreq_mode(false, &ddr.dualview_rate, "dual-view");
- } else if (ddr.video_1080p_rate && (s & SYS_STATUS_VIDEO_1080P)) {
- ddrfreq_mode(false, &ddr.video_1080p_rate, "video_1080p");
- } else if (ddr.video_4k_rate && (s & SYS_STATUS_VIDEO_4K)) {
- ddrfreq_mode(false, &ddr.video_4k_rate, "video_4k");
- } else if (ddr.performance_rate && (s & SYS_STATUS_PERFORMANCE)) {
- ddrfreq_mode(false, &ddr.performance_rate, "performance");
- } else if (ddr.isp_rate && (s & SYS_STATUS_ISP)) {
- ddrfreq_mode(false, &ddr.isp_rate, "isp");
- } else if (ddr.idle_rate
- && !(s & SYS_STATUS_GPU)
- && !(s & SYS_STATUS_RGA)
- && !(s & SYS_STATUS_CIF0)
- && !(s & SYS_STATUS_CIF1)
- && (clk_get_rate(cpu) < 816 * MHZ)
- && (clk_get_rate(gpu) <= 200 * MHZ)
- ) {
- ddrfreq_mode(false, &ddr.idle_rate, "idle");
- } else {
- if (ddr.auto_freq) {
- ddr_auto_freq();
- timeout = auto_freq_interval_ms;
- }
- else {
- ddrfreq_mode(false, &ddr.normal_rate, "normal");
- }
- }
-
-
-
- return timeout;
-#endif
-}
-
-static int ddrfreq_task(void *data)
-{
- long timeout;
- unsigned long status=ddr.sys_status, old_status=ddr.sys_status;
-
- set_freezable();
-
- do {
- status = ddr.sys_status;
- timeout = ddrfreq_work(status);
- if (old_status != status)
- complete(&ddrfreq_completion);
- if (vop_bandwidth_update_flag) {
- vop_bandwidth_update_flag = 0;
-#ifdef VOP_REQ_BLOCK
- complete(&vop_req_completion);
-#endif
- }
- wait_event_freezable_timeout(ddr.wait, vop_bandwidth_update_flag || (status != ddr.sys_status) || kthread_should_stop(), timeout);
- old_status = status;
- } while (!kthread_should_stop());
-
- return 0;
-}
-
-void add_video_info(struct video_info *video_info)
-{
- if (video_info)
- list_add(&video_info->node, &ddr.video_info_list);
-}
-
-void del_video_info(struct video_info *video_info)
-{
- if (video_info) {
- list_del(&video_info->node);
- kfree(video_info);
- }
-}
-
-void clear_video_info(void)
-{
- struct video_info *video_info, *next;
-
- list_for_each_entry_safe(video_info, next, &ddr.video_info_list, node) {
- del_video_info(video_info);
- }
-}
-
-struct video_info *find_video_info(struct video_info *match_video_info)
-{
- struct video_info *video_info;
-
- if (!match_video_info)
- return NULL;
-
- list_for_each_entry(video_info, &ddr.video_info_list, node) {
- if ((video_info->width == match_video_info->width)
- && (video_info->height == match_video_info->height)
- && (video_info->ishevc== match_video_info->ishevc)
- && (video_info->videoFramerate == match_video_info->videoFramerate)
- && (video_info->streamBitrate== match_video_info->streamBitrate)) {
-
- return video_info;
- }
-
- }
-
- return NULL;
-}
-
-void update_video_info(void)
-{
- struct video_info *video_info, *max_res_video;
- int max_res=0, res=0;
-
- if (list_empty(&ddr.video_info_list)) {
- rockchip_clear_system_status(SYS_STATUS_VIDEO_1080P|SYS_STATUS_VIDEO_4K);
- return;
- }
-
- list_for_each_entry(video_info, &ddr.video_info_list, node) {
- res = video_info->width * video_info->height;
- if (res > max_res) {
- max_res = res;
- max_res_video = video_info;
- }
- }
-
- if (max_res <= 1920*1080)
- rockchip_set_system_status(SYS_STATUS_VIDEO_1080P);
- else
- rockchip_set_system_status(SYS_STATUS_VIDEO_4K);
-
- return;
-}
-
-/***format: width=val,height=val,ishevc=val,videoFramerate=val,streamBitrate=val***/
-static long get_video_param(char **str)
-{
- char *p;
-
- strsep(str,"=");
- p=strsep(str,",");
- if (p)
- return simple_strtol(p,NULL,10);
-
- return 0;
-}
-
-static ssize_t video_state_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *ppos)
-{
- struct video_info *video_info = NULL;
- char state, *cookie_pot, *buf = vzalloc(count);
- cookie_pot = buf;
-
- if(!buf)
- return -ENOMEM;
-
- if (count < 1){
- vfree(buf);
- return -EPERM;
- }
-
- if (copy_from_user(cookie_pot, buffer, count)) {
- vfree(buf);
- return -EFAULT;
- }
-
- dprintk(DEBUG_VIDEO_STATE, "%s: %s,len %zu\n", __func__, cookie_pot,count);
-
- state=cookie_pot[0];
- if( (count>=3) && (cookie_pot[2]=='w') )
- {
- video_info = kzalloc(sizeof(struct video_info), GFP_KERNEL);
- if (!video_info){
- vfree(buf);
- return -ENOMEM;
- }
- INIT_LIST_HEAD(&video_info->node);
-
- strsep(&cookie_pot,",");
-
- video_info->width = get_video_param(&cookie_pot);
- video_info->height = get_video_param(&cookie_pot);
- video_info->ishevc = get_video_param(&cookie_pot);
- video_info->videoFramerate = get_video_param(&cookie_pot);
- video_info->streamBitrate = get_video_param(&cookie_pot);
-
- dprintk(DEBUG_VIDEO_STATE, "%s: video_state=%c,width=%d,height=%d,ishevc=%d,videoFramerate=%d,streamBitrate=%d\n",
- __func__, state,video_info->width,video_info->height,
- video_info->ishevc, video_info->videoFramerate,
- video_info->streamBitrate);
-
- }
- switch (state) {
- case '0':
- del_video_info(find_video_info(video_info));
- kfree(video_info);
- update_video_info();
- break;
- case '1':
- add_video_info(video_info);
- update_video_info();
- break;
- case 'p'://performance
- rockchip_set_system_status(SYS_STATUS_PERFORMANCE);
- break;
- case 'n'://normal
- rockchip_clear_system_status(SYS_STATUS_PERFORMANCE);
- break;
- default:
- vfree(buf);
- return -EINVAL;
-
- }
-
- vfree(buf);
- return count;
-}
-
-static int video_state_release(struct inode *inode, struct file *file)
-{
- dprintk(DEBUG_VIDEO_STATE, "video_state release\n");
- clear_video_info();
- update_video_info();
- return 0;
-}
-
-
-static const struct file_operations video_state_fops = {
- .owner = THIS_MODULE,
- .release= video_state_release,
- .write = video_state_write,
-};
-
-static struct miscdevice video_state_dev = {
- .fops = &video_state_fops,
- .name = "video_state",
- .minor = MISC_DYNAMIC_MINOR,
-};
-
-static long ddr_freq_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct bpvopinfo *bpvinfo = (struct bpvopinfo *)arg;
- unsigned long vop_req_freq;
- int ret = -1;
-
- vop_bandwidth = bpvinfo->bp_vop_size;
- vop_bandwidth_update_jiffies = jiffies;
- vop_req_freq = req_freq_by_vop(vop_bandwidth);
- if (dvfs_clk_get_rate(ddr.clk_dvfs_node) >= vop_req_freq)
- ret = 0;
-
- vop_bandwidth_update_flag = 1;
- wake_up(&ddr.wait);
-#ifdef VOP_REQ_BLOCK
- wait_for_completion(&vop_req_completion);
- if (dvfs_clk_get_rate(ddr.clk_dvfs_node) >= vop_req_freq)
- ret = 0;
-#endif
-
- return ret;
-}
-
-
-static const struct file_operations ddr_freq_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = ddr_freq_ioctl,
-#ifdef CONFIG_COMPAT
- .compat_ioctl = ddr_freq_ioctl,
-#endif
-};
-
-static struct miscdevice ddr_freq_dev = {
- .fops = &ddr_freq_fops,
- .name = "ddr_freq",
- .mode = S_IRUGO | S_IWUSR | S_IWUGO,
- .minor = MISC_DYNAMIC_MINOR,
-};
-
-#ifdef CONFIG_INPUT
-static void ddr_freq_input_event(struct input_handle *handle, unsigned int type,
- unsigned int code, int value)
-{
- if (type == EV_ABS)
- ddr_boost = 1;
-}
-
-static int ddr_freq_input_connect(struct input_handler *handler,
- struct input_dev *dev, const struct input_device_id *id)
-{
- struct input_handle *handle;
- int error;
-
- handle = kzalloc(sizeof(struct input_handle), GFP_KERNEL);
- if (!handle)
- return -ENOMEM;
-
- handle->dev = dev;
- handle->handler = handler;
- handle->name = "ddr_freq";
-
- error = input_register_handle(handle);
- if (error)
- goto err2;
-
- error = input_open_device(handle);
- if (error)
- goto err1;
-
- return 0;
-err1:
- input_unregister_handle(handle);
-err2:
- kfree(handle);
- return error;
-}
-
-static void ddr_freq_input_disconnect(struct input_handle *handle)
-{
- input_close_device(handle);
- input_unregister_handle(handle);
- kfree(handle);
-}
-
-static const struct input_device_id ddr_freq_ids[] = {
- {
- .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
- INPUT_DEVICE_ID_MATCH_ABSBIT,
- .evbit = { BIT_MASK(EV_ABS) },
- .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
- BIT_MASK(ABS_MT_POSITION_X) |
- BIT_MASK(ABS_MT_POSITION_Y) },
- },
- {
- .flags = INPUT_DEVICE_ID_MATCH_KEYBIT |
- INPUT_DEVICE_ID_MATCH_ABSBIT,
- .keybit = { [BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH) },
- .absbit = { [BIT_WORD(ABS_X)] =
- BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) },
- },
- {
- .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
- .evbit = { BIT_MASK(EV_KEY) },
- },
- { },
-};
-
-static struct input_handler ddr_freq_input_handler = {
- .event = ddr_freq_input_event,
- .connect = ddr_freq_input_connect,
- .disconnect = ddr_freq_input_disconnect,
- .name = "ddr_freq",
- .id_table = ddr_freq_ids,
-};
-#endif
-#if 0
-static int ddrfreq_clk_event(int status, unsigned long event)
-{
- switch (event) {
- case RK_CLK_PD_PREPARE:
- ddrfreq_set_sys_status(status);
- break;
- case RK_CLK_PD_UNPREPARE:
- ddrfreq_clear_sys_status(status);
- break;
- }
- return NOTIFY_OK;
-}
-
-#define CLK_NOTIFIER(name, status) \
-static int ddrfreq_clk_##name##_event(struct notifier_block *this, unsigned long event, void *ptr) \
-{ \
- return ddrfreq_clk_event(SYS_STATUS_##status, event); \
-} \
-static struct notifier_block ddrfreq_clk_##name##_notifier = { .notifier_call = ddrfreq_clk_##name##_event };
-
-#define REGISTER_CLK_NOTIFIER(name) \
-do { \
- struct clk *clk = clk_get(NULL, #name); \
- rk_clk_pd_notifier_register(clk, &ddrfreq_clk_##name##_notifier); \
- clk_put(clk); \
-} while (0)
-
-#define UNREGISTER_CLK_NOTIFIER(name) \
-do { \
- struct clk *clk = clk_get(NULL, #name); \
- rk_clk_pd_notifier_unregister(clk, &ddrfreq_clk_##name##_notifier); \
- clk_put(clk); \
-} while (0)
-
-CLK_NOTIFIER(pd_isp, ISP)
-CLK_NOTIFIER(pd_vop0, LCDC0)
-CLK_NOTIFIER(pd_vop1, LCDC1)
-#endif
-
-static int ddr_freq_suspend_notifier_call(struct notifier_block *self,
- unsigned long action, void *data)
-{
- struct fb_event *event = data;
-
- if (action == FB_EARLY_EVENT_BLANK) {
- switch (*((int *)event->data)) {
- case FB_BLANK_UNBLANK:
- rockchip_clear_system_status(SYS_STATUS_SUSPEND);
- break;
- default:
- break;
- }
- }
- else if (action == FB_EVENT_BLANK) {
- switch (*((int *)event->data)) {
- case FB_BLANK_POWERDOWN:
- rockchip_set_system_status(SYS_STATUS_SUSPEND);
- break;
- default:
- break;
- }
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block ddr_freq_suspend_notifier = {
- .notifier_call = ddr_freq_suspend_notifier_call,
-};
-
-static int ddrfreq_system_status_notifier_call(struct notifier_block *nb,
- unsigned long val, void *data)
-{
- mutex_lock(&ddrfreq_mutex);
- ddr.sys_status = val;
- wake_up(&ddr.wait);
- wait_for_completion(&ddrfreq_completion);
- mutex_unlock(&ddrfreq_mutex);
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block ddrfreq_system_status_notifier = {
- .notifier_call = ddrfreq_system_status_notifier_call,
-};
-
-static struct cpufreq_frequency_table
- *of_get_bd_freq_table(struct device_node *np, const char *propname)
-{
- struct cpufreq_frequency_table *freq_table = NULL;
- const struct property *prop;
- const __be32 *val;
- int nr, i;
-
- prop = of_find_property(np, propname, NULL);
- if (!prop)
- return NULL;
- if (!prop->value)
- return NULL;
-
- nr = prop->length / sizeof(u32);
- if (nr % 2) {
- pr_err("%s: Invalid freq list\n", __func__);
- return NULL;
- }
-
- freq_table = kzalloc(sizeof(*freq_table) * (nr/2 + 1), GFP_KERNEL);
-
- val = prop->value;
-
- for (i = 0; i < nr/2; i++) {
- freq_table[i].index = be32_to_cpup(val++);
- freq_table[i].frequency = be32_to_cpup(val++);
- }
-
- freq_table[i].index = 0;
- freq_table[i].frequency = CPUFREQ_TABLE_END;
-
- return freq_table;
-}
-
-int of_init_ddr_freq_table(void)
-{
- struct device_node *clk_ddr_dev_node;
- const struct property *prop;
- const __be32 *val;
- int nr, i=0;
-
- clk_ddr_dev_node = of_find_node_by_name(NULL, "clk_ddr");
- if (IS_ERR_OR_NULL(clk_ddr_dev_node)) {
- pr_err("%s: get clk ddr dev node err\n", __func__);
- return PTR_ERR(clk_ddr_dev_node);
- }
-
- prop = of_find_property(clk_ddr_dev_node, "auto-freq", NULL);
- if (prop && prop->value)
- ddr.auto_freq = be32_to_cpup(prop->value);
-
- prop = of_find_property(clk_ddr_dev_node, "auto-freq-table", NULL);
- if (prop && prop->value) {
- nr = prop->length / sizeof(u32);
- auto_freq_table = kzalloc((sizeof(u32) *(nr+1)), GFP_KERNEL);
- val = prop->value;
- while (nr) {
- auto_freq_table[i++] =
- dvfs_clk_round_rate(ddr.clk_dvfs_node, 1000 * be32_to_cpup(val++));
- nr--;
- }
- cur_freq_index = 0;
- auto_freq_table_size = i;
- }
-
- prop = of_find_property(clk_ddr_dev_node, "freq-table", NULL);
- if (!prop)
- return -ENODEV;
- if (!prop->value)
- return -ENODATA;
-
- nr = prop->length / sizeof(u32);
- if (nr % 2) {
- pr_err("%s: Invalid freq list\n", __func__);
- return -EINVAL;
- }
-
- val = prop->value;
- while (nr) {
- unsigned long status = be32_to_cpup(val++);
- unsigned long rate =
- dvfs_clk_round_rate(ddr.clk_dvfs_node, be32_to_cpup(val++) * 1000);
-
- if (status & SYS_STATUS_NORMAL)
- ddr.normal_rate = rate;
- if (status & SYS_STATUS_SUSPEND)
- ddr.suspend_rate = rate;
- if (status & SYS_STATUS_VIDEO_1080P)
- ddr.video_1080p_rate = rate;
- if (status & SYS_STATUS_VIDEO_4K)
- ddr.video_4k_rate = rate;
- if (status & SYS_STATUS_PERFORMANCE)
- ddr.performance_rate= rate;
- if ((status & SYS_STATUS_LCDC0)&&(status & SYS_STATUS_LCDC1))
- ddr.dualview_rate = rate;
- if (status & SYS_STATUS_HDMI)
- ddr.hdmi_rate = rate;
- if (status & SYS_STATUS_IDLE)
- ddr.idle_rate= rate;
- if (status & SYS_STATUS_REBOOT)
- ddr.reboot_rate= rate;
- if (status & SYS_STATUS_BOOST)
- ddr.boost_rate= rate;
- if (status & SYS_STATUS_ISP)
- ddr.isp_rate= rate;
-
- nr -= 2;
- }
-
- bd_freq_table = of_get_bd_freq_table(clk_ddr_dev_node, "bd-freq-table");
-
- of_property_read_u32_index(clk_ddr_dev_node, "high_load", 0,
- &high_load);
- of_property_read_u32_index(clk_ddr_dev_node, "low_load", 0, &low_load);
- of_property_read_u32_index(clk_ddr_dev_node, "auto_freq_interval", 0,
- &auto_freq_interval_ms);
- of_property_read_u32_index(clk_ddr_dev_node, "down_rate_delay", 0,
- &down_rate_delay_ms);
-
- return 0;
-}
-
-static int ddrfreq_scale_rate_for_dvfs(struct clk *clk, unsigned long rate)
-{
- unsigned long real_rate;
-
- real_rate = ddr_change_freq(rate/MHZ);
- real_rate *= MHZ;
- if (!real_rate)
- return -EAGAIN;
- if (cpu_is_rk312x()) {
- clk->parent->rate = 2 * real_rate;
- clk->rate = real_rate;
- } else {
- clk->rate = real_rate;
- clk->parent->rate = real_rate;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_RK_PM_TESTS)
-static void ddrfreq_tst_init(void);
-#endif
-
-static int ddrfreq_init(void)
-{
- int ret, i;
- struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 };
-
-#if defined(CONFIG_RK_PM_TESTS)
- ddrfreq_tst_init();
-#endif
-
- clk_cpu_dvfs_node = clk_get_dvfs_node("clk_core");
- memset(&ddr, 0x00, sizeof(ddr));
- ddr.clk_dvfs_node = clk_get_dvfs_node("clk_ddr");
- if (!ddr.clk_dvfs_node){
- return -EINVAL;
- }
- clk_enable_dvfs(ddr.clk_dvfs_node);
-
- dvfs_clk_register_set_rate_callback(ddr.clk_dvfs_node, ddrfreq_scale_rate_for_dvfs);
-
- init_waitqueue_head(&ddr.wait);
- INIT_LIST_HEAD(&ddr.video_info_list);
- ddr.mode = "normal";
- ddr.normal_rate = dvfs_clk_get_rate(ddr.clk_dvfs_node);
- ddr.sys_status = rockchip_get_system_status();
-
- of_init_ddr_freq_table();
-
- if (!ddr.reboot_rate)
- ddr.reboot_rate = ddr.normal_rate;
-
-#ifdef CONFIG_INPUT
- ret = input_register_handler(&ddr_freq_input_handler);
- if (ret)
- ddr.auto_freq = false;
-#endif
-
- //REGISTER_CLK_NOTIFIER(pd_isp);
- //REGISTER_CLK_NOTIFIER(pd_vop0);
- //REGISTER_CLK_NOTIFIER(pd_vop1);
-
- ret = misc_register(&video_state_dev);
- ret = misc_register(&ddr_freq_dev);
- if (unlikely(ret)) {
- pr_err("failed to register video_state misc device! error %d\n", ret);
- goto err;
- }
-
- ddr.task = kthread_create(ddrfreq_task, NULL, "ddrfreqd");
- if (IS_ERR(ddr.task)) {
- ret = PTR_ERR(ddr.task);
- pr_err("failed to create kthread! error %d\n", ret);
- goto err1;
- }
-
- sched_setscheduler_nocheck(ddr.task, SCHED_FIFO, ¶m);
- get_task_struct(ddr.task);
- kthread_bind(ddr.task, 0);
- wake_up_process(ddr.task);
-
- rockchip_register_system_status_notifier(&ddrfreq_system_status_notifier);
- fb_register_client(&ddr_freq_suspend_notifier);
-
- pr_info("verion 1.2 20140526\n");
- pr_info("normal %luMHz video_1080p %luMHz video_4k %luMHz dualview %luMHz idle %luMHz suspend %luMHz reboot %luMHz\n",
- ddr.normal_rate / MHZ,
- ddr.video_1080p_rate / MHZ,
- ddr.video_4k_rate / MHZ,
- ddr.dualview_rate / MHZ,
- ddr.idle_rate / MHZ,
- ddr.suspend_rate / MHZ,
- ddr.reboot_rate / MHZ);
-
- pr_info("auto-freq=%d\n", ddr.auto_freq);
- if (auto_freq_table) {
- for (i = 0; i < auto_freq_table_size; i++) {
- pr_info("auto-freq-table[%d] %luMHz\n", i, auto_freq_table[i] / MHZ);
- }
- } else {
- pr_info("auto-freq-table epmty!\n");
- }
- return 0;
-
-err1:
- misc_deregister(&video_state_dev);
-err:
- return ret;
-}
-late_initcall(ddrfreq_init);
-/****************************ddr bandwith tst************************************/
-#if defined(CONFIG_RK_PM_TESTS)
-static ssize_t ddrbw_dyn_show(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf)
-{
- char *str = buf;
- str += sprintf(str, "print: %d\n", print);
- str += sprintf(str, "watch: %d\n", watch);
- str += sprintf(str, "high_load: %d\n", high_load);
- str += sprintf(str, "low_load: %d\n", low_load);
- str += sprintf(str, "auto_freq_interval_ms: %d\n", auto_freq_interval_ms);
- str += sprintf(str, "down_rate_delay_ms: %d\n", down_rate_delay_ms);
-// str += sprintf(str, "low_load_last_ms: %d\n", low_load_last_ms);
- if (str != buf)
- *(str - 1) = '\n';
- return (str - buf);
-}
-
-static ssize_t ddrbw_dyn_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n)
-{
- int value;
- char var_name[64];
-
- sscanf(buf, "%s %u", var_name, &value);
-
- if((strncmp(buf, "print", strlen("print")) == 0)) {
- print = value;
- } else if((strncmp(buf, "watch", strlen("watch")) == 0)) {
- watch = value;
- } else if((strncmp(buf, "high", strlen("high")) == 0)) {
- high_load = value;
- } else if((strncmp(buf, "low", strlen("low")) == 0)) {
- low_load = value;
- } else if((strncmp(buf, "interval", strlen("interval")) == 0)) {
- auto_freq_interval_ms = value;
- } else if((strncmp(buf, "downdelay", strlen("downdelay")) == 0)) {
- down_rate_delay_ms = value;
- }
- return n;
-}
-
-struct ddrfreq_attribute {
- struct attribute attr;
- ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
- char *buf);
- ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t n);
-};
-
-static struct ddrfreq_attribute ddrfreq_attrs[] = {
- /* node_name permision show_func store_func */
- __ATTR(ddrfreq, S_IRUSR|S_IRGRP|S_IWUSR, ddrbw_dyn_show, ddrbw_dyn_store),
-};
-int rk_pm_tests_kobj_atrradd(const struct attribute *attr);
-
-static void ddrfreq_tst_init(void)
-{
- int ret;
-
- ret = rk_pm_tests_kobj_atrradd(&ddrfreq_attrs[0].attr);
-
- if (ret) {
- printk("%s: create ddrfreq sysfs node error, ret: %d\n", __func__, ret);
- return;
- }
-}
-#endif
+++ /dev/null
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+++ /dev/null
-/*
- * Function Driver for DDR controller
- *
- * Copyright (C) 2011-2014 Fuzhou Rockchip Electronics Co.,Ltd
- * Author:
- * hcy@rock-chips.com
- * yk@rock-chips.com
- *
- * v1.00
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <linux/cpu.h>
-#include <dt-bindings/clock/ddr.h>
-
-#include <linux/rockchip/cru.h>
-
-typedef uint32_t uint32;
-
-/***********************************
- * Global Control Macro
- ***********************************/
-//#define ENABLE_DDR_CLCOK_GPLL_PATH //for RK3188
-
-#define DDR3_DDR2_ODT_DISABLE_FREQ (333)
-#define DDR3_DDR2_DLL_DISABLE_FREQ (333)
-#define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
-#define PD_IDLE (0X40) //unit:DDR clk cycle, and 0 for disable auto power-down
-
-#if (DDR3_DDR2_ODT_DISABLE_FREQ > DDR3_DDR2_DLL_DISABLE_FREQ)
-#error
-#endif
-
-#define ddr_print(x...) printk( "DDR DEBUG: " x )
-
-/***********************************
- * ARCH Relative Macro and Struction
- ***********************************/
-#define PMU_BASE_ADDR RK_PMU_VIRT
-#define SDRAMC_BASE_ADDR RK30_DDR_PCTL_BASE
-#define DDR_PUBL_BASE RK30_DDR_PUBL_BASE
-#define CRU_BASE_ADDR RK_CRU_VIRT
-#define REG_FILE_BASE_ADDR RK_GRF_VIRT
-#define SysSrv_DdrConf (RK_CPU_AXI_BUS_VIRT+0x08)
-#define SysSrv_DdrTiming (RK_CPU_AXI_BUS_VIRT+0x0c)
-#define SysSrv_DdrMode (RK_CPU_AXI_BUS_VIRT+0x10)
-#define SysSrv_ReadLatency (RK_CPU_AXI_BUS_VIRT+0x14)
-
-#define SRAM_CODE_OFFSET rockchip_sram_virt
-#define SRAM_SIZE rockchip_sram_size
-
-/*
- * PMU
- */
-//PMU_MISC_CON1
-#define idle_req_cpu_cfg (1<<1)
-#define idle_req_peri_cfg (1<<2)
-#define idle_req_gpu_cfg (1<<3)
-#define idle_req_video_cfg (1<<4)
-#define idle_req_vio_cfg (1<<5)
-#define idle_req_core_cfg (1<<14)
-#define idle_req_dma_cfg (1<<16)
-
-//PMU_PWRDN_ST
-#define idle_cpu (1<<26)
-#define idle_peri (1<<25)
-#define idle_gpu (1<<24)
-#define idle_video (1<<23)
-#define idle_vio (1<<22)
-#define idle_core (1<<15)
-#define idle_dma (1<<14)
-
-#define pd_a9_0_pwr_st (1<<0)
-#define pd_a9_1_pwr_st (1<<1)
-#define pd_peri_pwr_st (1<<6)
-#define pd_vio_pwr_st (1<<7)
-#define pd_video_pwr_st (1<<8)
-#define pd_gpu_pwr_st (1<<9)
-
-struct ddr_freq_t {
- unsigned long screen_ft_us;
- unsigned long long t0;
- unsigned long long t1;
- unsigned long t2;
-};
-
-//PMU registers
-typedef volatile struct tagPMU_FILE
-{
- uint32 PMU_WAKEUP_CFG[2];
- uint32 PMU_PWRDN_CON;
- uint32 PMU_PWRDN_ST;
- uint32 PMU_INT_CON;
- uint32 PMU_INT_ST;
- uint32 PMU_MISC_CON;
- uint32 PMU_OSC_CNT;
- uint32 PMU_PLL_CNT;
- uint32 PMU_PMU_CNT;
- uint32 PMU_DDRIO_PWRON_CNT;
- uint32 PMU_WAKEUP_RST_CLR_CNT;
- uint32 PMU_SCU_PWRDWN_CNT;
- uint32 PMU_SCU_PWRUP_CNT;
- uint32 PMU_MISC_CON1;
- uint32 PMU_GPIO6_CON;
- uint32 PMU_PMU_SYS_REG[4];
-} PMU_FILE, *pPMU_FILE;
-
-//PMU_NOC_REQ
-#define idle_req_bp2ap_rk319x (1<<8)
-#define idle_req_dma_cfg_rk319x (1<<7)
-#define idle_req_vio_cfg_rk319x (1<<4)
-#define idle_req_video_cfg_rk319x (1<<3)
-#define idle_req_gpu_cfg_rk319x (1<<2)
-#define idle_req_peri_cfg_rk319x (1<<1)
-
-//PMU_NOC_ST
-#define idle_bp2ap_rk319x (1<<8)
-#define idle_dma_rk319x (1<<7)
-#define idle_vio_rk319x (1<<4)
-#define idle_video_rk319x (1<<3)
-#define idle_gpu_rk319x (1<<2)
-#define idle_peri_rk319x (1<<1)
-
-//PMU_PWRDN_ST
-#define pd_peri_pwr_st_rk319x (1<<10)
-#define pd_vio_pwr_st_rk319x (1<<9)
-#define pd_video_pwr_st_rk319x (1<<8)
-#define pd_gpu_pwr_st_rk319x (1<<7)
-#define pd_a9_1_pwr_st_rk319x (1<<1)
-#define pd_a9_0_pwr_st_rk319x (1<<0)
-
-//PMU registers
-typedef volatile struct tagPMU_FILE_RK319X
-{
- uint32 PMU_WAKEUP_CFG[3];
- uint32 PMU_PWRDN_CON;
- uint32 PMU_PWRDN_ST;
- uint32 PMU_PWRMODE_CON;
- uint32 PMU_SFT_CON;
- uint32 PMU_INT_CON;
- uint32 PMU_INT_ST;
- uint32 PMU_GPIO_INT_ST;
- uint32 PMU_GPIO_2EDGE_INT_ST;
- uint32 PMU_NOC_REQ;
- uint32 PMU_NOC_ST;
- uint32 PMU_POWER_ST;
- uint32 reserved1[3];
- uint32 PMU_OSC_CNT;
- uint32 PMU_PLLLOCK_CNT;
- uint32 PMU_PLLRST_CNT;
- uint32 PMU_STABLE_CNT;
- uint32 PMU_DDRIO_PWRON_CNT;
- uint32 reserved2[2];
- uint32 PMU_WAKEUP_RST_CLR_CNT;
- uint32 reserved3;
- uint32 PMU_DDR_SREF_ST;
- uint32 reserved4[2];
- uint32 PMU_PMU_SYS_REG[4];
-} PMU_FILE_RK319X, *pPMU_FILE_RK319X;
-
-/*
- * CRU
- */
-typedef enum PLL_ID_Tag
-{
- APLL=0,
- DPLL,
- CPLL,
- GPLL,
- PLL_MAX
-}PLL_ID;
-
-#define PLL_RESET (((0x1<<5)<<16) | (0x1<<5))
-#define PLL_DE_RESET (((0x1<<5)<<16) | (0x0<<5))
-#define NR(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
-#define NO(n) ((0xF<<16) | ((n)-1))
-#define NF(n) ((0x1FFF<<16) | ((n)-1))
-#define NB(n) ((0xFFF<<16) | ((n)-1))
-
-//RK3066B
-#define PLL_RESET_RK3066B (((0x1<<1)<<16) | (0x1<<1))
-#define PLL_DE_RESET_RK3066B (((0x1<<1)<<16) | (0x0<<1))
-#define NR_RK3066B(n) ((0x3F<<(8+16)) | (((n)-1)<<8))
-#define NO_RK3066B(n) ((0x3F<<16) | ((n)-1))
-#define NF_RK3066B(n) ((0xFFFF<<16) | ((n)-1))
-
- //CRU Registers
-typedef volatile struct tagCRU_STRUCT
-{
- uint32 CRU_PLL_CON[4][4];
- uint32 CRU_MODE_CON;
- uint32 CRU_CLKSEL_CON[35];
- uint32 CRU_CLKGATE_CON[10];
- uint32 reserved1[2];
- uint32 CRU_GLB_SRST_FST_VALUE;
- uint32 CRU_GLB_SRST_SND_VALUE;
- uint32 reserved2[2];
- uint32 CRU_SOFTRST_CON[9];
- uint32 CRU_MISC_CON;
- uint32 reserved3[2];
- uint32 CRU_GLB_CNT_TH;
-} CRU_REG, *pCRU_REG;
-
-typedef volatile struct tagCRU_STRUCT_RK319X
-{
- uint32 CRU_PLL_CON[4][4];
- uint32 CRU_MODE_CON;
- uint32 CRU_CLKSEL_CON[35];
- uint32 CRU_CLKGATE_CON[16];
- uint32 CRU_SOFTRST_CON[12];
- uint32 CRU_GLB_CNT_TH;
- uint32 CRU_MISC_CON;
- uint32 CRU_TSADC_CON;
- uint32 reserved1[(0x160-0x14c)/4];
- uint32 CRU_GLB_SRST_FST_VALUE;
- uint32 CRU_GLB_SRST_SND_VALUE;
- uint32 CRU_GLB_BB_SRST_FST_VALUE;
- uint32 CRU_GLB_BB_SRST_SND_VALUE;
-} CRU_REG_RK319X, *pCRU_REG_RK319X;
-
-/*
- * GRF
- */
-typedef struct tagGPIO_LH
-{
- uint32 GPIOL;
- uint32 GPIOH;
-}GPIO_LH_T;
-
-typedef struct tagGPIO_IOMUX
-{
- uint32 GPIOA_IOMUX;
- uint32 GPIOB_IOMUX;
- uint32 GPIOC_IOMUX;
- uint32 GPIOD_IOMUX;
-}GPIO_IOMUX_T;
-
-//REG FILE registers
-typedef volatile struct tagREG_FILE
-{
- GPIO_LH_T GRF_GPIO_DIR[7];
- GPIO_LH_T GRF_GPIO_DO[7];
- GPIO_LH_T GRF_GPIO_EN[7];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[7];
- GPIO_LH_T GRF_GPIO_PULL[7];
- uint32 GRF_SOC_CON[3];
- uint32 GRF_SOC_STATUS0;
- uint32 GRF_DMAC1_CON[3];
- uint32 GRF_DMAC2_CON[4];
- uint32 GRF_UOC0_CON[3];
- uint32 GRF_UOC1_CON[4];
- uint32 GRF_DDRC_CON0;
- uint32 GRF_DDRC_STAT;
- uint32 reserved[(0x1c8-0x1a0)/4];
- uint32 GRF_OS_REG[4];
-} REG_FILE, *pREG_FILE;
-
-//REG FILE registers
-typedef volatile struct tagREG_FILE_RK3066B
-{
- GPIO_LH_T GRF_GPIO_DIR[4];
- GPIO_LH_T GRF_GPIO_DO[4];
- GPIO_LH_T GRF_GPIO_EN[4];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[4];
- uint32 GRF_SOC_CON[3];
- uint32 GRF_SOC_STATUS0;
- uint32 GRF_DMAC0_CON[3];
- uint32 GRF_DMAC1_CON[4];
- uint32 reserved0[(0xec-0xcc)/4];
- uint32 GRF_DDRC_CON0;
- uint32 GRF_DDRC_STAT;
- uint32 GRF_IO_CON[5];
- uint32 reserved1;
- uint32 GRF_UOC0_CON[4];
- uint32 GRF_UOC1_CON[4];
- uint32 GRF_UOC2_CON[2];
- uint32 reserved2;
- uint32 GRF_UOC3_CON[2];
- uint32 GRF_EHCI_STAT;
- uint32 GRF_OS_REG[8];
-} REG_FILE_RK3066B, *pREG_FILE_RK3066B;
-
-typedef struct tagGPIO
-{
- uint32 GPIOA;
- uint32 GPIOB;
- uint32 GPIOC;
- uint32 GPIOD;
-}GPIO_T;
-
-//REG FILE registers
-typedef volatile struct tagREG_FILE_RK319X
-{
- GPIO_T GRF_GPIO_IOMUX[5]; // 0x0010
- GPIO_T reserved1;
- uint32 GRF_SOC_CON[5]; // 0x0060
- uint32 GRF_SOC_STATUS0;
- uint32 GRF_SOC_STATUS1;
- uint32 GRF_SOC_STATUS2;
- uint32 GRF_DMAC1_CON[3];
- uint32 GRF_DMAC2_CON[4];
- uint32 GRF_CPU_CON[6];
- uint32 GRF_CPU_STATUS[2];
- uint32 GRF_DDRC_CON0;
- uint32 GRF_DDRC_STAT;
- uint32 GRF_UOC0_CON[4];
- uint32 GRF_U0C1_CON[4];
- uint32 GRF_UOC2_CON[2];
- uint32 GRF_UOC3_CON[2];
- uint32 GRF_PVTM_CON[3];
- uint32 GRF_PVTM_STATUS[3];
- uint32 reserved2;
- uint32 GRF_NIF_FIFO[4];
- uint32 GRF_OS_REG[4];
- uint32 GRF_SOC_CON5_8[4];
- uint32 reserved3;
- GPIO_T GRF_GPIO_PULL_1_4[4];
- uint32 reserved4[2];
- uint32 GRF_IO_VSEL;
- uint32 reserved5[2];
- uint32 GRF_GPIO1L_SR;
- uint32 GRF_GPIO1H_SR;
- uint32 GRF_GPIO2L_SR;
- uint32 GRF_GPIO2H_SR;
- uint32 GRF_GPIO3L_SR;
- uint32 GRF_GPIO3H_SR;
- uint32 GRF_GPIO4L_SR;
- uint32 GRF_GPIO4H_SR;
- GPIO_T GRF_GPIO_E[5];
- uint32 reserved6[2];
- uint32 GRF_FLASH_DATA_PULL;
- uint32 GRF_FLASH_DATA_E;
- uint32 GRF_FLASH_DATA_SR;
- uint32 reserved7;
- uint32 GRF_USBPHY_CON[12];
- uint32 GRF_DFI_STAT[4];
- uint32 reserved8[(0x300-0x260)/4];
- uint32 GRF_SECURE_BOOT_STATUS;
-} REG_FILE_RK319X, *pREG_FILE_RK319X;
-
-/*
- * PCTL
- */
-//SCTL
-#define INIT_STATE (0)
-#define CFG_STATE (1)
-#define GO_STATE (2)
-#define SLEEP_STATE (3)
-#define WAKEUP_STATE (4)
-
-//STAT
-#define Init_mem (0)
-#define Config (1)
-#define Config_req (2)
-#define Access (3)
-#define Access_req (4)
-#define Low_power (5)
-#define Low_power_entry_req (6)
-#define Low_power_exit_req (7)
-
-//MCFG
-#define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
-#define pd_idle(n) ((n)<<8)
-#define mddr_en (2<<22)
-#define lpddr2_en (3<<22)
-#define ddr2_en (0<<5)
-#define ddr3_en (1<<5)
-#define lpddr2_s2 (0<<6)
-#define lpddr2_s4 (1<<6)
-#define mddr_lpddr2_bl_2 (0<<20)
-#define mddr_lpddr2_bl_4 (1<<20)
-#define mddr_lpddr2_bl_8 (2<<20)
-#define mddr_lpddr2_bl_16 (3<<20)
-#define ddr2_ddr3_bl_4 (0)
-#define ddr2_ddr3_bl_8 (1)
-#define tfaw_cfg(n) (((n)-4)<<18)
-#define pd_exit_slow (0<<17)
-#define pd_exit_fast (1<<17)
-#define pd_type(n) ((n)<<16)
-#define two_t_en(n) ((n)<<3)
-#define bl8int_en(n) ((n)<<2)
-#define cke_or_en(n) ((n)<<1)
-
-//POWCTL
-#define power_up_start (1<<0)
-
-//POWSTAT
-#define power_up_done (1<<0)
-
-//DFISTSTAT0
-#define dfi_init_complete (1<<0)
-
-//CMDTSTAT
-#define cmd_tstat (1<<0)
-
-//CMDTSTATEN
-#define cmd_tstat_en (1<<1)
-
-//MCMD
-#define Deselect_cmd (0)
-#define PREA_cmd (1)
-#define REF_cmd (2)
-#define MRS_cmd (3)
-#define ZQCS_cmd (4)
-#define ZQCL_cmd (5)
-#define RSTL_cmd (6)
-#define MRR_cmd (8)
-#define DPDE_cmd (9)
-
-#define lpddr2_op(n) ((n)<<12)
-#define lpddr2_ma(n) ((n)<<4)
-
-#define bank_addr(n) ((n)<<17)
-#define cmd_addr(n) ((n)<<4)
-
-#define start_cmd (1u<<31)
-
-typedef union STAT_Tag
-{
- uint32 d32;
- struct
- {
- unsigned ctl_stat : 3;
- unsigned reserved3 : 1;
- unsigned lp_trig : 3;
- unsigned reserved7_31 : 25;
- }b;
-}STAT_T;
-
-typedef union SCFG_Tag
-{
- uint32 d32;
- struct
- {
- unsigned hw_low_power_en : 1;
- unsigned reserved1_5 : 5;
- unsigned nfifo_nif1_dis : 1;
- unsigned reserved7 : 1;
- unsigned bbflags_timing : 4;
- unsigned reserved12_31 : 20;
- } b;
-}SCFG_T;
-
-/* DDR Controller register struct */
-typedef volatile struct DDR_REG_Tag
-{
- //Operational State, Control, and Status Registers
- SCFG_T SCFG; //State Configuration Register
- volatile uint32 SCTL; //State Control Register
- STAT_T STAT; //State Status Register
- volatile uint32 INTRSTAT; //Interrupt Status Register
- uint32 reserved0[(0x40-0x10)/4];
- //Initailization Control and Status Registers
- volatile uint32 MCMD; //Memory Command Register
- volatile uint32 POWCTL; //Power Up Control Registers
- volatile uint32 POWSTAT; //Power Up Status Register
- volatile uint32 CMDTSTAT; //Command Timing Status Register
- volatile uint32 CMDTSTATEN; //Command Timing Status Enable Register
- uint32 reserved1[(0x60-0x54)/4];
- volatile uint32 MRRCFG0; //MRR Configuration 0 Register
- volatile uint32 MRRSTAT0; //MRR Status 0 Register
- volatile uint32 MRRSTAT1; //MRR Status 1 Register
- uint32 reserved2[(0x7c-0x6c)/4];
- //Memory Control and Status Registers
- volatile uint32 MCFG1; //Memory Configuration 1 Register
- volatile uint32 MCFG; //Memory Configuration Register
- volatile uint32 PPCFG; //Partially Populated Memories Configuration Register
- volatile uint32 MSTAT; //Memory Status Register
- volatile uint32 LPDDR2ZQCFG; //LPDDR2 ZQ Configuration Register
- uint32 reserved3;
- //DTU Control and Status Registers
- volatile uint32 DTUPDES; //DTU Status Register
- volatile uint32 DTUNA; //DTU Number of Random Addresses Created Register
- volatile uint32 DTUNE; //DTU Number of Errors Register
- volatile uint32 DTUPRD0; //DTU Parallel Read 0
- volatile uint32 DTUPRD1; //DTU Parallel Read 1
- volatile uint32 DTUPRD2; //DTU Parallel Read 2
- volatile uint32 DTUPRD3; //DTU Parallel Read 3
- volatile uint32 DTUAWDT; //DTU Address Width
- uint32 reserved4[(0xc0-0xb4)/4];
- //Memory Timing Registers
- volatile uint32 TOGCNT1U; //Toggle Counter 1U Register
- volatile uint32 TINIT; //t_init Timing Register
- volatile uint32 TRSTH; //Reset High Time Register
- volatile uint32 TOGCNT100N; //Toggle Counter 100N Register
- volatile uint32 TREFI; //t_refi Timing Register
- volatile uint32 TMRD; //t_mrd Timing Register
- volatile uint32 TRFC; //t_rfc Timing Register
- volatile uint32 TRP; //t_rp Timing Register
- volatile uint32 TRTW; //t_rtw Timing Register
- volatile uint32 TAL; //AL Latency Register
- volatile uint32 TCL; //CL Timing Register
- volatile uint32 TCWL; //CWL Register
- volatile uint32 TRAS; //t_ras Timing Register
- volatile uint32 TRC; //t_rc Timing Register
- volatile uint32 TRCD; //t_rcd Timing Register
- volatile uint32 TRRD; //t_rrd Timing Register
- volatile uint32 TRTP; //t_rtp Timing Register
- volatile uint32 TWR; //t_wr Timing Register
- volatile uint32 TWTR; //t_wtr Timing Register
- volatile uint32 TEXSR; //t_exsr Timing Register
- volatile uint32 TXP; //t_xp Timing Register
- volatile uint32 TXPDLL; //t_xpdll Timing Register
- volatile uint32 TZQCS; //t_zqcs Timing Register
- volatile uint32 TZQCSI; //t_zqcsi Timing Register
- volatile uint32 TDQS; //t_dqs Timing Register
- volatile uint32 TCKSRE; //t_cksre Timing Register
- volatile uint32 TCKSRX; //t_cksrx Timing Register
- volatile uint32 TCKE; //t_cke Timing Register
- volatile uint32 TMOD; //t_mod Timing Register
- volatile uint32 TRSTL; //Reset Low Timing Register
- volatile uint32 TZQCL; //t_zqcl Timing Register
- volatile uint32 TMRR; //t_mrr Timing Register
- volatile uint32 TCKESR; //t_ckesr Timing Register
- volatile uint32 TDPD; //t_dpd Timing Register
- uint32 reserved5[(0x180-0x148)/4];
- //ECC Configuration, Control, and Status Registers
- volatile uint32 ECCCFG; //ECC Configuration Register
- volatile uint32 ECCTST; //ECC Test Register
- volatile uint32 ECCCLR; //ECC Clear Register
- volatile uint32 ECCLOG; //ECC Log Register
- uint32 reserved6[(0x200-0x190)/4];
- //DTU Control and Status Registers
- volatile uint32 DTUWACTL; //DTU Write Address Control Register
- volatile uint32 DTURACTL; //DTU Read Address Control Register
- volatile uint32 DTUCFG; //DTU Configuration Control Register
- volatile uint32 DTUECTL; //DTU Execute Control Register
- volatile uint32 DTUWD0; //DTU Write Data 0
- volatile uint32 DTUWD1; //DTU Write Data 1
- volatile uint32 DTUWD2; //DTU Write Data 2
- volatile uint32 DTUWD3; //DTU Write Data 3
- volatile uint32 DTUWDM; //DTU Write Data Mask
- volatile uint32 DTURD0; //DTU Read Data 0
- volatile uint32 DTURD1; //DTU Read Data 1
- volatile uint32 DTURD2; //DTU Read Data 2
- volatile uint32 DTURD3; //DTU Read Data 3
- volatile uint32 DTULFSRWD; //DTU LFSR Seed for Write Data Generation
- volatile uint32 DTULFSRRD; //DTU LFSR Seed for Read Data Generation
- volatile uint32 DTUEAF; //DTU Error Address FIFO
- //DFI Control Registers
- volatile uint32 DFITCTRLDELAY; //DFI tctrl_delay Register
- volatile uint32 DFIODTCFG; //DFI ODT Configuration Register
- volatile uint32 DFIODTCFG1; //DFI ODT Configuration 1 Register
- volatile uint32 DFIODTRANKMAP; //DFI ODT Rank Mapping Register
- //DFI Write Data Registers
- volatile uint32 DFITPHYWRDATA; //DFI tphy_wrdata Register
- volatile uint32 DFITPHYWRLAT; //DFI tphy_wrlat Register
- uint32 reserved7[(0x260-0x258)/4];
- volatile uint32 DFITRDDATAEN; //DFI trddata_en Register
- volatile uint32 DFITPHYRDLAT; //DFI tphy_rddata Register
- uint32 reserved8[(0x270-0x268)/4];
- //DFI Update Registers
- volatile uint32 DFITPHYUPDTYPE0; //DFI tphyupd_type0 Register
- volatile uint32 DFITPHYUPDTYPE1; //DFI tphyupd_type1 Register
- volatile uint32 DFITPHYUPDTYPE2; //DFI tphyupd_type2 Register
- volatile uint32 DFITPHYUPDTYPE3; //DFI tphyupd_type3 Register
- volatile uint32 DFITCTRLUPDMIN; //DFI tctrlupd_min Register
- volatile uint32 DFITCTRLUPDMAX; //DFI tctrlupd_max Register
- volatile uint32 DFITCTRLUPDDLY; //DFI tctrlupd_dly Register
- uint32 reserved9;
- volatile uint32 DFIUPDCFG; //DFI Update Configuration Register
- volatile uint32 DFITREFMSKI; //DFI Masked Refresh Interval Register
- volatile uint32 DFITCTRLUPDI; //DFI tctrlupd_interval Register
- uint32 reserved10[(0x2ac-0x29c)/4];
- volatile uint32 DFITRCFG0; //DFI Training Configuration 0 Register
- volatile uint32 DFITRSTAT0; //DFI Training Status 0 Register
- volatile uint32 DFITRWRLVLEN; //DFI Training dfi_wrlvl_en Register
- volatile uint32 DFITRRDLVLEN; //DFI Training dfi_rdlvl_en Register
- volatile uint32 DFITRRDLVLGATEEN; //DFI Training dfi_rdlvl_gate_en Register
- //DFI Status Registers
- volatile uint32 DFISTSTAT0; //DFI Status Status 0 Register
- volatile uint32 DFISTCFG0; //DFI Status Configuration 0 Register
- volatile uint32 DFISTCFG1; //DFI Status configuration 1 Register
- uint32 reserved11;
- volatile uint32 DFITDRAMCLKEN; //DFI tdram_clk_enalbe Register
- volatile uint32 DFITDRAMCLKDIS; //DFI tdram_clk_disalbe Register
- volatile uint32 DFISTCFG2; //DFI Status configuration 2 Register
- volatile uint32 DFISTPARCLR; //DFI Status Parity Clear Register
- volatile uint32 DFISTPARLOG; //DFI Status Parity Log Register
- uint32 reserved12[(0x2f0-0x2e4)/4];
- //DFI Low Power Registers
- volatile uint32 DFILPCFG0; //DFI Low Power Configuration 0 Register
- uint32 reserved13[(0x300-0x2f4)/4];
- //DFI Training 2 Registers
- volatile uint32 DFITRWRLVLRESP0; //DFI Training dif_wrlvl_resp Status 0 Register
- volatile uint32 DFITRWRLVLRESP1; //DFI Training dif_wrlvl_resp Status 1 Register
- volatile uint32 DFITRWRLVLRESP2; //DFI Training dif_wrlvl_resp Status 2 Register
- volatile uint32 DFITRRDLVLRESP0; //DFI Training dif_rdlvl_resp Status 0 Register
- volatile uint32 DFITRRDLVLRESP1; //DFI Training dif_rdlvl_resp Status 1 Register
- volatile uint32 DFITRRDLVLRESP2; //DFI Training dif_rdlvl_resp Status 2 Register
- volatile uint32 DFITRWRLVLDELAY0; //DFI Training dif_wrlvl_delay Configuration 0 Register
- volatile uint32 DFITRWRLVLDELAY1; //DFI Training dif_wrlvl_delay Configuration 1 Register
- volatile uint32 DFITRWRLVLDELAY2; //DFI Training dif_wrlvl_delay Configuration 2 Register
- volatile uint32 DFITRRDLVLDELAY0; //DFI Training dif_rdlvl_delay Configuration 0 Register
- volatile uint32 DFITRRDLVLDELAY1; //DFI Training dif_rdlvl_delay Configuration 1 Register
- volatile uint32 DFITRRDLVLDELAY2; //DFI Training dif_rdlvl_delay Configuration 2 Register
- volatile uint32 DFITRRDLVLGATEDELAY0; //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
- volatile uint32 DFITRRDLVLGATEDELAY1; //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
- volatile uint32 DFITRRDLVLGATEDELAY2; //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
- volatile uint32 DFITRCMD; //DFI Training Command Register
- uint32 reserved14[(0x3f8-0x340)/4];
- //IP Status Registers
- volatile uint32 IPVR; //IP Version Register
- volatile uint32 IPTR; //IP Type Register
-}DDR_REG_T, *pDDR_REG_T;
-
-#define pDDR_Reg ((pDDR_REG_T)SDRAMC_BASE_ADDR)
-
-/*
- * PUBL
- */
-//PIR
-#define INIT (1<<0)
-#define DLLSRST (1<<1)
-#define DLLLOCK (1<<2)
-#define ZCAL (1<<3)
-#define ITMSRST (1<<4)
-#define DRAMRST (1<<5)
-#define DRAMINIT (1<<6)
-#define QSTRN (1<<7)
-#define EYETRN (1<<8)
-#define ICPC (1<<16)
-#define DLLBYP (1<<17)
-#define CTLDINIT (1<<18)
-#define CLRSR (1<<28)
-#define LOCKBYP (1<<29)
-#define ZCALBYP (1<<30)
-#define INITBYP (1u<<31)
-
-//PGCR
-#define DFTLMT(n) ((n)<<3)
-#define DFTCMP(n) ((n)<<2)
-#define DQSCFG(n) ((n)<<1)
-#define ITMDMD(n) ((n)<<0)
-#define RANKEN(n) ((n)<<18)
-
-//PGSR
-#define IDONE (1<<0)
-#define DLDONE (1<<1)
-#define ZCDONE (1<<2)
-#define DIDONE (1<<3)
-#define DTDONE (1<<4)
-#define DTERR (1<<5)
-#define DTIERR (1<<6)
-#define DFTERR (1<<7)
-#define TQ (1u<<31)
-
-//PTR0
-#define tITMSRST(n) ((n)<<18)
-#define tDLLLOCK(n) ((n)<<6)
-#define tDLLSRST(n) ((n)<<0)
-
-//PTR1
-#define tDINIT1(n) ((n)<<19)
-#define tDINIT0(n) ((n)<<0)
-
-//PTR2
-#define tDINIT3(n) ((n)<<17)
-#define tDINIT2(n) ((n)<<0)
-
-//DSGCR
-#define DQSGE(n) ((n)<<8)
-#define DQSGX(n) ((n)<<5)
-
-typedef union DCR_Tag
-{
- uint32 d32;
- struct
- {
- unsigned DDRMD : 3;
- unsigned DDR8BNK : 1;
- unsigned PDQ : 3;
- unsigned MPRDQ : 1;
- unsigned DDRTYPE : 2;
- unsigned reserved10_26 : 17;
- unsigned NOSRA : 1;
- unsigned DDR2T : 1;
- unsigned UDIMM : 1;
- unsigned RDIMM : 1;
- unsigned TPD : 1;
- } b;
-}DCR_T;
-
-typedef volatile struct DATX8_REG_Tag
-{
- volatile uint32 DXGCR; //DATX8 General Configuration Register
- volatile uint32 DXGSR[2]; //DATX8 General Status Register
- volatile uint32 DXDLLCR; //DATX8 DLL Control Register
- volatile uint32 DXDQTR; //DATX8 DQ Timing Register
- volatile uint32 DXDQSTR; //DATX8 DQS Timing Register
- uint32 reserved[0x80-0x76];
-}DATX8_REG_T;
-
-/* DDR PHY register struct */
-typedef volatile struct DDRPHY_REG_Tag
-{
- volatile uint32 RIDR; //Revision Identification Register
- volatile uint32 PIR; //PHY Initialization Register
- volatile uint32 PGCR; //PHY General Configuration Register
- volatile uint32 PGSR; //PHY General Status Register
- volatile uint32 DLLGCR; //DLL General Control Register
- volatile uint32 ACDLLCR; //AC DLL Control Register
- volatile uint32 PTR[3]; //PHY Timing Registers 0-2
- volatile uint32 ACIOCR; //AC I/O Configuration Register
- volatile uint32 DXCCR; //DATX8 Common Configuration Register
- volatile uint32 DSGCR; //DDR System General Configuration Register
- DCR_T DCR; //DRAM Configuration Register
- volatile uint32 DTPR[3]; //DRAM Timing Parameters Register 0-2
- volatile uint32 MR[4]; //Mode Register 0-3
- volatile uint32 ODTCR; //ODT Configuration Register
- volatile uint32 DTAR; //Data Training Address Register
- volatile uint32 DTDR[2]; //Data Training Data Register 0-1
-
- uint32 reserved1[0x30-0x18];
- uint32 DCU[0x38-0x30];
- uint32 reserved2[0x40-0x38];
- uint32 BIST[0x51-0x40];
- uint32 reserved3[0x60-0x51];
-
- volatile uint32 ZQ0CR[2]; //ZQ 0 Impedance Control Register 0-1
- volatile uint32 ZQ0SR[2]; //ZQ 0 Impedance Status Register 0-1
- volatile uint32 ZQ1CR[2]; //ZQ 1 Impedance Control Register 0-1
- volatile uint32 ZQ1SR[2]; //ZQ 1 Impedance Status Register 0-1
- volatile uint32 ZQ2CR[2]; //ZQ 2 Impedance Control Register 0-1
- volatile uint32 ZQ2SR[2]; //ZQ 2 Impedance Status Register 0-1
- volatile uint32 ZQ3CR[2]; //ZQ 3 Impedance Control Register 0-1
- volatile uint32 ZQ3SR[2]; //ZQ 3 Impedance Status Register 0-1
-
- DATX8_REG_T DATX8[9]; //DATX8 Register
-}DDRPHY_REG_T, *pDDRPHY_REG_T;
-
-#define pPHY_Reg ((pDDRPHY_REG_T)DDR_PUBL_BASE)
-
-#if defined(CONFIG_ARCH_RK30) && (!defined(CONFIG_ARCH_RK3066B))
-#define pPMU_Reg ((pPMU_FILE)PMU_BASE_ADDR)
-#define pCRU_Reg ((pCRU_REG)CRU_BASE_ADDR)
-#define pGRF_Reg ((pREG_FILE)REG_FILE_BASE_ADDR)
-#define GET_DDR3_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0xb<<5) | 0xb)
-#define GET_LPDDR2_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x8<<5) | 0x8)
-#define GET_3188_PLUS_STATUS() (false)
-#define GET_DPLL_STATUS() (true)
-#define DDR_GET_RANK_2_ROW15() (pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
-#define DDR_GET_BANK_2_RANK() (pGRF_Reg->GRF_SOC_CON[2] & (1<<2))
-#define DDR_HW_WAKEUP(en) do{pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | en);}while(0)
-#define READ_GRF_REG() (pGRF_Reg->GRF_SOC_CON[2])
-#define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS0 & (1<<4))
-#define SET_DDR_PLL_SRC(src, div) do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<8))<<16)|(src<<8)| div;}while(0)
-#define GET_DDR_PLL_SRC() (DPLL)
-#define SET_DDRPHY_CLKGATE(dis) do{pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (dis<<2);}while(0)
-#elif defined(CONFIG_ARCH_RK30) && defined(CONFIG_ARCH_RK3066B)
-#define pPMU_Reg ((pPMU_FILE)PMU_BASE_ADDR)
-#define pCRU_Reg ((pCRU_REG)CRU_BASE_ADDR)
-#define pGRF_Reg ((pREG_FILE_RK3066B)REG_FILE_BASE_ADDR)
-#define GET_DDR3_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
-#define GET_LPDDR2_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
-#define GET_3188_PLUS_STATUS() (false)
-#define GET_DPLL_STATUS() (true)
-#define DDR_GET_RANK_2_ROW15() (pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
-#define DDR_GET_BANK_2_RANK() (pGRF_Reg->GRF_SOC_CON[2] & (1<<2))
-#define DDR_HW_WAKEUP(en) do{pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | en);}while(0)
-#define READ_GRF_REG() (pGRF_Reg->GRF_SOC_CON[2])
-#define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS0 & (1<<5))
-#define SET_DDR_PLL_SRC(src, div) do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<8))<<16)|(src<<8)| div;}while(0)
-#define GET_DDR_PLL_SRC() (DPLL)
-#define DDR_GPLL_CLK_GATE(en) do{pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000 | (en<<7);}while(0)
-#define SET_DDRPHY_CLKGATE(dis) do{pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (dis<<2);}while(0)
-#elif defined(CONFIG_ARCH_RK3188)
-#define pPMU_Reg ((pPMU_FILE)PMU_BASE_ADDR)
-#define pCRU_Reg ((pCRU_REG)CRU_BASE_ADDR)
-#define pGRF_Reg ((pREG_FILE_RK3066B)REG_FILE_BASE_ADDR)
-#define GET_DDR3_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
-#define GET_LPDDR2_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
-#define GET_3188_PLUS_STATUS() (soc_is_rk3188plus())
-#define GET_DPLL_STATUS() ((rk_pll_flag() & 0x3) ? false : true)
-#define DDR_GET_RANK_2_ROW15() (pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
-#define DDR_GET_BANK_2_RANK() (pGRF_Reg->GRF_SOC_CON[2] & (1<<2))
-#define DDR_HW_WAKEUP(en) do{pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | en);}while(0)
-#define READ_GRF_REG() (pGRF_Reg->GRF_SOC_CON[2])
-#define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS0 & (1<<5))
-#define SET_DDR_PLL_SRC(src, div) do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<8))<<16)|(src<<8)| div;}while(0)
-#define GET_DDR_PLL_SRC() ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<8)) ? GPLL : DPLL)
-#define DDR_GPLL_CLK_GATE(en) do{pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000 | (en<<7);}while(0)
-#define SET_DDRPHY_CLKGATE(dis) do{pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (dis<<2);}while(0)
-#elif defined(CONFIG_ARCH_RK319X)
-#define pPMU_Reg ((pPMU_FILE_RK319X)PMU_BASE_ADDR)
-#define pCRU_Reg ((pCRU_REG_RK319X)CRU_BASE_ADDR)
-#define pGRF_Reg ((pREG_FILE_RK319X)REG_FILE_BASE_ADDR)
-#define GET_DDR3_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
-#define GET_LPDDR2_DS_ODT() ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
-#define GET_3188_PLUS_STATUS() (true)
-#define GET_DPLL_STATUS() (true)
-#define DDR_GET_RANK_2_ROW15() (pGRF_Reg->GRF_SOC_CON[0] & (1<<9))
-#define DDR_GET_BANK_2_RANK() (pGRF_Reg->GRF_SOC_CON[0] & (1<<10))
-#define DDR_HW_WAKEUP(en) do{pGRF_Reg->GRF_SOC_CON[0] = (1<<(16+8)) | (en<<8);}while(0)
-#define READ_GRF_REG() (pGRF_Reg->GRF_SOC_CON[0])
-#define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS0 & (1<<5))
-#define SET_DDR_PLL_SRC(src, div) do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<2))<<16)|(src<<2)| div;}while(0)
-#define GET_DDR_PLL_SRC() ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<2)) ? GPLL : DPLL)
-#define DDR_GPLL_CLK_GATE(en) do{pCRU_Reg->CRU_CLKGATE_CON[0] = 0x02000000 | (en<<9);}while(0)
-#define SET_DDRPHY_CLKGATE(dis) do{pCRU_Reg->CRU_CLKGATE_CON[10] = ((0x1<<12)<<16) | (dis<<12);}while(0)
-#else
-#arch defined error!!
-#endif
-#define SET_PLL_MODE(pll, mode) do{pCRU_Reg->CRU_MODE_CON = ((mode<<((pll)*4))|(0x3<<(16+(pll)*4)));}while(0)
-#define SET_PLL_PD(pll, pd) do{pCRU_Reg->CRU_PLL_CON[pll][3] = ((0x1<<1)<<16) | (pd<<1);}while(0)
-
-#define DDR_SYS_REG() (pPMU_Reg->PMU_PMU_SYS_REG[2])
-#define READ_CS_INFO() ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>11)&0x1)+1)
-#define READ_BW_INFO() (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>2)&0x3))
-#define READ_COL_INFO() (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>9)&0x3))
-#define READ_BK_INFO() (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>8)&0x1))
-#define READ_CS0_ROW_INFO() (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>6)&0x3))
-#define READ_CS1_ROW_INFO() (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>4)&0x3))
-#define READ_DIE_BW_INFO() (2>>(pPMU_Reg->PMU_PMU_SYS_REG[2]&0x3))
-
-static const uint8_t ddr_cfg_2_rbc[] =
-{
- /****************************/
- // [7:6] bank(n:n bit bank)
- // [5:4] row(13+n)
- // [3:2] bank(n:n bit bank)
- // [1:0] col(9+n)
- /****************************/
- //bank, row, bank, col
- ((3<<6)|(2<<4)|(0<<2)|2), // 0 bank ahead
- ((0<<6)|(2<<4)|(3<<2)|1), // 1
- ((0<<6)|(1<<4)|(3<<2)|1), // 2
- ((0<<6)|(0<<4)|(3<<2)|1), // 3
- ((0<<6)|(2<<4)|(3<<2)|2), // 4
- ((0<<6)|(1<<4)|(3<<2)|2), // 5
- ((0<<6)|(0<<4)|(3<<2)|2), // 6
- ((0<<6)|(1<<4)|(3<<2)|0), // 7
- ((0<<6)|(0<<4)|(3<<2)|0), // 8
- ((1<<6)|(2<<4)|(2<<2)|2), // 9
- ((1<<6)|(1<<4)|(2<<2)|2), // 10
- ((1<<6)|(2<<4)|(2<<2)|1), // 11
- ((1<<6)|(1<<4)|(2<<2)|1), // 12
- ((1<<6)|(2<<4)|(2<<2)|0), // 13
- ((1<<6)|(1<<4)|(2<<2)|0), // 14
- ((3<<6)|(2<<4)|(0<<2)|1), // 15 bank ahead
-};
-
-/***********************************
- * LPDDR2 define
- ***********************************/
-//MR0 (Device Information)
-#define LPDDR2_DAI (0x1) // 0:DAI complete, 1:DAI still in progress
-#define LPDDR2_DI (0x1<<1) // 0:S2 or S4 SDRAM, 1:NVM
-#define LPDDR2_DNVI (0x1<<2) // 0:DNV not supported, 1:DNV supported
-#define LPDDR2_RZQI (0x3<<3) // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
- // 10:ZQ-pin may short to GND. 11:ZQ-pin self test completed, no error condition detected.
-
-//MR1 (Device Feature)
-#define LPDDR2_BL4 (0x2)
-#define LPDDR2_BL8 (0x3)
-#define LPDDR2_BL16 (0x4)
-#define LPDDR2_nWR(n) (((n)-2)<<5)
-
-//MR2 (Device Feature 2)
-#define LPDDR2_RL3_WL1 (0x1)
-#define LPDDR2_RL4_WL2 (0x2)
-#define LPDDR2_RL5_WL2 (0x3)
-#define LPDDR2_RL6_WL3 (0x4)
-#define LPDDR2_RL7_WL4 (0x5)
-#define LPDDR2_RL8_WL4 (0x6)
-
-//MR3 (IO Configuration 1)
-#define LPDDR2_DS_34 (0x1)
-#define LPDDR2_DS_40 (0x2)
-#define LPDDR2_DS_48 (0x3)
-#define LPDDR2_DS_60 (0x4)
-#define LPDDR2_DS_80 (0x6)
-#define LPDDR2_DS_120 (0x7) //optional
-
-//MR4 (Device Temperature)
-#define LPDDR2_tREF_MASK (0x7)
-#define LPDDR2_4_tREF (0x1)
-#define LPDDR2_2_tREF (0x2)
-#define LPDDR2_1_tREF (0x3)
-#define LPDDR2_025_tREF (0x5)
-#define LPDDR2_025_tREF_DERATE (0x6)
-
-#define LPDDR2_TUF (0x1<<7)
-
-//MR8 (Basic configuration 4)
-#define LPDDR2_S4 (0x0)
-#define LPDDR2_S2 (0x1)
-#define LPDDR2_N (0x2)
-#define LPDDR2_Density(mr8) (8<<(((mr8)>>2)&0xf)) // Unit:MB
-#define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
-
-//MR10 (Calibration)
-#define LPDDR2_ZQINIT (0xFF)
-#define LPDDR2_ZQCL (0xAB)
-#define LPDDR2_ZQCS (0x56)
-#define LPDDR2_ZQRESET (0xC3)
-
-//MR16 (PASR Bank Mask)
-// S2 SDRAM Only
-#define LPDDR2_PASR_Full (0x0)
-#define LPDDR2_PASR_1_2 (0x1)
-#define LPDDR2_PASR_1_4 (0x2)
-#define LPDDR2_PASR_1_8 (0x3)
-
-//MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
-
-//MR32 (DQ Calibration Pattern A)
-
-//MR40 (DQ Calibration Pattern B)
-
-/***********************************
- * DDR3 define
- ***********************************/
-//mr0 for ddr3
-#define DDR3_BL8 (0)
-#define DDR3_BC4_8 (1)
-#define DDR3_BC4 (2)
-#define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
-#define DDR3_WR(n) (((n)&0x7)<<9)
-#define DDR3_DLL_RESET (1<<8)
-#define DDR3_DLL_DeRESET (0<<8)
-
-//mr1 for ddr3
-#define DDR3_DLL_ENABLE (0)
-#define DDR3_DLL_DISABLE (1)
-#define DDR3_MR1_AL(n) (((n)&0x3)<<3)
-
-#define DDR3_DS_40 (0)
-#define DDR3_DS_34 (1<<1)
-#define DDR3_Rtt_Nom_DIS (0)
-#define DDR3_Rtt_Nom_60 (1<<2)
-#define DDR3_Rtt_Nom_120 (1<<6)
-#define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
-
- //mr2 for ddr3
-#define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
-#define DDR3_Rtt_WR_DIS (0)
-#define DDR3_Rtt_WR_60 (1<<9)
-#define DDR3_Rtt_WR_120 (2<<9)
-
-/***********************************
- * DDR2 define
- ***********************************/
-//MR; //Mode Register
-#define DDR2_BL4 (2)
-#define DDR2_BL8 (3)
-#define DDR2_CL(n) (((n)&0x7)<<4)
-#define DDR2_WR(n) ((((n)-1)&0x7)<<9)
-#define DDR2_DLL_RESET (1<<8)
-#define DDR2_DLL_DeRESET (0<<8)
-
-//EMR; //Extended Mode Register
-#define DDR2_DLL_ENABLE (0)
-#define DDR2_DLL_DISABLE (1)
-
-#define DDR2_STR_FULL (0)
-#define DDR2_STR_REDUCE (1<<1)
-#define DDR2_AL(n) (((n)&0x7)<<3)
-#define DDR2_Rtt_Nom_DIS (0)
-#define DDR2_Rtt_Nom_150 (0x40)
-#define DDR2_Rtt_Nom_75 (0x4)
-#define DDR2_Rtt_Nom_50 (0x44)
-
-/***********************************
- * LPDDR define
- ***********************************/
-#define mDDR_BL2 (1)
-#define mDDR_BL4 (2)
-#define mDDR_BL8 (3)
-#define mDDR_CL(n) (((n)&0x7)<<4)
-
-#define mDDR_DS_Full (0)
-#define mDDR_DS_1_2 (1<<5)
-#define mDDR_DS_1_4 (2<<5)
-#define mDDR_DS_1_8 (3<<5)
-#define mDDR_DS_3_4 (4<<5)
-
-static const uint8_t ddr3_cl_cwl[22][7]={
-/*speed 0~330 331~400 401~533 534~666 667~800 801~933 934~1066
- * tCK >3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07
- * cl<<4, cwl cl<<4, cwl cl<<4, cwl */
- {((5<<4)|5), ((5<<4)|5), 0 , 0, 0, 0, 0}, //DDR3_800D (5-5-5)
- {((5<<4)|5), ((6<<4)|5), 0 , 0, 0, 0, 0}, //DDR3_800E (6-6-6)
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), 0, 0, 0, 0}, //DDR3_1066E (6-6-6)
- {((5<<4)|5), ((6<<4)|5), ((7<<4)|6), 0, 0, 0, 0}, //DDR3_1066F (7-7-7)
- {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), 0, 0, 0, 0}, //DDR3_1066G (8-8-8)
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7), 0, 0, 0}, //DDR3_1333F (7-7-7)
- {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7), 0, 0, 0}, //DDR3_1333G (8-8-8)
- {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((9<<4)|7), 0, 0, 0}, //DDR3_1333H (9-9-9)
- {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7), 0, 0, 0}, //DDR3_1333J (10-10-10)
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7), ((8<<4)|8), 0, 0}, //DDR3_1600G (8-8-8)
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7), ((9<<4)|8), 0, 0}, //DDR3_1600H (9-9-9)
- {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7), ((10<<4)|8), 0, 0}, //DDR3_1600J (10-10-10)
- {((5<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7), ((11<<4)|8), 0, 0}, //DDR3_1600K (11-11-11)
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7), ((9<<4)|8), ((11<<4)|9), 0}, //DDR3_1866J (10-10-10)
- {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((8<<4)|7), ((10<<4)|8), ((11<<4)|9), 0}, //DDR3_1866K (11-11-11)
- {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7), ((11<<4)|8), ((12<<4)|9), 0}, //DDR3_1866L (12-12-12)
- {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7), ((11<<4)|8), ((13<<4)|9), 0}, //DDR3_1866M (13-13-13)
-
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((7<<4)|7), ((9<<4)|8), ((10<<4)|9), ((11<<4)|10)}, //DDR3_2133K (11-11-11)
- {((5<<4)|5), ((5<<4)|5), ((6<<4)|6), ((8<<4)|7), ((9<<4)|8), ((11<<4)|9), ((12<<4)|10)}, //DDR3_2133L (12-12-12)
- {((5<<4)|5), ((5<<4)|5), ((7<<4)|6), ((9<<4)|7), ((10<<4)|8), ((12<<4)|9), ((13<<4)|10)}, //DDR3_2133M (13-13-13)
- {((6<<4)|5), ((6<<4)|5), ((7<<4)|6), ((9<<4)|7), ((11<<4)|8), ((13<<4)|9), ((14<<4)|10)}, //DDR3_2133N (14-14-14)
-
- {((6<<4)|5), ((6<<4)|5), ((8<<4)|6), ((10<<4)|7), ((11<<4)|8), ((13<<4)|9), ((14<<4)|10)} //DDR3_DEFAULT
-};
-
-static const uint16_t ddr3_tRC_tFAW[22]={
-/** tRC tFAW */
- ((50<<8)|50), //DDR3_800D (5-5-5)
- ((53<<8)|50), //DDR3_800E (6-6-6)
-
- ((49<<8)|50), //DDR3_1066E (6-6-6)
- ((51<<8)|50), //DDR3_1066F (7-7-7)
- ((53<<8)|50), //DDR3_1066G (8-8-8)
-
- ((47<<8)|45), //DDR3_1333F (7-7-7)
- ((48<<8)|45), //DDR3_1333G (8-8-8)
- ((50<<8)|45), //DDR3_1333H (9-9-9)
- ((51<<8)|45), //DDR3_1333J (10-10-10)
-
- ((45<<8)|40), //DDR3_1600G (8-8-8)
- ((47<<8)|40), //DDR3_1600H (9-9-9)
- ((48<<8)|40), //DDR3_1600J (10-10-10)
- ((49<<8)|40), //DDR3_1600K (11-11-11)
-
- ((45<<8)|35), //DDR3_1866J (10-10-10)
- ((46<<8)|35), //DDR3_1866K (11-11-11)
- ((47<<8)|35), //DDR3_1866L (12-12-12)
- ((48<<8)|35), //DDR3_1866M (13-13-13)
-
- ((44<<8)|35), //DDR3_2133K (11-11-11)
- ((45<<8)|35), //DDR3_2133L (12-12-12)
- ((46<<8)|35), //DDR3_2133M (13-13-13)
- ((47<<8)|35), //DDR3_2133N (14-14-14)
-
- ((53<<8)|50) //DDR3_DEFAULT
-};
-
-typedef enum DRAM_TYPE_Tag
-{
- LPDDR = 0,
- DDR,
- DDR2,
- DDR3,
- LPDDR2,
-
- DRAM_MAX
-}DRAM_TYPE;
-
-typedef struct PCTRL_TIMING_Tag
-{
- uint32 ddrFreq;
- //Memory Timing Registers
- uint32 togcnt1u; //Toggle Counter 1U Register
- uint32 tinit; //t_init Timing Register
- uint32 trsth; //Reset High Time Register
- uint32 togcnt100n; //Toggle Counter 100N Register
- uint32 trefi; //t_refi Timing Register
- uint32 tmrd; //t_mrd Timing Register
- uint32 trfc; //t_rfc Timing Register
- uint32 trp; //t_rp Timing Register
- uint32 trtw; //t_rtw Timing Register
- uint32 tal; //AL Latency Register
- uint32 tcl; //CL Timing Register
- uint32 tcwl; //CWL Register
- uint32 tras; //t_ras Timing Register
- uint32 trc; //t_rc Timing Register
- uint32 trcd; //t_rcd Timing Register
- uint32 trrd; //t_rrd Timing Register
- uint32 trtp; //t_rtp Timing Register
- uint32 twr; //t_wr Timing Register
- uint32 twtr; //t_wtr Timing Register
- uint32 texsr; //t_exsr Timing Register
- uint32 txp; //t_xp Timing Register
- uint32 txpdll; //t_xpdll Timing Register
- uint32 tzqcs; //t_zqcs Timing Register
- uint32 tzqcsi; //t_zqcsi Timing Register
- uint32 tdqs; //t_dqs Timing Register
- uint32 tcksre; //t_cksre Timing Register
- uint32 tcksrx; //t_cksrx Timing Register
- uint32 tcke; //t_cke Timing Register
- uint32 tmod; //t_mod Timing Register
- uint32 trstl; //Reset Low Timing Register
- uint32 tzqcl; //t_zqcl Timing Register
- uint32 tmrr; //t_mrr Timing Register
- uint32 tckesr; //t_ckesr Timing Register
- uint32 tdpd; //t_dpd Timing Register
-}PCTL_TIMING_T;
-
-typedef union DTPR_0_Tag
-{
- uint32 d32;
- struct
- {
- unsigned tMRD : 2;
- unsigned tRTP : 3;
- unsigned tWTR : 3;
- unsigned tRP : 4;
- unsigned tRCD : 4;
- unsigned tRAS : 5;
- unsigned tRRD : 4;
- unsigned tRC : 6;
- unsigned tCCD : 1;
- } b;
-}DTPR_0_T;
-
-typedef union DTPR_1_Tag
-{
- uint32 d32;
- struct
- {
- unsigned tAOND : 2;
- unsigned tRTW : 1;
- unsigned tFAW : 6;
- unsigned tMOD : 2;
- unsigned tRTODT : 1;
- unsigned reserved12_15 : 4;
- unsigned tRFC : 8;
- unsigned tDQSCK : 3;
- unsigned tDQSCKmax : 3;
- unsigned reserved30_31 : 2;
- } b;
-}DTPR_1_T;
-
-typedef union DTPR_2_Tag
-{
- uint32 d32;
- struct
- {
- unsigned tXS : 10;
- unsigned tXP : 5;
- unsigned tCKE : 4;
- unsigned tDLLK : 10;
- unsigned reserved29_31 : 3;
- } b;
-}DTPR_2_T;
-
-typedef struct PHY_TIMING_Tag
-{
- DTPR_0_T dtpr0;
- DTPR_1_T dtpr1;
- DTPR_2_T dtpr2;
- uint32 mr[4]; //LPDDR2 no MR0, mr[2] is mDDR MR1
-}PHY_TIMING_T;
-
-typedef union NOC_TIMING_Tag
-{
- uint32 d32;
- struct
- {
- unsigned ActToAct : 6;
- unsigned RdToMiss : 6;
- unsigned WrToMiss : 6;
- unsigned BurstLen : 3;
- unsigned RdToWr : 5;
- unsigned WrToRd : 5;
- unsigned BwRatio : 1;
- } b;
-}NOC_TIMING_T;
-
-typedef struct PCTL_REG_Tag
-{
- uint32 SCFG;
- uint32 CMDTSTATEN;
- uint32 MCFG1;
- uint32 MCFG;
- PCTL_TIMING_T pctl_timing;
- //DFI Control Registers
- uint32 DFITCTRLDELAY;
- uint32 DFIODTCFG;
- uint32 DFIODTCFG1;
- uint32 DFIODTRANKMAP;
- //DFI Write Data Registers
- uint32 DFITPHYWRDATA;
- uint32 DFITPHYWRLAT;
- //DFI Read Data Registers
- uint32 DFITRDDATAEN;
- uint32 DFITPHYRDLAT;
- //DFI Update Registers
- uint32 DFITPHYUPDTYPE0;
- uint32 DFITPHYUPDTYPE1;
- uint32 DFITPHYUPDTYPE2;
- uint32 DFITPHYUPDTYPE3;
- uint32 DFITCTRLUPDMIN;
- uint32 DFITCTRLUPDMAX;
- uint32 DFITCTRLUPDDLY;
- uint32 DFIUPDCFG;
- uint32 DFITREFMSKI;
- uint32 DFITCTRLUPDI;
- //DFI Status Registers
- uint32 DFISTCFG0;
- uint32 DFISTCFG1;
- uint32 DFITDRAMCLKEN;
- uint32 DFITDRAMCLKDIS;
- uint32 DFISTCFG2;
- //DFI Low Power Register
- uint32 DFILPCFG0;
-}PCTL_REG_T;
-
-typedef struct PUBL_REG_Tag
-{
- uint32 PIR;
- uint32 PGCR;
- uint32 DLLGCR;
- uint32 ACDLLCR;
- uint32 PTR[3];
- uint32 ACIOCR;
- uint32 DXCCR;
- uint32 DSGCR;
- uint32 DCR;
- PHY_TIMING_T phy_timing;
- uint32 ODTCR;
- uint32 DTAR;
- uint32 ZQ0CR0;
- uint32 ZQ1CR0;
-
- uint32 DX0GCR;
- uint32 DX0DLLCR;
- uint32 DX0DQTR;
- uint32 DX0DQSTR;
-
- uint32 DX1GCR;
- uint32 DX1DLLCR;
- uint32 DX1DQTR;
- uint32 DX1DQSTR;
-
- uint32 DX2GCR;
- uint32 DX2DLLCR;
- uint32 DX2DQTR;
- uint32 DX2DQSTR;
-
- uint32 DX3GCR;
- uint32 DX3DLLCR;
- uint32 DX3DQTR;
- uint32 DX3DQSTR;
-}PUBL_REG_T;
-
-typedef struct BACKUP_REG_Tag
-{
- PCTL_REG_T pctl;
- PUBL_REG_T publ;
- uint32 DdrConf;
- NOC_TIMING_T noc_timing;
- uint32 DdrMode;
- uint32 ReadLatency;
-}BACKUP_REG_T;
-
-BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
-static BACKUP_REG_T *p_ddr_reg;
-static __attribute__((aligned(4096))) uint32_t ddr_data_training_buf[32];
-uint32_t DEFINE_PIE_DATA(mem_type); // 0:LPDDR, 1:DDR, 2:DDR2, 3:DDR3, 4:LPDDR2
-static uint32_t *p_mem_type;
-static uint32_t ddr_speed_bin; // used for ddr3 only
-static uint32_t ddr_capability_per_die; // one chip cs capability
-uint32_t DEFINE_PIE_DATA(ddr_freq);
-static uint32_t ddr_freq;
-uint32_t DEFINE_PIE_DATA(ddr_sr_idle);
-
-/***********************************
- * ARCH Relative Data and Function
- ***********************************/
-static __sramdata uint32_t clkr;
-static __sramdata uint32_t clkf;
-static __sramdata uint32_t clkod;
-static __sramdata uint32_t dpllvaluel=0,gpllvaluel=0;
-uint32_t DEFINE_PIE_DATA(ddr_select_gpll_div); // 0-Disable, 1-1:1, 2-2:1, 4-4:1
-static uint32_t *p_ddr_select_gpll_div;
-bool DEFINE_PIE_DATA(ddr_soc_is_rk3188_plus);
-static bool ddr_soc_is_rk3188_plus;
-bool DEFINE_PIE_DATA(ddr_rk3188_dpll_is_good);
-static bool ddr_rk3188_dpll_is_good;
-
-static void __sramfunc ddr_delayus(uint32_t us);
-
-static uint32_t __sramfunc ddr_get_pll_freq_sram(PLL_ID pll_id) //APLL-1;CPLL-2;DPLL-3;GPLL-4
-{
- uint32_t ret = 0;
-
- // freq = (Fin/NR)*NF/OD
- if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1) // DPLL Normal mode
- ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0xffff)+1) // NF = 2*(CLKF+1)
- /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1) // NR = CLKR+1
- *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0x3F)+1)); // OD = 2^CLKOD
- else
- ret = 24;
-
- return ret;
-}
-
-static noinline uint32_t ddr_get_pll_freq(PLL_ID pll_id) //APLL-1;CPLL-2;DPLL-3;GPLL-4
-{
- uint32_t ret = 0;
-
- // freq = (Fin/NR)*NF/OD
- if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1) // DPLL Normal mode
- ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0xffff)+1) // NF = 2*(CLKF+1)
- /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1) // NR = CLKR+1
- *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0x3F)+1)); // OD = 2^CLKOD
- else
- ret = 24;
-
- return ret;
-}
-
-#if defined(CONFIG_ARCH_RK30) && (!defined(CONFIG_ARCH_RK3066B))
-/*****************************************
-NR NO NF Fout freq Step finally use
-1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
-1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
-1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
-1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
-1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
-******************************************/
-static uint32_t __sramfunc ddr_set_pll_3066(uint32_t nMHz, uint32_t set)
-{
- uint32_t ret = 0;
- int delay = 1000;
- //NOÒ»¶¨ÒªÅ¼Êý,NR¾¡Á¿Ð¡£¬jitter¾Í»áС
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
-
- if(!set)
- {
- if(nMHz <= 150)
- {
- clkod = 8;
- }
- else if(nMHz <= 200)
- {
- clkod = 6;
- }
- else if(nMHz <= 300)
- {
- clkod = 4;
- }
- else if(nMHz <= 600)
- {
- clkod = 2;
- }
- else
- {
- clkod = 1;
- }
- clkr = 1;
- clkf=(nMHz*clkr*clkod)/24;
- ret = (24*clkf)/(clkr*clkod);
- }
- else
- {
- SET_PLL_MODE(DPLL,0); //PLL slow-mode
- dsb();
- pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
- pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
- pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
- pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
- if (GET_DPLL_LOCK_STATUS())
- break;
- delay--;
- }
- SET_DDR_PLL_SRC(0, 0); //clk_ddr_src = DDR PLL, clk_ddr_src:clk_ddrphy = 1:1
- SET_PLL_MODE(DPLL,1); //PLL normal
- dsb();
- }
-out:
- return ret;
-}
-#endif
-
-#if (defined(CONFIG_ARCH_RK30) && defined(CONFIG_ARCH_RK3066B)) || defined(CONFIG_ARCH_RK3188)
-/*****************************************
-RK3066B
-NR NO NF Fout freq Step finally use
-1 14 46 - 91 78MHz - 157MHz 1.7MHz 78MHz<= 150MHz
-1 8 46 - 91 137MHz - 275MHz 3MHz 150MHz<= 200MHz
-1 6 46 - 91 183MHz - 366MHz 4MHz 200MHz<= 300MHz
-1 4 46 - 91 275MHz - 550MHz 6MHz 300MHz<= 550MHz
-1 2 46 - 91 550MHz - 1100MHz 12MHz 550MHz<= 1100MHz
-1 1 46 - 91 1100MHz - 2200MHz 24MHz 1100MHz<= 2200MHz
-******************************************/
-static uint32_t __sramfunc ddr_set_pll_rk3066b(uint32_t nMHz, uint32_t set)
-{
- uint32_t ret = 0;
- int delay = 1000;
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
-
- if(!set)
- {
- dpllvaluel = ddr_get_pll_freq_sram(DPLL);
- gpllvaluel = ddr_get_pll_freq_sram(GPLL);
-
- if(DATA(ddr_rk3188_dpll_is_good) == false) //if rk3188 DPLL is bad,use GPLL
- {
- if( (gpllvaluel < 200) ||(gpllvaluel > 2000))
- {
- ///ddr_print("DPLL is bad and GPLL freq = %dMHz,Not suitable for ddr_clock\n",gpllvaluel);
- return 0;
- }
-
- if(gpllvaluel > 1000) //GPLL:1000MHz-2000MHz
- {
- DATA(ddr_select_gpll_div)=4; //DDR_CLCOK:250MHz-500MHz
- }
- else if(gpllvaluel > 800) //GPLL:800MHz-1000MHz
- {
- if(nMHz > 250)
- DATA(ddr_select_gpll_div)=2; //DDR_CLCOK:400MHz-500MHz
- else
- DATA(ddr_select_gpll_div)=4; //DDR_CLCOK:200MHz-250MHz
- }
- else if(gpllvaluel > 500) //GPLL:500MHz-800MHz
- {
- DATA(ddr_select_gpll_div)=2; //DDR_CLCOK:250MHz-400MHz
- }
- else //GPLL:200MHz-500MHz
- {
- DATA(ddr_select_gpll_div)=1; //DDR_CLCOK:200MHz-500MHz
- }
- }
-
- if(DATA(ddr_select_gpll_div) > 0)
- {
- ret=gpllvaluel/DATA(ddr_select_gpll_div);
- }
- else
- {
- if(nMHz <= 150)
- {
- clkod = 14;
- }
- else if(nMHz <= 200)
- {
- clkod = 8;
- }
- else if(nMHz <= 300)
- {
- clkod = 6;
- }
- else if(nMHz <= 550)
- {
- clkod = 4;
- }
- else if(nMHz <= 1100)
- {
- clkod = 2;
- }
- else
- {
- clkod = 1;
- }
- clkr = 1;
- clkf=(nMHz*clkr*clkod)/24;
- ret = (24*clkf)/(clkr*clkod);
- }
-
- }
- else
- {
- if(DATA(ddr_select_gpll_div) > 0)
- {
- DDR_GPLL_CLK_GATE(0);
- SET_DDR_PLL_SRC(1, (DATA(ddr_select_gpll_div)>>1)); //clk_ddr_src = G PLL, clk_ddr_src:clk_ddrphy = 4:1/2:1/1:1
- dsb();
- }
- else if((nMHz==dpllvaluel) && (set == 1))
- {
- SET_DDR_PLL_SRC(0, 0); //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
- dsb();
- }
- else
- {
- SET_PLL_MODE(DPLL,0); //PLL slow-mode
- dsb();
-
- pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET_RK3066B;
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR_RK3066B(clkr) | NO_RK3066B(clkod);
- pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF_RK3066B(clkf);
- // pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET_RK3066B;
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
- if (GET_DPLL_LOCK_STATUS())
- break;
- delay--;
- }
-
- if(set == 1)
- SET_DDR_PLL_SRC(0, 0); //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
- SET_PLL_MODE(DPLL,1); //PLL normal
- dsb();
- }
- }
- dsb();
-out:
- return ret;
-}
-#endif
-
-#if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X)
-/*****************************************
-NR NO NF Fout freq Step finally use
-1 8 12.5 - 62.5 37.5MHz - 187.5MHz 3MHz 50MHz <= 150MHz
-1 6 12.5 - 62.5 50MHz - 250MHz 4MHz 150MHz <= 200MHz
-1 4 12.5 - 62.5 75MHz - 375MHz 6MHz 200MHz <= 300MHz
-1 2 12.5 - 62.5 150MHz - 750MHz 12MHz 300MHz <= 600MHz
-1 1 12.5 - 62.5 300MHz - 1500MHz 24MHz 600MHz <= 1200MHz
-******************************************/
-static uint32_t __sramfunc ddr_set_pll_rk3188_plus(uint32_t nMHz, uint32_t set)
-{
- uint32_t ret = 0;
- int delay = 1000;
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
-
- if(!set)
- {
- dpllvaluel = ddr_get_pll_freq_sram(DPLL);
- gpllvaluel = ddr_get_pll_freq_sram(GPLL);
-
- if(DATA(ddr_select_gpll_div) > 0)
- {
- ret = gpllvaluel/DATA(ddr_select_gpll_div);
- }
- else
- {
- if(nMHz <= 150)
- {
- clkod = 8;
- }
- else if(nMHz <= 200)
- {
- clkod = 6;
- }
- else if(nMHz <= 300)
- {
- clkod = 4;
- }
- else if(nMHz <= 600)
- {
- clkod = 2;
- }
- else
- {
- clkod = 1;
- }
- clkr = 1;
- clkf=(nMHz*clkr*clkod)/24;
- ret = (24*clkf)/(clkr*clkod);
- }
-
- }
- else
- {
- if(DATA(ddr_select_gpll_div) > 0)
- {
- DDR_GPLL_CLK_GATE(0);
- SET_DDR_PLL_SRC(1, (DATA(ddr_select_gpll_div)>>1)); //clk_ddr_src = G PLL,clk_ddr_src:clk_ddrphy = 4:1/2:1/1:1
- dsb();
- }
- else if((nMHz==dpllvaluel) && (set == 1))
- {
- SET_DDR_PLL_SRC(0, 0); //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
- dsb();
- }
- else
- {
- SET_PLL_MODE(DPLL,0); //PLL slow-mode
- dsb();
-
- pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
- pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
- pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
- if (GET_DPLL_LOCK_STATUS())
- break;
- delay--;
- }
-
- if(set == 1)
- SET_DDR_PLL_SRC(0, 0); //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
- SET_PLL_MODE(DPLL,1); //PLL normal
- dsb();
- }
- }
- dsb();
-out:
- return ret;
-}
-#endif
-
-uint32_t PIE_FUNC(ddr_set_pll)(uint32_t nMHz, uint32_t set)
-{
-#if defined(CONFIG_ARCH_RK3188)
- if(DATA(ddr_soc_is_rk3188_plus) == true)
- return ddr_set_pll_rk3188_plus(nMHz,set);
- else
- return ddr_set_pll_rk3066b(nMHz,set);
-#elif defined(CONFIG_ARCH_RK30) && defined(CONFIG_ARCH_RK3066B)
- return ddr_set_pll_rk3066b(nMHz,set);
-#elif defined(CONFIG_ARCH_RK319X)
- return ddr_set_pll_rk3188_plus(nMHz,set);
-#else
- return ddr_set_pll_3066(nMHz,set);
-#endif
-}
-EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
-static uint32_t (*p_ddr_set_pll)(uint32_t nMHz, uint32_t set);
-
-#ifdef CONFIG_ARCH_RK319X
-static void __sramfunc idle_port(void)
-{
- int i;
- uint32 clk_gate[16];
-
- //save clock gate status
- for(i=0;i<16;i++)
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
-
- //enable all clock gate for request idle
- for(i=0;i<16;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
-
- /*
- pPMU_Reg->PMU_NOC_REQ |= idle_req_bp2ap_rk319x;
- dsb();
- while(((pPMU_Reg->PMU_NOC_ST) & idle_req_bp2ap_rk319x) == 0);
- */
-
- pPMU_Reg->PMU_NOC_REQ |= idle_req_dma_cfg_rk319x;
- dsb();
- while(((pPMU_Reg->PMU_NOC_ST) & idle_req_dma_cfg_rk319x) == 0);
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st_rk319x) == 0 )
- {
- pPMU_Reg->PMU_NOC_REQ |= idle_req_peri_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_peri_rk319x) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st_rk319x) == 0 )
- {
- pPMU_Reg->PMU_NOC_REQ |= idle_req_vio_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_vio_rk319x) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st_rk319x) == 0 )
- {
- pPMU_Reg->PMU_NOC_REQ |= idle_req_video_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_video_rk319x) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st_rk319x) == 0 )
- {
- pPMU_Reg->PMU_NOC_REQ |= idle_req_gpu_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_gpu_rk319x) == 0 );
- }
-
- //resume clock gate status
- for(i=0;i<16;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-}
-
-static void __sramfunc deidle_port(void)
-{
- int i;
- uint32 clk_gate[16];
-
- //save clock gate status
- for(i=0;i<16;i++)
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
-
- //enable all clock gate for request idle
- for(i=0;i<16;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
-
- /*
- pPMU_Reg->PMU_NOC_REQ &= ~idle_req_bp2ap_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_bp2ap_rk319x) != 0 );
- */
-
- pPMU_Reg->PMU_NOC_REQ &= ~idle_req_dma_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_dma_rk319x) != 0 );
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st_rk319x) == 0 )
- {
- pPMU_Reg->PMU_NOC_REQ &= ~idle_req_peri_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_peri_rk319x) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st_rk319x) == 0 )
- {
- pPMU_Reg->PMU_NOC_REQ &= ~idle_req_vio_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_vio_rk319x) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st_rk319x) == 0 )
- {
- pPMU_Reg->PMU_NOC_REQ &= ~idle_req_video_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_video_rk319x) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st_rk319x) == 0 )
- {
- pPMU_Reg->PMU_NOC_REQ &= ~idle_req_gpu_cfg_rk319x;
- dsb();
- while( (pPMU_Reg->PMU_NOC_ST & idle_gpu_rk319x) != 0 );
- }
-
- //resume clock gate status
- for(i=0;i<16;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-
-}
-#else
-static void __sramfunc idle_port(void)
-{
- int i;
- uint32 clk_gate[10];
-
- //save clock gate status
- for(i=0;i<10;i++)
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
-
- //enable all clock gate for request idle
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
- {
-#ifdef CONFIG_ARCH_RK3188
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_dma_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) == 0 );
-#else
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
-#endif
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_peri_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_vio_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_video_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) == 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 |= idle_req_gpu_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) == 0 );
- }
-
- //resume clock gate status
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-}
-
-static void __sramfunc deidle_port(void)
-{
- int i;
- uint32 clk_gate[10];
-
- //save clock gate status
- for(i=0;i<10;i++)
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
-
- //enable all clock gate for request idle
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
- {
-
-#ifdef CONFIG_ARCH_RK3188
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_dma_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) != 0 );
-#else
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
-#endif
- }
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_peri_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_vio_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_video_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) != 0 );
- }
-
- if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
- {
- pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_gpu_cfg;
- dsb();
- while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) != 0 );
- }
-
- //resume clock gate status
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-
-}
-#endif
-
-/***********************************
- * Only DDR Relative Function
- ***********************************/
-
-/****************************************************************************
-Internal sram us delay function
-Cpu highest frequency is 1.6 GHz
-1 cycle = 1/1.6 ns
-1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
-*****************************************************************************/
-static __sramdata volatile uint32_t loops_per_us;
-
-#define LPJ_100MHZ 999456UL
-
-static void __sramfunc ddr_delayus(uint32_t us)
-{
- do
- {
- unsigned int i = (loops_per_us*us);
- if (i < 7) i = 7;
- barrier();
- asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
- } while (0);
-}
-
-static __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
-{
- uint32 i;
-
- for(i=0; i<words; i++)
- {
- pDest[i] = pSrc[i];
- }
-}
-
-static uint32 ddr_get_row(void)
-{
- uint32 i;
- uint32 row;
-
- if(DDR_SYS_REG())
- {
- row=READ_CS0_ROW_INFO();
- }
- else
- {
- i = *(volatile uint32*)SysSrv_DdrConf;
- row = 13+((ddr_cfg_2_rbc[i]>>4)&0x3);
- if(DDR_GET_RANK_2_ROW15())
- {
- row += 1;
- }
- }
- return row;
-}
-
-static uint32 ddr_get_bank(void)
-{
- uint32 i;
- uint32 bank;
-
- if(DDR_SYS_REG())
- {
- bank = READ_BK_INFO();
- }
- else
- {
- i = *(volatile uint32*)SysSrv_DdrConf;
- bank = ((ddr_cfg_2_rbc[i]>>6)&0x3) + ((ddr_cfg_2_rbc[i]>>2)&0x3);
- if(DDR_GET_BANK_2_RANK())
- {
- bank -= 1;
- }
- }
- return bank;
-}
-
-static uint32 ddr_get_col(void)
-{
- uint32 i;
- uint32 col;
-
- if(DDR_SYS_REG())
- {
- col=READ_COL_INFO();
- }
- else
- {
- i = *(volatile uint32*)SysSrv_DdrConf;
- col = 9+(ddr_cfg_2_rbc[i]&0x3);
- if(pDDR_Reg->PPCFG & 1)
- {
- col +=1;
- }
- }
- return col;
-}
-
-static uint32 ddr_get_bw(void)
-{
- uint32 bw;
-
- if(pDDR_Reg->PPCFG & 1)
- {
- bw=1;
- }
- else
- {
- bw=2;
- }
- return bw;
-}
-
-static uint32 ddr_get_cs(void)
-{
- uint32 cs;
-
- switch((pPHY_Reg->PGCR>>18) & 0xF)
- {
- case 0xF:
- cs = 4;
- case 7:
- cs = 3;
- break;
- case 3:
- cs = 2;
- break;
- default:
- cs = 1;
- break;
- }
- return cs;
-}
-
-static uint32_t ddr_get_datatraing_addr(void)
-{
- uint32_t value=0;
- uint32_t addr;
- uint32_t col = 0;
- uint32_t row = 0;
- uint32_t bank = 0;
- uint32_t bw = 0;
- uint32_t i;
-
- // caculate aglined physical address
- addr = __pa((unsigned long)ddr_data_training_buf);
- if(addr&0x3F)
- {
- addr += (64-(addr&0x3F));
- }
- addr -= 0x60000000;
- // find out col£¬row£¬bank
- row = ddr_get_row();
- bank = ddr_get_bank();
- col = ddr_get_col();
- bw = ddr_get_bw();
- // according different address mapping, caculate DTAR register value
- i = (*(volatile uint32*)SysSrv_DdrConf);
- value |= (addr>>bw) & ((0x1<<col)-1); // col
- if(row==16)
- {
- value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & 0x7FFF) << 12; // row
- value |= (((addr>>(bw+col+bank+15))&0x1)<<15)<<12;
- row = 15; //use for bank
- }
- else
- {
- value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & ((0x1<<row)-1)) << 12; // row
- }
- if(((ddr_cfg_2_rbc[i]>>6)&0x3)==1)
- {
- value |= (((addr>>(bw+col)) & 0x3) << 28)
- | (((addr>>(bw+col+2+row)) & (bank-2)) << 30); // bank
- }
- else if(((ddr_cfg_2_rbc[i]>>6)&0x3)==3)
- {
- value |= (((addr>>(bw+col+row)) & ((0x1<<bank)-1)) << 28); // bank
- }
- else
- {
- value |= (((addr>>(bw+col)) & 0x7) << 28); // bank
- }
-
- return value;
-}
-
-static __sramfunc void ddr_reset_dll(void)
-{
- pPHY_Reg->ACDLLCR &= ~0x40000000;
- pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
- pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
- pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
- }
- ddr_delayus(1);
- pPHY_Reg->ACDLLCR |= 0x40000000;
- pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
- pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
- pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
- }
- ddr_delayus(1);
-}
-
-static __sramfunc void ddr_move_to_Lowpower_state(void)
-{
- volatile uint32 value;
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if(value == Low_power)
- {
- break;
- }
- switch(value)
- {
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- case Config:
- pDDR_Reg->SCTL = GO_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- case Access:
- pDDR_Reg->SCTL = SLEEP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
- break;
- default: //Transitional state
- break;
- }
- }
-}
-
-static __sramfunc void ddr_move_to_Access_state(void)
-{
- volatile uint32 value;
-
- //set auto self-refresh idle
- pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00) | DATA(ddr_sr_idle) | (1<<31);
- dsb();
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if((value == Access)
- || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
- {
- break;
- }
- switch(value)
- {
- case Low_power:
- pDDR_Reg->SCTL = WAKEUP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
- break;
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- case Config:
- pDDR_Reg->SCTL = GO_STATE;
- dsb();
- while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
- || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
- break;
- default: //Transitional state
- break;
- }
- }
- /* de_hw_wakeup :enable auto sr if sr_idle != 0 */
- DDR_HW_WAKEUP(0);
-}
-
-static __sramfunc void ddr_move_to_Config_state(void)
-{
- volatile uint32 value;
-
- /* hw_wakeup :disable auto sr */
- DDR_HW_WAKEUP(1);
- dsb();
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if(value == Config)
- {
- break;
- }
- switch(value)
- {
- case Low_power:
- pDDR_Reg->SCTL = WAKEUP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- while((pPHY_Reg->PGSR & DLDONE) != DLDONE); //wait DLL lock
- case Access:
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- break;
- default: //Transitional state
- break;
- }
- }
-}
-
-//arg°üÀ¨bank_addrºÍcmd_addr
-static void __sramfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
-{
- pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
- dsb();
- while(pDDR_Reg->MCMD & start_cmd);
-}
-
-//¶ÔtypeÀàÐ͵ÄDDRµÄ¼¸¸öcs½øÐÐDTT
-//0 DTT³É¹¦
-//!0 DTTʧ°Ü
-static uint32_t __sramfunc ddr_data_training(void)
-{
- uint32 value,cs,i,byte=2;
-
- // disable auto refresh
- value = pDDR_Reg->TREFI;
- pDDR_Reg->TREFI = 0;
- dsb();
- if(DATA(mem_type) != LPDDR2)
- {
- // passive window
- pPHY_Reg->PGCR |= (1<<1);
- }
- // clear DTDONE status
- pPHY_Reg->PIR |= CLRSR;
- cs = ((pPHY_Reg->PGCR>>18) & 0xF);
- pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (1<<18); //use cs0 dtt
- // trigger DTT
- pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
- dsb();
- // wait echo byte DTDONE
- while((pPHY_Reg->DATX8[0].DXGSR[0] & 1) != 1);
- while((pPHY_Reg->DATX8[1].DXGSR[0] & 1) != 1);
- if(!(pDDR_Reg->PPCFG & 1))
- {
- while((pPHY_Reg->DATX8[2].DXGSR[0] & 1) != 1);
- while((pPHY_Reg->DATX8[3].DXGSR[0] & 1) != 1);
- byte=4;
- }
- pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (cs<<18); //restore cs
- for(i=0;i<byte;i++)
- {
- pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<3)|(0x3<<14))))
- | ((pPHY_Reg->DATX8[i].DXDQSTR & 0x7)<<3)
- | (((pPHY_Reg->DATX8[i].DXDQSTR>>12) & 0x3)<<14);
- }
- // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×ʱ¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
- if(cs > 1)
- {
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- }
- else
- {
- ddr_send_command(cs, REF_cmd, 0);
- ddr_send_command(cs, REF_cmd, 0);
- }
- if(DATA(mem_type) != LPDDR2)
- {
- // active window
- pPHY_Reg->PGCR &= ~(1<<1);
- }
- // resume auto refresh
- pDDR_Reg->TREFI = value;
-
- if(pPHY_Reg->PGSR & DTERR)
- {
- return (-1);
- }
- else
- {
- return 0;
- }
-}
-
-static void __sramfunc ddr_set_dll_bypass(uint32 freq)
-{
- if(freq<=150)
- {
- pPHY_Reg->DLLGCR &= ~(1<<23);
- pPHY_Reg->ACDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
- pPHY_Reg->PIR |= DLLBYP;
- }
- else if(freq<=250)
- {
- pPHY_Reg->DLLGCR |= (1<<23);
- pPHY_Reg->ACDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
- pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
- pPHY_Reg->PIR |= DLLBYP;
- }
- else
- {
- pPHY_Reg->DLLGCR &= ~(1<<23);
- pPHY_Reg->ACDLLCR &= ~0x80000000;
- pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
- pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
- pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
- }
- pPHY_Reg->PIR &= ~DLLBYP;
- }
-}
-
-static noinline uint32_t ddr_get_parameter(uint32_t nMHz)
-{
- uint32_t tmp;
- uint32_t ret = 0;
- uint32_t al;
- uint32_t bl,bl_tmp;
- uint32_t cl;
- uint32_t cwl;
- PCTL_TIMING_T *p_pctl_timing=&(p_ddr_reg->pctl.pctl_timing);
- PHY_TIMING_T *p_publ_timing=&(p_ddr_reg->publ.phy_timing);
- NOC_TIMING_T *p_noc_timing=&(p_ddr_reg->noc_timing);
-
- p_pctl_timing->togcnt1u = nMHz;
- p_pctl_timing->togcnt100n = nMHz/10;
- p_pctl_timing->tinit = 200;
- p_pctl_timing->trsth = 500;
-
- if(*p_mem_type == DDR3)
- {
- if(ddr_speed_bin > DDR3_DEFAULT){
- ret = -1;
- goto out;
- }
-
- #define DDR3_tREFI_7_8_us (78) //unit 100ns
- #define DDR3_tMRD (4) //tCK
- #define DDR3_tRFC_512Mb (90) //ns
- #define DDR3_tRFC_1Gb (110) //ns
- #define DDR3_tRFC_2Gb (160) //ns
- #define DDR3_tRFC_4Gb (300) //ns
- #define DDR3_tRFC_8Gb (350) //ns
- #define DDR3_tRTW (2) //register min valid value
- #define DDR3_tRAS (37) //ns
- #define DDR3_tRRD (10) //ns
- #define DDR3_tRTP (7) //ns
- #define DDR3_tWR (15) //ns
- #define DDR3_tWTR (7) //ns
- #define DDR3_tXP (7) //ns
- #define DDR3_tXPDLL (24) //ns
- #define DDR3_tZQCS (80) //ns
- #define DDR3_tZQCSI (0) //ns
- #define DDR3_tDQS (1) //tCK
- #define DDR3_tCKSRE (10) //ns
- #define DDR3_tCKE_400MHz (7) //ns
- #define DDR3_tCKE_533MHz (6) //ns
- #define DDR3_tMOD (15) //ns
- #define DDR3_tRSTL (100) //ns
- #define DDR3_tZQCL (320) //ns
- #define DDR3_tDLLK (512) //tCK
-
- al = 0;
- bl = 8;
- if(nMHz <= 330)
- {
- tmp = 0;
- }
- else if(nMHz<=400)
- {
- tmp = 1;
- }
- else if(nMHz<=533)
- {
- tmp = 2;
- }
- else if(nMHz<=666)
- {
- tmp = 3;
- }
- else if(nMHz<=800)
- {
- tmp = 4;
- }
- else if(nMHz<=933)
- {
- tmp = 5;
- }
- else
- {
- tmp = 6;
- }
-
- if(nMHz < DDR3_DDR2_DLL_DISABLE_FREQ) //when dll bypss cl = cwl = 6;
- {
- cl = 6;
- cwl = 6;
- }
- else
- {
- cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
- cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
- }
- if(cl == 0)
- ret = -4;
- if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
- {
- p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
- }
- else
- {
- p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
- }
- p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
- p_publ_timing->mr[3] = 0;
- /**************************************************
- * PCTL Timing
- **************************************************/
- /*
- * tREFI, average periodic refresh interval, 7.8us
- */
- p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
- /*
- * tMRD, 4 tCK
- */
- p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
- p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
- /*
- * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
- */
- if(ddr_capability_per_die <= 0x4000000) // 512Mb 90ns
- {
- tmp = DDR3_tRFC_512Mb;
- }
- else if(ddr_capability_per_die <= 0x8000000) // 1Gb 110ns
- {
- tmp = DDR3_tRFC_1Gb;
- }
- else if(ddr_capability_per_die <= 0x10000000) // 2Gb 160ns
- {
- tmp = DDR3_tRFC_2Gb;
- }
- else if(ddr_capability_per_die <= 0x20000000) // 4Gb 300ns
- {
- tmp = DDR3_tRFC_4Gb;
- }
- else // 8Gb 350ns
- {
- tmp = DDR3_tRFC_8Gb;
- }
- p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
- p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
- /*
- * tXSR, =tDLLK=512 tCK
- */
- p_pctl_timing->texsr = DDR3_tDLLK;
- p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
- /*
- * tRP=CL
- */
- p_pctl_timing->trp = cl;
- p_publ_timing->dtpr0.b.tRP = cl;
- /*
- * WrToMiss=WL*tCK + tWR + tRP + tRCD
- */
- p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
- /*
- * tRC=tRAS+tRP
- */
- p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
- p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
- p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0xF;
-
- p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
- p_publ_timing->dtpr1.b.tRTW = 0;
- p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
- p_pctl_timing->tal = al;
- p_pctl_timing->tcl = cl;
- p_pctl_timing->tcwl = cwl;
- /*
- * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
- */
- p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
- p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x1F;
- /*
- * tRCD=CL
- */
- p_pctl_timing->trcd = cl;
- p_publ_timing->dtpr0.b.tRCD = cl;
- /*
- * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
- * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
- * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
- *
- */
- tmp = ((DDR3_tRRD*nMHz+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->trrd = (tmp&0xF);
- p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
- /*
- * tRTP, max(4 tCK,7.5ns)
- */
- tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->trtp = tmp&0xF;
- p_publ_timing->dtpr0.b.tRTP = tmp;
- /*
- * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
- */
- p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
- /*
- * tWR, 15ns
- */
- tmp = ((DDR3_tWR*nMHz+999)/1000);
- p_pctl_timing->twr = tmp&0x1F;
- if(tmp<9)
- tmp = tmp - 4;
- else
- tmp = tmp>>1;
- bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
- p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
-
- /*
- * tWTR, max(4 tCK,7.5ns)
- */
- tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->twtr = tmp&0xF;
- p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
- p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
- /*
- * tXP, max(3 tCK, 7.5ns)(<933MHz)
- */
- tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->txp = tmp&0x7;
- /*
- * tXPDLL, max(10 tCK,24ns)
- */
- tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
- if(tmp < 10)
- {
- tmp = 10;
- }
- p_pctl_timing->txpdll = tmp & 0x3F;
- p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
- /*
- * tZQCS, max(64 tCK, 80ns)
- */
- tmp = ((DDR3_tZQCS*nMHz+999)/1000);
- if(tmp < 64)
- {
- tmp = 64;
- }
- p_pctl_timing->tzqcs = tmp&0x7F;
- /*
- * tZQCSI,
- */
- p_pctl_timing->tzqcsi = DDR3_tZQCSI;
- /*
- * tDQS,
- */
- p_pctl_timing->tdqs = DDR3_tDQS;
- /*
- * tCKSRE, max(5 tCK, 10ns)
- */
- tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
- if(tmp < 5)
- {
- tmp = 5;
- }
- p_pctl_timing->tcksre = tmp & 0x1F;
- /*
- * tCKSRX, max(5 tCK, 10ns)
- */
- p_pctl_timing->tcksrx = tmp & 0x1F;
- /*
- * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
- */
- if(nMHz>=533)
- {
- tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
- }
- else
- {
- tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
- }
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->tcke = tmp & 0x7;
- p_publ_timing->dtpr2.b.tCKE = tmp;
- /*
- * tCKESR, =tCKE + 1tCK
- */
- p_pctl_timing->tckesr = (tmp+1)&0xF;
- /*
- * tMOD, max(12 tCK,15ns)
- */
- tmp = ((DDR3_tMOD*nMHz+999)/1000);
- if(tmp < 12)
- {
- tmp = 12;
- }
- p_pctl_timing->tmod = tmp&0x1F;
- p_publ_timing->dtpr1.b.tMOD = tmp;
- /*
- * tRSTL, 100ns
- */
- p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
- /*
- * tZQCL, max(256 tCK, 320ns)
- */
- tmp = ((DDR3_tZQCL*nMHz+999)/1000);
- if(tmp < 256)
- {
- tmp = 256;
- }
- p_pctl_timing->tzqcl = tmp&0x3FF;
- /*
- * tMRR, 0 tCK
- */
- p_pctl_timing->tmrr = 0;
- /*
- * tDPD, 0
- */
- p_pctl_timing->tdpd = 0;
-
- /**************************************************
- * PHY Timing
- **************************************************/
- /*
- * tCCD, BL/2 for DDR2 and 4 for DDR3
- */
- p_publ_timing->dtpr0.b.tCCD = 0;
- /*
- * tDQSCKmax,5.5ns
- */
- p_publ_timing->dtpr1.b.tDQSCKmax = 0;
- /*
- * tRTODT, 0:ODT may be turned on immediately after read post-amble
- * 1:ODT may not be turned on until one clock after the read post-amble
- */
- p_publ_timing->dtpr1.b.tRTODT = 1;
- /*
- * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page) 50ns(533MHz 2KB page)
- */
- p_publ_timing->dtpr1.b.tFAW = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000)&0x7F;
- /*
- * tAOND_tAOFD
- */
- p_publ_timing->dtpr1.b.tAOND = 0;
- /*
- * tDLLK,512 tCK
- */
- p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
- /**************************************************
- * NOC Timing
- **************************************************/
- p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
- }
- else if(*p_mem_type == LPDDR2)
- {
- #define LPDDR2_tREFI_3_9_us (38) //unit 100ns
- #define LPDDR2_tREFI_7_8_us (78) //unit 100ns
- #define LPDDR2_tMRD (5) //tCK
- #define LPDDR2_tRFC_8Gb (210) //ns
- #define LPDDR2_tRFC_4Gb (130) //ns
- #define LPDDR2_tRP_4_BANK (24) //ns
- #define LPDDR2_tRPab_SUB_tRPpb_4_BANK (0)
- #define LPDDR2_tRP_8_BANK (27) //ns
- #define LPDDR2_tRPab_SUB_tRPpb_8_BANK (3)
- #define LPDDR2_tRTW (1) //tCK register min valid value
- #define LPDDR2_tRAS (42) //ns
- #define LPDDR2_tRCD (24) //ns
- #define LPDDR2_tRRD (10) //ns
- #define LPDDR2_tRTP (7) //ns
- #define LPDDR2_tWR (15) //ns
- #define LPDDR2_tWTR_GREAT_200MHz (7) //ns
- #define LPDDR2_tWTR_LITTLE_200MHz (10) //ns
- #define LPDDR2_tXP (7) //ns
- #define LPDDR2_tXPDLL (0)
- #define LPDDR2_tZQCS (90) //ns
- #define LPDDR2_tZQCSI (0)
- #define LPDDR2_tDQS (1)
- #define LPDDR2_tCKSRE (1) //tCK
- #define LPDDR2_tCKSRX (2) //tCK
- #define LPDDR2_tCKE (3) //tCK
- #define LPDDR2_tMOD (0)
- #define LPDDR2_tRSTL (0)
- #define LPDDR2_tZQCL (360) //ns
- #define LPDDR2_tMRR (2) //tCK
- #define LPDDR2_tCKESR (15) //ns
- #define LPDDR2_tDPD_US (500)
- #define LPDDR2_tFAW_GREAT_200MHz (50) //ns
- #define LPDDR2_tFAW_LITTLE_200MHz (60) //ns
- #define LPDDR2_tDLLK (2) //tCK
- #define LPDDR2_tDQSCK_MAX (3) //tCK
- #define LPDDR2_tDQSCK_MIN (0) //tCK
- #define LPDDR2_tDQSS (1) //tCK
-
- uint32 trp_tmp;
- uint32 trcd_tmp;
- uint32 tras_tmp;
- uint32 trtp_tmp;
- uint32 twr_tmp;
-
- al = 0;
- if(nMHz>=200)
- {
- bl = 4; //you can change burst here
- }
- else
- {
- bl = 8; // freq < 200MHz, BL fixed 8
- }
- /* 1066 933 800 667 533 400 333
- * RL, 8 7 6 5 4 3 3
- * WL, 4 4 3 2 2 1 1
- */
- if(nMHz<=200)
- {
- cl = 3;
- cwl = 1;
- p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
- }
- else if(nMHz<=266)
- {
- cl = 4;
- cwl = 2;
- p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
- }
- else if(nMHz<=333)
- {
- cl = 5;
- cwl = 2;
- p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
- }
- else if(nMHz<=400)
- {
- cl = 6;
- cwl = 3;
- p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
- }
- else if(nMHz<=466)
- {
- cl = 7;
- cwl = 4;
- p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
- }
- else //(nMHz<=1066)
- {
- cl = 8;
- cwl = 4;
- p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
- }
- p_publ_timing->mr[3] = LPDDR2_DS_34;
- p_publ_timing->mr[0] = 0;
- /**************************************************
- * PCTL Timing
- **************************************************/
- /*
- * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
- */
- if(ddr_capability_per_die >= 0x10000000) // 2Gb
- {
- p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
- }
- else
- {
- p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
- }
-
- /*
- * tMRD, (=tMRW), 5 tCK
- */
- p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
- p_publ_timing->dtpr0.b.tMRD = 3;
- /*
- * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
- */
- if(ddr_capability_per_die >= 0x40000000) // 8Gb
- {
- p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
- p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000)&0xFF;
- /*
- * tXSR, max(2tCK,tRFC+10ns)
- */
- tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
- }
- else
- {
- p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
- p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000)&0xFF;
- tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
- }
- if(tmp<2)
- {
- tmp=2;
- }
- p_pctl_timing->texsr = tmp&0x3FF;
- p_publ_timing->dtpr2.b.tXS = tmp&0x3FF;
-
- /*
- * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
- */
- if(pPHY_Reg->DCR.b.DDR8BNK)
- {
- trp_tmp = ((LPDDR2_tRP_8_BANK*nMHz+999)/1000);
- if(trp_tmp<3)
- {
- trp_tmp=3;
- }
- p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
- }
- else
- {
- trp_tmp = ((LPDDR2_tRP_4_BANK*nMHz+999)/1000);
- if(trp_tmp<3)
- {
- trp_tmp=3;
- }
- p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
- }
- p_publ_timing->dtpr0.b.tRP = trp_tmp;
- /*
- * tRAS, max(3tCK,42ns)
- */
- tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
- if(tras_tmp<3)
- {
- tras_tmp=3;
- }
- p_pctl_timing->tras = (tras_tmp&0x3F);
- p_publ_timing->dtpr0.b.tRAS = tras_tmp&0x1F;
-
- /*
- * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
- */
- trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
- if(trcd_tmp<3)
- {
- trcd_tmp=3;
- }
- p_pctl_timing->trcd = (trcd_tmp&0xF);
- p_publ_timing->dtpr0.b.tRCD = trcd_tmp&0xF;
-
- /*
- * tRTP, max(2tCK, 7.5ns)
- */
- trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
- if(trtp_tmp<2)
- {
- trtp_tmp = 2;
- }
- p_pctl_timing->trtp = trtp_tmp&0xF;
- p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
-
- /*
- * tWR, max(3tCK,15ns)
- */
- twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
- if(twr_tmp<3)
- {
- twr_tmp=3;
- }
- p_pctl_timing->twr = twr_tmp&0x1F;
- bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
- p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
-
- /*
- * WrToMiss=WL*tCK + tDQSS + tWR + tRP + tRCD
- */
- p_noc_timing->b.WrToMiss = ((cwl+LPDDR2_tDQSS+twr_tmp+trp_tmp+trcd_tmp)&0x3F);
- /*
- * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
- */
- p_noc_timing->b.RdToMiss = ((trtp_tmp+trp_tmp+trcd_tmp-(bl>>1))&0x3F);
- /*
- * tRC=tRAS+tRP
- */
- p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
- p_noc_timing->b.ActToAct = ((tras_tmp+trp_tmp)&0x3F);
- p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp)&0xF;
-
- /*
- * RdToWr=RL+tDQSCK-WL
- */
- p_pctl_timing->trtw = (cl+LPDDR2_tDQSCK_MAX+(bl/2)+1-cwl);//LPDDR2_tRTW;
- p_publ_timing->dtpr1.b.tRTW = 0;
- p_noc_timing->b.RdToWr = ((cl+LPDDR2_tDQSCK_MAX+1-cwl)&0x1F);
- p_pctl_timing->tal = al;
- p_pctl_timing->tcl = cl;
- p_pctl_timing->tcwl = cwl;
- /*
- * tRRD, max(2tCK,10ns)
- */
- tmp=((LPDDR2_tRRD*nMHz+999)/1000);
- if(tmp<2)
- {
- tmp=2;
- }
- p_pctl_timing->trrd = (tmp&0xF);
- p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
- /*
- * tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz))
- */
- if(nMHz > 200)
- {
- tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
- }
- else
- {
- tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
- }
- if(tmp<2)
- {
- tmp=2;
- }
- p_pctl_timing->twtr = tmp&0xF;
- p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
- /*
- * WrToRd=WL+tDQSS+tWTR
- */
- p_noc_timing->b.WrToRd = ((cwl+LPDDR2_tDQSS+tmp)&0x1F);
- /*
- * tXP, max(2tCK,7.5ns)
- */
- tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp<2)
- {
- tmp=2;
- }
- p_pctl_timing->txp = tmp&0x7;
- p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
- /*
- * tXPDLL, 0ns
- */
- p_pctl_timing->txpdll = LPDDR2_tXPDLL;
- /*
- * tZQCS, 90ns
- */
- p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
- /*
- * tZQCSI,
- */
- if(pDDR_Reg->MCFG &= lpddr2_s4)
- {
- p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
- }
- else
- {
- p_pctl_timing->tzqcsi = 0;
- }
- /*
- * tDQS,
- */
- p_pctl_timing->tdqs = LPDDR2_tDQS;
- /*
- * tCKSRE, 1 tCK
- */
- p_pctl_timing->tcksre = LPDDR2_tCKSRE;
- /*
- * tCKSRX, 2 tCK
- */
- p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
- /*
- * tCKE, 3 tCK
- */
- p_pctl_timing->tcke = LPDDR2_tCKE;
- p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
- /*
- * tMOD, 0 tCK
- */
- p_pctl_timing->tmod = LPDDR2_tMOD;
- p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
- /*
- * tRSTL, 0 tCK
- */
- p_pctl_timing->trstl = LPDDR2_tRSTL;
- /*
- * tZQCL, 360ns
- */
- p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
- /*
- * tMRR, 2 tCK
- */
- p_pctl_timing->tmrr = LPDDR2_tMRR;
- /*
- * tCKESR, max(3tCK,15ns)
- */
- tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->tckesr = tmp&0xF;
- /*
- * tDPD, 500us
- */
- p_pctl_timing->tdpd = LPDDR2_tDPD_US;
-
- /**************************************************
- * PHY Timing
- **************************************************/
- /*
- * tCCD, BL/2 for DDR2 and 4 for DDR3
- */
- p_publ_timing->dtpr0.b.tCCD = 0;
- /*
- * tDQSCKmax,5.5ns
- */
- p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
- /*
- * tDQSCKmin,2.5ns
- */
- p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
- /*
- * tRTODT, 0:ODT may be turned on immediately after read post-amble
- * 1:ODT may not be turned on until one clock after the read post-amble
- */
- p_publ_timing->dtpr1.b.tRTODT = 1;
- /*
- * tFAW,max(8tCK, 50ns(200-533MHz) 60ns(166MHz))
- */
- if(nMHz>=200)
- {
- tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
- }
- else
- {
- tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
- }
- if(tmp<8)
- {
- tmp=8;
- }
- p_publ_timing->dtpr1.b.tFAW = tmp&0x7F;
- /*
- * tAOND_tAOFD
- */
- p_publ_timing->dtpr1.b.tAOND = 0;
- /*
- * tDLLK,0
- */
- p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
- /**************************************************
- * NOC Timing
- **************************************************/
- p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
- }
-
-out:
- return ret;
-}
-
-static uint32_t __sramfunc ddr_update_timing(void)
-{
- uint32_t i,bl_tmp=0;
- PCTL_TIMING_T *p_pctl_timing=&(DATA(ddr_reg).pctl.pctl_timing);
- PHY_TIMING_T *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
- NOC_TIMING_T *p_noc_timing=&(DATA(ddr_reg).noc_timing);
-
- ddr_copy((uint32_t *)&(pDDR_Reg->TOGCNT1U), (uint32_t*)&(p_pctl_timing->togcnt1u), 34);
- ddr_copy((uint32_t *)&(pPHY_Reg->DTPR[0]), (uint32_t*)&(p_publ_timing->dtpr0), 3);
- *(volatile uint32_t *)SysSrv_DdrTiming = p_noc_timing->d32;
- // Update PCTL BL
- if(DATA(mem_type) == DDR3)
- {
- bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
- if((DATA(ddr_freq) <= DDR3_DDR2_DLL_DISABLE_FREQ) && (true == DATA(ddr_soc_is_rk3188_plus)))
- {
- pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-3;
- }
- else
- {
- pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-2;
- }
- pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
- }
- else if(DATA(mem_type) == LPDDR2)
- {
- if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
- {
- bl_tmp = mddr_lpddr2_bl_8;
- }
- else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
- {
- bl_tmp = mddr_lpddr2_bl_4;
- }
- else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
- {
- bl_tmp = mddr_lpddr2_bl_16;
- }
- if(DATA(ddr_freq)>=200)
- {
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
- }
- else
- {
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
- }
- i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
- pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8); //tDQSCKmax-tDQSCK
- pDDR_Reg->DFITRDDATAEN = pDDR_Reg->TCL-1;
- pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL;
- }
-
- return 0;
-}
-
-static uint32_t __sramfunc ddr_update_mr(void)
-{
- PHY_TIMING_T *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
- uint32_t cs,dll_off;
-
- cs = ((pPHY_Reg->PGCR>>18) & 0xF);
- dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
- ddr_copy((uint32_t *)&(pPHY_Reg->MR[0]), (uint32_t*)&(p_publ_timing->mr[0]), 4);
- if((DATA(mem_type) == DDR3) || (DATA(mem_type) == DDR2))
- {
- if(DATA(ddr_freq)>DDR3_DDR2_DLL_DISABLE_FREQ)
- {
- if(dll_off) // off -> on
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1]))); //DLL enable
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET)); //DLL reset
- ddr_delayus(2); //at least 200 DDR cycle
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
- }
- else // on -> on
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
- }
- }
- else
- {
- pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE)); //DLL disable
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
- }
- ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
- }
- else if(DATA(mem_type) == LPDDR2)
- {
- ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
- ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
- ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
- }
- else //mDDR
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
- }
- return 0;
-}
-
-static void __sramfunc ddr_update_odt(void)
-{
- uint32_t cs,tmp;
-
- //adjust DRV and ODT
- if((DATA(mem_type) == DDR3) || (DATA(mem_type) == DDR2))
- {
- if(DATA(ddr_freq) <= DDR3_DDR2_ODT_DISABLE_FREQ)
- {
- pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
- pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
- pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
- }
- }
- else
- {
- pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9); //dynamic RTT enable
- pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
- pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
- }
- }
- }
- else
- {
- pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9); //dynamic RTT disable
- pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
- if(!(pDDR_Reg->PPCFG & 1))
- {
- pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
- pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
- }
- }
- if(DATA(mem_type) == LPDDR2)
- {
- tmp = GET_LPDDR2_DS_ODT(); //DS=34ohm,ODT=171ohm
- }
- else
- {
- tmp = GET_DDR3_DS_ODT(); //DS=34ohm,ODT=171ohm
- }
- cs = ((pPHY_Reg->PGCR>>18) & 0xF);
- if(cs > 1)
- {
- pPHY_Reg->ZQ1CR[0] = tmp;
- dsb();
- }
- pPHY_Reg->ZQ0CR[0] = tmp;
- dsb();
-}
-
-void PIE_FUNC(ddr_adjust_config)(void *arg)
-{
- uint32 value = (uint32)arg;
-
- //enter config state
- ddr_move_to_Config_state();
-
- //set data training address
- pPHY_Reg->DTAR = value;
-
- //set auto power down idle
- pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
-
- //CKDV=00
- pPHY_Reg->PGCR &= ~(0x3<<12);
-
- //enable the hardware low-power interface
- pDDR_Reg->SCFG.b.hw_low_power_en = 1;
-
- if(pDDR_Reg->PPCFG & 1)
- {
- pPHY_Reg->DATX8[2].DXGCR &= ~(1); //disable byte
- pPHY_Reg->DATX8[3].DXGCR &= ~(1);
- pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000; //disable DLL
- pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
- }
-
- ddr_update_odt();
-
- //enter access state
- ddr_move_to_Access_state();
-}
-EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
-
-static void ddr_adjust_config(uint32_t dram_type)
-{
- uint32 value;
- u32 i;
- volatile u32 n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
-
- //get data training address before idle port
- value = ddr_get_datatraing_addr();
-
- /** 1. Make sure there is no host access */
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- isb();
-
- for(i=0;i<SRAM_SIZE/4096;i++)
- {
- n=temp[1024*i];
- barrier();
- }
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->RIDR;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= pPMU_Reg->PMU_WAKEUP_CFG[0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
- n= READ_GRF_REG();
- dsb();
-
- call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
- (void *)value,
- rockchip_sram_stack);
-}
-
-static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
-{
- PHY_TIMING_T *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
- uint32 cs;
-
- ddr_move_to_Config_state();
- pDDR_Reg->TZQCSI = 0;
- if((nMHz<=DDR3_DDR2_DLL_DISABLE_FREQ) && ((DATA(mem_type) == DDR3) || (DATA(mem_type) == DDR2))) // DLL disable
- {
- cs = ((pPHY_Reg->PGCR>>18) & 0xF);
- pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));
- }
- ddr_move_to_Lowpower_state();
-
- ddr_set_dll_bypass(0); //dll bypass
- SET_DDRPHY_CLKGATE(1); //disable DDR PHY clock
- ddr_delayus(1);
-}
-
-static void __sramfunc ddr_selfrefresh_exit(void)
-{
- uint32 n;
-
- SET_DDRPHY_CLKGATE(0); //enable DDR PHY clock
- dsb();
- ddr_set_dll_bypass(DATA(ddr_freq));
- ddr_reset_dll();
- //ddr_delayus(10); //wait DLL lock
-
- ddr_move_to_Config_state();
- ddr_update_timing();
- ddr_update_mr();
- ddr_update_odt();
- n = ddr_data_training();
- ddr_move_to_Access_state();
- if(n!=0)
- {
- sram_printascii("DTT failed!\n");
- }
-}
-
-#if defined(CONFIG_ARCH_RK3066B)
-static __sramdata uint32_t data8_dqstr[25][4];
-static __sramdata uint32_t min_ddr_freq,dqstr_flag=false;
-
-int ddr_get_datatraing_value_3168(bool end_flag,uint32_t dqstr_value,uint32_t min_freq)
-{
- if(end_flag == true)
- {
- dqstr_flag = true; //complete learn data training value flag
- min_ddr_freq = min_freq;
- return 0;
- }
-
- data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
- data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
- data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
- data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
-
- ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
- clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
- data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
- return 0;
-}
-
-static void __sramfunc ddr_set_pll_enter_3168(uint32_t freq_slew)
-{
- uint32_t value_1u,value_100n;
- ddr_move_to_Config_state();
-
- if(freq_slew == 1)
- {
- value_100n = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
- value_1u = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
- DATA(ddr_reg).pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
- DATA(ddr_reg).pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
- ddr_update_timing();
- ddr_update_mr();
- DATA(ddr_reg).pctl.pctl_timing.togcnt100n = value_100n;
- DATA(ddr_reg).pctl.pctl_timing.togcnt1u = value_1u;
- }
- else
- {
- pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
- pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
- }
-
- pDDR_Reg->TZQCSI = 0;
- ddr_move_to_Lowpower_state();
-
- ddr_set_dll_bypass(0); //dll bypass
- SET_DDRPHY_CLKGATE(1); //disable DDR PHY clock
- dsb();
-}
-
-void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32_t dqstr_value)
-{
- SET_DDRPHY_CLKGATE(0); //enable DDR PHY clock
- dsb();
- ddr_set_dll_bypass(DATA(ddr_freq));
- ddr_reset_dll();
-
- if(dqstr_flag==true)
- {
- pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
- pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
- pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
- pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
- }
-
- ddr_update_odt();
- ddr_move_to_Config_state();
- if(freq_slew == 1)
- {
- pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
- pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
- pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl.pctl_timing.tzqcsi;
- }
- else
- {
- ddr_update_timing();
- ddr_update_mr();
- }
- ddr_data_training();
- ddr_move_to_Access_state();
-}
-#endif
-
-/* Make sure ddr_SRE_2_SRX paramter less than 4 */
-static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32_t freq_slew,uint32_t dqstr_value)
-{
- /** 2. ddr enter self-refresh mode or precharge power-down mode */
- idle_port();
-#if defined(CONFIG_ARCH_RK3066B)
- ddr_set_pll_enter_3168(freq_slew);
-#else
- ddr_selfrefresh_enter(freq);
-#endif
-
- /** 3. change frequence */
- FUNC(ddr_set_pll)(freq,1);
- DATA(ddr_freq) = freq;
-
- /** 5. Issues a Mode Exit command */
-#if defined(CONFIG_ARCH_RK3066B)
- ddr_set_pll_exit_3168(freq_slew,dqstr_value);
-#else
- ddr_selfrefresh_exit();
-#endif
- deidle_port();
- dsb();
-}
-
-struct ddr_change_freq_sram_param {
- uint32_t arm_freq;
- uint32_t freq;
- uint32_t freq_slew;
- uint32_t dqstr_value;
-};
-
-void PIE_FUNC(ddr_change_freq_sram)(void *arg)
-{
- struct ddr_change_freq_sram_param *param = arg;
- loops_per_us = LPJ_100MHZ * param->arm_freq / 1000000;
- /* Make sure ddr_SRE_2_SRX paramter less than 4 */
- ddr_SRE_2_SRX(param->freq, param->freq_slew, param->dqstr_value);
-}
-EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
-
-static noinline uint32_t ddr_change_freq_sram(uint32_t nMHz , struct ddr_freq_t ddr_freq_t)
-{
- register uint32_t freq;
- register uint32_t freq_slew=0;
- register uint32_t dqstr_value=0;
- unsigned long flags;
- struct ddr_change_freq_sram_param param;
- volatile u32 n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
- u32 i;
-
-#if defined(CONFIG_ARCH_RK3066B)
- if(dqstr_flag==true)
- {
- dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
- freq_slew = (nMHz>ddr_freq)? 1 : 0;
- }
-#endif
-
- freq=p_ddr_set_pll(nMHz,0);
-
- ddr_get_parameter(freq);
-
- /** 1. Make sure there is no host access */
- local_irq_save(flags);
- local_fiq_disable();
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- isb();
-
-#if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
- if(ddr_freq_t.screen_ft_us > 0)
- {
- ddr_freq_t.t1 = cpu_clock(0);
- ddr_freq_t.t2 = (u32)(ddr_freq_t.t1 - ddr_freq_t.t0); //ns
-
- //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
- if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe))
- {
- freq = 0;
- goto end;
- }
- else
- {
- rk_fb_poll_wait_frame_complete();
- }
- }
-#endif
- for(i=0;i<SRAM_SIZE/4096;i++)
- {
- n=temp[1024*i];
- barrier();
- }
-
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->RIDR;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= pPMU_Reg->PMU_WAKEUP_CFG[0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
- n= READ_GRF_REG();
- dsb();
-
- param.arm_freq = ddr_get_pll_freq(APLL);
- param.freq = freq;
- param.freq_slew = freq_slew;
- param.dqstr_value = dqstr_value;
- call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
- ¶m,
- rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
-
-#if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
-end:
-#endif
- local_fiq_enable();
- local_irq_restore(flags);
- return freq;
-}
-
-#if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
-static uint32_t ddr_change_freq_gpll_dpll(uint32_t nMHz)
-{
- uint32_t gpll_freq,gpll_div;
- struct ddr_freq_t ddr_freq_t;
- ddr_freq_t.screen_ft_us = 0;
-
- if(true == ddr_rk3188_dpll_is_good)
- {
- gpllvaluel = ddr_get_pll_freq(GPLL);
-
- if((200 < gpllvaluel) ||( gpllvaluel <1600)) //GPLL:200MHz~1600MHz
- {
- gpll_div = (gpllvaluel+nMHz-1)/nMHz;
- if( gpllvaluel > 800) //800-1600MHz /4:200MHz-400MHz
- {
- gpll_freq = gpllvaluel/4;
- gpll_div = 4;
- }
- else if( gpllvaluel > 400) //400-800MHz /2:200MHz-400MHz
- {
- gpll_freq = gpllvaluel/2;
- gpll_div = 2;
- }
- else //200-400MHz /1:200MHz-400MHz
- {
- gpll_freq = gpllvaluel;
- gpll_div = 1;
- }
-
- *p_ddr_select_gpll_div=gpll_div; //select GPLL
- ddr_change_freq_sram(gpll_freq,ddr_freq_t);
- *p_ddr_select_gpll_div=0;
-
- p_ddr_set_pll(nMHz,0); //count DPLL
- p_ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
- }
- else
- {
- ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
- }
- }
-
- return ddr_change_freq_sram(nMHz,ddr_freq_t);
-
-}
-#endif
-
-/*****************************************
-if rk3188 DPLL is bad,use GPLL
- GPLL DDR_CLCOK
-1000MHz-2000MHz 4:250MHz-500MHz
-800MHz-1000MHz 4:200MHz-250MHz 2:400MHz-500MHz
-500MHz-800MHz 2:250MHz-400MHz
-200MHz-500MHz 1:200MHz-500MHz
-******************************************/
-#if 0
-static noinline uint32_t ddr_change_freq(uint32_t nMHz)
-{
- struct ddr_freq_t ddr_freq_t;
- ddr_freq_t.screen_ft_us = 0;
-
-#if defined(ENABLE_DDR_CLCOK_GPLL_PATH) && (defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X))
- return ddr_change_freq_gpll_dpll(nMHz);
-#else
- return ddr_change_freq_sram(nMHz,ddr_freq_t);
-#endif
-}
-#endif
-
-bool DEFINE_PIE_DATA(cpu_pause[NR_CPUS]);
-volatile bool *p_cpu_pause;
-static inline bool is_cpu0_paused(unsigned int cpu) { smp_rmb(); return DATA(cpu_pause)[0]; }
-static inline void set_cpuX_paused(unsigned int cpu, bool pause) { DATA(cpu_pause)[cpu] = pause; smp_wmb(); }
-static inline bool is_cpuX_paused(unsigned int cpu) { smp_rmb(); return p_cpu_pause[cpu]; }
-static inline void set_cpu0_paused(bool pause) { p_cpu_pause[0] = pause; smp_wmb();}
-
-#define MAX_TIMEOUT (16000000UL << 6) //>0.64s
-
-/* Do not use stack, safe on SMP */
-void PIE_FUNC(_pause_cpu)(void *arg)
-{
- unsigned int cpu = (unsigned int)arg;
-
- set_cpuX_paused(cpu, true);
- while (is_cpu0_paused(cpu));
- set_cpuX_paused(cpu, false);
-}
-
-static void pause_cpu(void *info)
-{
- unsigned int cpu = raw_smp_processor_id();
-
- call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(_pause_cpu)),
- (void *)cpu,
- rockchip_sram_stack-(cpu-1)*PAUSE_CPU_STACK_SIZE);
-}
-
-static void wait_cpu(void *info)
-{
-}
-
-static int __ddr_change_freq(uint32_t nMHz, struct ddr_freq_t ddr_freq_t)
-{
- u32 timeout = MAX_TIMEOUT;
- unsigned int cpu;
- unsigned int this_cpu = smp_processor_id();
- int ret = 0;
-
- cpu_maps_update_begin();
- local_bh_disable();
- set_cpu0_paused(true);
- smp_call_function((smp_call_func_t)pause_cpu, NULL, 0);
-
- for_each_online_cpu(cpu) {
- if (cpu == this_cpu)
- continue;
- while (!is_cpuX_paused(cpu) && --timeout);
- if (timeout == 0) {
- pr_err("pause cpu %d timeout\n", cpu);
- goto out;
- }
- }
-
- ret = ddr_change_freq_sram(nMHz, ddr_freq_t);
-
-out:
- set_cpu0_paused(false);
- local_bh_enable();
- smp_call_function(wait_cpu, NULL, true);
- cpu_maps_update_done();
-
- return ret;
-}
-
-static int _ddr_change_freq(uint32_t nMHz)
-{
- struct ddr_freq_t ddr_freq_t;
- //int test_count=0;
-
- ddr_freq_t.screen_ft_us = 0;
- ddr_freq_t.t0 = 0;
- ddr_freq_t.t1 = 0;
-#if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
- do
- {
- if(rk_fb_poll_wait_frame_complete() == true)
- {
- ddr_freq_t.t0 = cpu_clock(0);
- ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
-
- test_count++;
- if(test_count > 10) //test 10 times
- {
- ddr_freq_t.screen_ft_us = 0xfefefefe;
- dprintk(DEBUG_DDR,"%s:test_count exceed maximum!\n",__func__);
- }
- dprintk(DEBUG_VERBOSE,"%s:test_count=%d\n",__func__,test_count);
- usleep_range(ddr_freq_t.screen_ft_us-test_count*1000,ddr_freq_t.screen_ft_us-test_count*1000);
-
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- }
- }while(__ddr_change_freq(nMHz, ddr_freq_t)==0);
-#else
- return __ddr_change_freq(nMHz, ddr_freq_t);
-#endif
-}
-
-static long _ddr_round_rate(uint32_t nMHz)
-{
- return p_ddr_set_pll(nMHz, 0);
-}
-
-static void _ddr_set_auto_self_refresh(bool en)
-{
- //set auto self-refresh idle
- *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
-}
-
-#define PERI_ACLK_DIV_MASK 0x1f
-#define PERI_ACLK_DIV_OFF 0
-
-#define PERI_HCLK_DIV_MASK 0x3
-#define PERI_HCLK_DIV_OFF 8
-
-#define PERI_PCLK_DIV_MASK 0x3
-#define PERI_PCLK_DIV_OFF 12
-#if 0
-static __sramdata u32 cru_sel32_sram;
-static void __sramfunc ddr_suspend(void)
-{
- u32 i;
- volatile u32 n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
- int pll_id;
-
- pll_id=GET_DDR_PLL_SRC();
- /** 1. Make sure there is no host access */
- flush_cache_all();
- outer_flush_all();
- //flush_tlb_all();
-
- for(i=0;i<SRAM_SIZE/4096;i++)
- {
- n=temp[1024*i];
- barrier();
- }
-
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->RIDR;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= pPMU_Reg->PMU_WAKEUP_CFG[0];
- n= *(volatile uint32_t *)SysSrv_DdrConf;
- n= READ_GRF_REG();
- dsb();
-
- ddr_selfrefresh_enter(0);
-
- SET_PLL_MODE(pll_id, 0); //PLL slow-mode
- dsb();
- ddr_delayus(1);
- SET_PLL_PD(pll_id, 1); //PLL power-down
- dsb();
- ddr_delayus(1);
- if(pll_id==GPLL)
- {
- cru_sel32_sram= pCRU_Reg->CRU_CLKSEL_CON[10];
-
- pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
- | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
- |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
- }
- pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29))); //CKOE
-}
-
-static void __sramfunc ddr_resume(void)
-{
- int delay=1000;
- int pll_id;
-
- pll_id=GET_DDR_PLL_SRC();
- pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29)); //CKOE
- dsb();
-
- if(pll_id==GPLL)
- pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
-
- SET_PLL_PD(pll_id, 0); //PLL no power-down
- dsb();
- while (delay > 0)
- {
- ddr_delayus(1);
- if (GET_DPLL_LOCK_STATUS())
- break;
- delay--;
- }
-
- SET_PLL_MODE(pll_id, 1); //PLL normal
- dsb();
-
- ddr_selfrefresh_exit();
-}
-#endif
-
-//»ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
-static uint32 ddr_get_cap(void)
-{
- uint32 cap;
-
- if(DDR_SYS_REG())
- {
- cap = (1 << (READ_CS0_ROW_INFO()+READ_COL_INFO()+READ_BK_INFO()+READ_BW_INFO()));
- if(READ_CS_INFO()>1)
- {
- cap +=(1 << (READ_CS1_ROW_INFO()+READ_COL_INFO()+READ_BK_INFO()+READ_BW_INFO()));
- }
- }
- else
- {
- cap = (1 << (ddr_get_row()+ddr_get_col()+ddr_get_bank()+ddr_get_bw()))*ddr_get_cs();
- }
-
- return cap;
-}
-
-#if 0
-static void ddr_reg_save(void)
-{
- //PCTLR
- p_ddr_reg->pctl.SCFG = pDDR_Reg->SCFG.d32;
- p_ddr_reg->pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
- p_ddr_reg->pctl.MCFG1 = pDDR_Reg->MCFG1;
- p_ddr_reg->pctl.MCFG = pDDR_Reg->MCFG;
- p_ddr_reg->pctl.pctl_timing.ddrFreq = ddr_freq;
- p_ddr_reg->pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
- p_ddr_reg->pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
- p_ddr_reg->pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
- p_ddr_reg->pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
- p_ddr_reg->pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
- p_ddr_reg->pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
- p_ddr_reg->pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
- p_ddr_reg->pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
- p_ddr_reg->pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
- p_ddr_reg->pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
- p_ddr_reg->pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
- p_ddr_reg->pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
- p_ddr_reg->pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
- p_ddr_reg->pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
- p_ddr_reg->pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
-
- p_ddr_reg->pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
- p_ddr_reg->pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
- p_ddr_reg->pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
- p_ddr_reg->pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
- p_ddr_reg->pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
- p_ddr_reg->pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
- p_ddr_reg->pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
- p_ddr_reg->pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
- p_ddr_reg->pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
-
- //PUBL
- p_ddr_reg->publ.PIR = pPHY_Reg->PIR;
- p_ddr_reg->publ.PGCR = pPHY_Reg->PGCR;
- p_ddr_reg->publ.DLLGCR = pPHY_Reg->DLLGCR;
- p_ddr_reg->publ.ACDLLCR = pPHY_Reg->ACDLLCR;
- p_ddr_reg->publ.PTR[0] = pPHY_Reg->PTR[0];
- p_ddr_reg->publ.PTR[1] = pPHY_Reg->PTR[1];
- p_ddr_reg->publ.PTR[2] = pPHY_Reg->PTR[2];
- p_ddr_reg->publ.ACIOCR = pPHY_Reg->ACIOCR;
- p_ddr_reg->publ.DXCCR = pPHY_Reg->DXCCR;
- p_ddr_reg->publ.DSGCR = pPHY_Reg->DSGCR;
- p_ddr_reg->publ.DCR = pPHY_Reg->DCR.d32;
- p_ddr_reg->publ.ODTCR = pPHY_Reg->ODTCR;
- p_ddr_reg->publ.DTAR = pPHY_Reg->DTAR;
- p_ddr_reg->publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
- p_ddr_reg->publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
-
- p_ddr_reg->publ.DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
- p_ddr_reg->publ.DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
- p_ddr_reg->publ.DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
- p_ddr_reg->publ.DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
-
- p_ddr_reg->publ.DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
- p_ddr_reg->publ.DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
- p_ddr_reg->publ.DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
- p_ddr_reg->publ.DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
-
- p_ddr_reg->publ.DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
- p_ddr_reg->publ.DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
- p_ddr_reg->publ.DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
- p_ddr_reg->publ.DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
-
- p_ddr_reg->publ.DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
- p_ddr_reg->publ.DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
- p_ddr_reg->publ.DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
- p_ddr_reg->publ.DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
-
- //NOC
- p_ddr_reg->DdrConf = *(volatile uint32_t *)SysSrv_DdrConf;
- p_ddr_reg->DdrMode = *(volatile uint32_t *)SysSrv_DdrMode;
- p_ddr_reg->ReadLatency = *(volatile uint32_t *)SysSrv_ReadLatency;
-}
-
-static __attribute__((aligned(4))) __sramdata uint32 ddr_reg_resume[] =
-{
-#include "ddr_reg_resume.inc"
-};
-#endif
-
-static int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
-{
- volatile uint32_t value = 0;
- uint32_t die=1;
- uint32_t gsr,dqstr;
- struct clk *clk;
-
- ddr_print("version 1.00 20140228 \n");
-
- p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
- p_ddr_select_gpll_div = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div));
- p_mem_type = kern_to_pie(rockchip_pie_chunk, &DATA(mem_type));
- p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
- p_cpu_pause = kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
-
- *p_mem_type = pPHY_Reg->DCR.b.DDRMD;
- ddr_speed_bin = dram_speed_bin;
-
- if(freq != 0)
- ddr_freq = freq;
- else
- ddr_freq = clk_get_rate(clk_get(NULL, "ddr"))/1000000;
- *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq)) = ddr_freq;
-
- *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
- ddr_soc_is_rk3188_plus = GET_3188_PLUS_STATUS();
- if(true == ddr_soc_is_rk3188_plus)
- {
- ddr_print("A\n");
- }
- *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_soc_is_rk3188_plus)) = ddr_soc_is_rk3188_plus;
- ddr_rk3188_dpll_is_good = GET_DPLL_STATUS();
- if(false == ddr_rk3188_dpll_is_good)
- {
- ddr_print("T\n");
- }
- *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_rk3188_dpll_is_good)) = ddr_rk3188_dpll_is_good;
- switch(*p_mem_type)
- {
- case DDR3:
- if(DDR_SYS_REG())
- {
- die = (8<<READ_BW_INFO())/(8<<READ_DIE_BW_INFO());
- }
- else
- {
- if(pDDR_Reg->PPCFG & 1)
- {
- die=1;
- }
- else
- {
- die = 2;
- }
- }
- ddr_print("DDR3 Device\n");
- break;
- case LPDDR2:
- ddr_print("LPDDR2 Device\n");
- break;
- case DDR2:
- ddr_print("DDR2 Device\n");
- break;
- case DDR:
- ddr_print("DDR Device\n");
- break;
- default:
- ddr_print("LPDDR Device\n");
- break;
- }
- //get capability per chip, not total size, used for calculate tRFC
- ddr_capability_per_die = ddr_get_cap()/(ddr_get_cs()*die);
- ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
- ddr_get_bw()*16,\
- ddr_get_col(), \
- (0x1<<(ddr_get_bank())), \
- ddr_get_row(), \
- ddr_get_cs(), \
- (ddr_get_cap()>>20));
- ddr_adjust_config(*p_mem_type);
-
- clk = clk_get(NULL, "clk_ddr");
- if (IS_ERR(clk)) {
- ddr_print("failed to get ddr clk\n");
- clk = NULL;
- }
- if(ddr_rk3188_dpll_is_good == true)
- {
- if(freq != 0)
- value = clk_set_rate(clk, 1000*1000*freq);
- else
- value = clk_set_rate(clk, clk_get_rate(clk));
- }
- ddr_print("init success!!! freq=%luMHz\n", clk ? clk_get_rate(clk)/1000000 : freq);
-
- for(value=0;value<4;value++)
- {
- gsr = pPHY_Reg->DATX8[value].DXGSR[0];
- dqstr = pPHY_Reg->DATX8[value].DXDQSTR;
- ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=0x%x, DGSL=%d extra clock, DGPS=%d\n", \
- (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), ((((dqstr>>12)&0x3)+1)*90));
- }
- ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
- (pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
- (pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
- pPHY_Reg->ZQ0SR[1]&0x3,\
- (pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
- (pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
- (pPHY_Reg->ZQ0SR[1]>>6)&0x3);
- ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", pPHY_Reg->ZQ0SR[0]&0x1F, (pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
- ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
-
- return 0;
-}
-
+++ /dev/null
-/*
- * arch/arm/mach-rk2928/ddr.c-- for ddr3&ddr2
- *
- * Function Driver for DDR controller
- *
- * Copyright (C) 2012 Fuzhou Rockchip Electronics Co.,Ltd
- * Author:
- * hcy@rock-chips.com
- * yk@rock-chips.com
- * typ@rock-chips.com
- *
- * v1.00
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <linux/cpu.h>
-#include <dt-bindings/clock/ddr.h>
-#include <linux/rockchip/cpu_axi.h>
-#include <linux/rockchip/cru.h>
-#include <linux/rk_fb.h>
-
-
-typedef uint32_t uint32 ;
-
-
-#define DDR3_DDR2_DLL_DISABLE_FREQ (300) // ¿ÅÁ£dll disableµÄƵÂÊ
-#define DDR3_DDR2_ODT_DISABLE_FREQ (333) //¿ÅÁ£odt disableµÄƵÂÊ
-#define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
-#define PD_IDLE (0x40) //unit:DDR clk cycle, and 0 for disable auto power-down
-#define PHY_ODT_DISABLE_FREQ (333) //¶¨ÒåÖ÷¿Ø¶Ëodt disableµÄƵÂÊ
-#define PHY_DLL_DISABLE_FREQ (266) //¶¨ÒåÖ÷¿Ø¶Ëdll bypassµÄƵÂÊ
-
-#define ddr_print(x...) printk( "DDR DEBUG: " x )
-
-#define SRAM_CODE_OFFSET rockchip_sram_virt
-#define SRAM_SIZE rockchip_sram_size
-
-
-/***********************************
- * DDR3 define
- ***********************************/
-//mr0 for ddr3
-#define DDR3_BL8 (0)
-#define DDR3_BC4_8 (1)
-#define DDR3_BC4 (2)
-#define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
-#define DDR3_WR(n) (((n)&0x7)<<9)
-#define DDR3_DLL_RESET (1<<8)
-#define DDR3_DLL_DeRESET (0<<8)
-
-//mr1 for ddr3
-#define DDR3_DLL_ENABLE (0)
-#define DDR3_DLL_DISABLE (1)
-#define DDR3_MR1_AL(n) (((n)&0x7)<<3)
-
-#define DDR3_DS_40 (0)
-#define DDR3_DS_34 (1<<1)
-#define DDR3_Rtt_Nom_DIS (0)
-#define DDR3_Rtt_Nom_60 (1<<2)
-#define DDR3_Rtt_Nom_120 (1<<6)
-#define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
-
-//mr2 for ddr3
-#define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
-#define DDR3_Rtt_WR_DIS (0)
-#define DDR3_Rtt_WR_60 (1<<9)
-#define DDR3_Rtt_WR_120 (2<<9)
-
-#define DDR_PLL_REFDIV (1)
-#define FBDIV(n) ((0xFFF<<16) | (n&0xfff))
-#define REFDIV(n) ((0x3F<<16) | (n&0x3f))
-#define POSTDIV1(n) ((0x7<<(12+16)) | ((n&0x7)<<12))
-#define POSTDIV2(n) ((0x7<<(6+16)) | ((n&0x7)<<6))
-
-#define PLL_LOCK_STATUS (0x1<<10)
- //CRU Registers
-typedef volatile struct tagCRU_STRUCT
-{
- uint32 CRU_PLL_CON[4][4];
- uint32 CRU_MODE_CON;
- uint32 CRU_CLKSEL_CON[35];
- uint32 CRU_CLKGATE_CON[10];
- uint32 reserved1[2];
- uint32 CRU_GLB_SRST_FST_VALUE;
- uint32 CRU_GLB_SRST_SND_VALUE;
- uint32 reserved2[2];
- uint32 CRU_SOFTRST_CON[9];
- uint32 CRU_MISC_CON;
- uint32 reserved3[2];
- uint32 CRU_GLB_CNT_TH;
- uint32 CRU_SDMMC_CON[2];
- uint32 CRU_SDIO_CON[2];
- uint32 CRU_EMMC_CON[2];
- uint32 reserved4;
- uint32 CRU_RST_ST;
- uint32 reserved5[(0x1f0-0x164)/4];
- uint32 CRU_PLL_MASK_CON;
-} CRU_REG, *pCRU_REG;
-
-typedef struct tagGPIO_LH
-{
- uint32 GPIOL;
- uint32 GPIOH;
-}GPIO_LH_T;
-
-typedef struct tagGPIO_IOMUX
-{
- uint32 GPIOA_IOMUX;
- uint32 GPIOB_IOMUX;
- uint32 GPIOC_IOMUX;
- uint32 GPIOD_IOMUX;
-}GPIO_IOMUX_T;
-
-/********************************
-GRF ¼Ä´æÆ÷ÖÐGRF_OS_REG1 ´æddr rank£¬typeµÈÐÅÏ¢
-GRF_SOC_CON2¼Ä´æÆ÷ÖпØÖÆc_sysreqÐźÅÏòpctl·¢ËͽøÈëlow power ÇëÇó
-GRF_DDRC_STAT ¿É²éѯpctlÊÇ·ñ½ÓÊÜÇëÇó ½øÈëlow power
-********************************/
-//REG FILE registers
-//GRF_SOC_STATUS0
-#define sys_pwr_idle (1<<27)
-#define gpu_pwr_idle (1<<26)
-#define vpu_pwr_idle (1<<25)
-#define vio_pwr_idle (1<<24)
-#define peri_pwr_idle (1<<23)
-#define core_pwr_idle (1<<22)
-//GRF_SOC_CON2
-#define core_pwr_idlereq (13)
-#define peri_pwr_idlereq (12)
-#define vio_pwr_idlereq (11)
-#define vpu_pwr_idlereq (10)
-#define gpu_pwr_idlereq (9)
-#define sys_pwr_idlereq (8)
-
-typedef volatile struct tagREG_FILE
-{
- uint32 reserved0[(0xa8-0x0)/4];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[3]; // 0x00a8
- uint32 reserved1[(0x100-0xd8)/4];
- uint32 GRF_GPIO_DS; //0x100
- uint32 reserved2[(0x118-0x104)/4];
- GPIO_LH_T GRF_GPIO_PULL[3]; // 0x118
- uint32 reserved3[(0x140-0x130)/4];
- uint32 GRF_SOC_CON[3]; // 0x140
- uint32 GRF_SOC_STATUS0;
- //uint32 GRF_LVDS_CON0;
- uint32 reserved4; //0x150
- uint32 GRF_SOC_CON3;
- uint32 reserved5[(0x15c-0x158)/4];
- uint32 GRF_DMAC_CON[3]; //0x15c
- uint32 reserved6[(0x17c-0x168)/4];
- uint32 GRF_UOC0_CON5; //0x17c
- uint32 reserved7[(0x190-0x180)/4];
- uint32 GRF_UOC1_CON4; //0x190
- uint32 GRF_UOC1_COM5;
- uint32 reserved8;
- uint32 GRF_DDRC_STAT;
- uint32 GRF_UOC_CON6;
- uint32 GRF_SOC_STATUS1;
- uint32 GRF_CPU_CON[4];
- uint32 reserved9[(0x1c0-0x1b8)/4];
- uint32 GRF_CPU_STATUS[2];
- uint32 GRF_OS_REG[8];
- uint32 reserved10[(0x200-0x1e8)/4];
- uint32 GRF_DLL_CON[4]; //0X200
- uint32 GRF_DLL_STATUS[4];
- //uint32 reserved10[(0x220-0x214)/4];
- uint32 GRF_DFI_WRNUM; //0X220
- uint32 GRF_DFI_RDNUM;
- uint32 GRF_DFI_ACTNUM;
- uint32 GRF_DFI_TIMERVAL;
- uint32 GRF_NIF_FIFO[4];
- uint32 reserved11[(0x280-0x240)/4];
- uint32 GRF_USBPHY0_CON[8];
- uint32 GRF_USBPHY1_CON[8];
- uint32 reserved12[(0x300-0x2c0)/4];
- uint32 GRF_CHIP_TAG;
- uint32 GRF_SDMMC_DET_CNT;
-} REG_FILE, *pREG_FILE;
-
-//SCTL
-#define INIT_STATE (0)
-#define CFG_STATE (1)
-#define GO_STATE (2)
-#define SLEEP_STATE (3)
-#define WAKEUP_STATE (4)
-
-//STAT
-#define Init_mem (0)
-#define Config (1)
-#define Config_req (2)
-#define Access (3)
-#define Access_req (4)
-#define Low_power (5)
-#define Low_power_entry_req (6)
-#define Low_power_exit_req (7)
-
-//MCFG
-#define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
-#define pd_idle(n) ((n)<<8)
-#define mddr_en (2<<22)
-#define lpddr2_en (3<<22)
-#define ddr2_en (0<<5)
-#define ddr3_en (1<<5)
-#define lpddr2_s2 (0<<6)
-#define lpddr2_s4 (1<<6)
-#define mddr_lpddr2_bl_2 (0<<20)
-#define mddr_lpddr2_bl_4 (1<<20)
-#define mddr_lpddr2_bl_8 (2<<20)
-#define mddr_lpddr2_bl_16 (3<<20)
-#define ddr2_ddr3_bl_4 (0)
-#define ddr2_ddr3_bl_8 (1)
-#define tfaw_cfg(n) (((n)-4)<<18)
-#define pd_exit_slow (0<<17)
-#define pd_exit_fast (1<<17)
-#define pd_type(n) ((n)<<16)
-#define two_t_en(n) ((n)<<3)
-#define bl8int_en(n) ((n)<<2)
-#define cke_or_en(n) ((n)<<1)
-
-//POWCTL
-#define power_up_start (1<<0)
-
-//POWSTAT
-#define power_up_done (1<<0)
-
-//DFISTSTAT0
-#define dfi_init_complete (1<<0)
-
-//CMDTSTAT
-#define cmd_tstat (1<<0)
-
-//CMDTSTATEN
-#define cmd_tstat_en (1<<1)
-
-//MCMD
-#define Deselect_cmd (0)
-#define PREA_cmd (1)
-#define REF_cmd (2)
-#define MRS_cmd (3)
-#define ZQCS_cmd (4)
-#define ZQCL_cmd (5)
-#define RSTL_cmd (6)
-#define MRR_cmd (8)
-#define DPDE_cmd (9)
-
-#define lpddr2_op(n) ((n)<<12)
-#define lpddr2_ma(n) ((n)<<4)
-
-#define bank_addr(n) ((n)<<17)
-#define cmd_addr(n) ((n)<<4)
-
-#define start_cmd (1u<<31)
-
-typedef union STAT_Tag
-{
- uint32 d32;
- struct
- {
- unsigned ctl_stat : 3;
- unsigned reserved3 : 1;
- unsigned lp_trig : 3;
- unsigned reserved7_31 : 25;
- }b;
-}STAT_T;
-
-typedef union SCFG_Tag
-{
- uint32 d32;
- struct
- {
- unsigned hw_low_power_en : 1;
- unsigned reserved1_5 : 5;
- unsigned nfifo_nif1_dis : 1;
- unsigned reserved7 : 1;
- unsigned bbflags_timing : 4;
- unsigned reserved12_31 : 20;
- } b;
-}SCFG_T;
-
-/* DDR Controller register struct */
-typedef volatile struct DDR_REG_Tag
-{
- //Operational State, Control, and Status Registers
- SCFG_T SCFG; //State Configuration Register
- volatile uint32 SCTL; //State Control Register
- STAT_T STAT; //State Status Register
- volatile uint32 INTRSTAT; //Interrupt Status Register
- uint32 reserved0[(0x40-0x10)/4];
- //Initailization Control and Status Registers
- volatile uint32 MCMD; //Memory Command Register
- volatile uint32 POWCTL; //Power Up Control Registers
- volatile uint32 POWSTAT; //Power Up Status Register
- volatile uint32 CMDTSTAT; //Command Timing Status Register
- volatile uint32 CMDTSTATEN; //Command Timing Status Enable Register
- uint32 reserved1[(0x60-0x54)/4];
- volatile uint32 MRRCFG0; //MRR Configuration 0 Register
- volatile uint32 MRRSTAT0; //MRR Status 0 Register
- volatile uint32 MRRSTAT1; //MRR Status 1 Register
- uint32 reserved2[(0x7c-0x6c)/4];
- //Memory Control and Status Registers
- volatile uint32 MCFG1; //Memory Configuration 1 Register
- volatile uint32 MCFG; //Memory Configuration Register
- volatile uint32 PPCFG; //Partially Populated Memories Configuration Register
- volatile uint32 MSTAT; //Memory Status Register
- volatile uint32 LPDDR2ZQCFG; //LPDDR2 ZQ Configuration Register
- uint32 reserved3;
- //DTU Control and Status Registers
- volatile uint32 DTUPDES; //DTU Status Register
- volatile uint32 DTUNA; //DTU Number of Random Addresses Created Register
- volatile uint32 DTUNE; //DTU Number of Errors Register
- volatile uint32 DTUPRD0; //DTU Parallel Read 0
- volatile uint32 DTUPRD1; //DTU Parallel Read 1
- volatile uint32 DTUPRD2; //DTU Parallel Read 2
- volatile uint32 DTUPRD3; //DTU Parallel Read 3
- volatile uint32 DTUAWDT; //DTU Address Width
- uint32 reserved4[(0xc0-0xb4)/4];
- //Memory Timing Registers
- volatile uint32 TOGCNT1U; //Toggle Counter 1U Register
- volatile uint32 TINIT; //t_init Timing Register
- volatile uint32 TRSTH; //Reset High Time Register
- volatile uint32 TOGCNT100N; //Toggle Counter 100N Register
- volatile uint32 TREFI; //t_refi Timing Register
- volatile uint32 TMRD; //t_mrd Timing Register
- volatile uint32 TRFC; //t_rfc Timing Register
- volatile uint32 TRP; //t_rp Timing Register
- volatile uint32 TRTW; //t_rtw Timing Register
- volatile uint32 TAL; //AL Latency Register
- volatile uint32 TCL; //CL Timing Register
- volatile uint32 TCWL; //CWL Register
- volatile uint32 TRAS; //t_ras Timing Register
- volatile uint32 TRC; //t_rc Timing Register
- volatile uint32 TRCD; //t_rcd Timing Register
- volatile uint32 TRRD; //t_rrd Timing Register
- volatile uint32 TRTP; //t_rtp Timing Register
- volatile uint32 TWR; //t_wr Timing Register
- volatile uint32 TWTR; //t_wtr Timing Register
- volatile uint32 TEXSR; //t_exsr Timing Register
- volatile uint32 TXP; //t_xp Timing Register
- volatile uint32 TXPDLL; //t_xpdll Timing Register
- volatile uint32 TZQCS; //t_zqcs Timing Register
- volatile uint32 TZQCSI; //t_zqcsi Timing Register
- volatile uint32 TDQS; //t_dqs Timing Register
- volatile uint32 TCKSRE; //t_cksre Timing Register
- volatile uint32 TCKSRX; //t_cksrx Timing Register
- volatile uint32 TCKE; //t_cke Timing Register
- volatile uint32 TMOD; //t_mod Timing Register
- volatile uint32 TRSTL; //Reset Low Timing Register
- volatile uint32 TZQCL; //t_zqcl Timing Register
- volatile uint32 TMRR; //t_mrr Timing Register
- volatile uint32 TCKESR; //t_ckesr Timing Register
- volatile uint32 TDPD; //t_dpd Timing Register
- uint32 reserved5[(0x180-0x148)/4];
- //ECC Configuration, Control, and Status Registers
- volatile uint32 ECCCFG; //ECC Configuration Register
- volatile uint32 ECCTST; //ECC Test Register
- volatile uint32 ECCCLR; //ECC Clear Register
- volatile uint32 ECCLOG; //ECC Log Register
- uint32 reserved6[(0x200-0x190)/4];
- //DTU Control and Status Registers
- volatile uint32 DTUWACTL; //DTU Write Address Control Register
- volatile uint32 DTURACTL; //DTU Read Address Control Register
- volatile uint32 DTUCFG; //DTU Configuration Control Register
- volatile uint32 DTUECTL; //DTU Execute Control Register
- volatile uint32 DTUWD0; //DTU Write Data 0
- volatile uint32 DTUWD1; //DTU Write Data 1
- volatile uint32 DTUWD2; //DTU Write Data 2
- volatile uint32 DTUWD3; //DTU Write Data 3
- volatile uint32 DTUWDM; //DTU Write Data Mask
- volatile uint32 DTURD0; //DTU Read Data 0
- volatile uint32 DTURD1; //DTU Read Data 1
- volatile uint32 DTURD2; //DTU Read Data 2
- volatile uint32 DTURD3; //DTU Read Data 3
- volatile uint32 DTULFSRWD; //DTU LFSR Seed for Write Data Generation
- volatile uint32 DTULFSRRD; //DTU LFSR Seed for Read Data Generation
- volatile uint32 DTUEAF; //DTU Error Address FIFO
- //DFI Control Registers
- volatile uint32 DFITCTRLDELAY; //DFI tctrl_delay Register
- volatile uint32 DFIODTCFG; //DFI ODT Configuration Register
- volatile uint32 DFIODTCFG1; //DFI ODT Configuration 1 Register
- volatile uint32 DFIODTRANKMAP; //DFI ODT Rank Mapping Register
- //DFI Write Data Registers
- volatile uint32 DFITPHYWRDATA; //DFI tphy_wrdata Register
- volatile uint32 DFITPHYWRLAT; //DFI tphy_wrlat Register
- uint32 reserved7[(0x260-0x258)/4];
- volatile uint32 DFITRDDATAEN; //DFI trddata_en Register
- volatile uint32 DFITPHYRDLAT; //DFI tphy_rddata Register
- uint32 reserved8[(0x270-0x268)/4];
- //DFI Update Registers
- volatile uint32 DFITPHYUPDTYPE0; //DFI tphyupd_type0 Register
- volatile uint32 DFITPHYUPDTYPE1; //DFI tphyupd_type1 Register
- volatile uint32 DFITPHYUPDTYPE2; //DFI tphyupd_type2 Register
- volatile uint32 DFITPHYUPDTYPE3; //DFI tphyupd_type3 Register
- volatile uint32 DFITCTRLUPDMIN; //DFI tctrlupd_min Register
- volatile uint32 DFITCTRLUPDMAX; //DFI tctrlupd_max Register
- volatile uint32 DFITCTRLUPDDLY; //DFI tctrlupd_dly Register
- uint32 reserved9;
- volatile uint32 DFIUPDCFG; //DFI Update Configuration Register
- volatile uint32 DFITREFMSKI; //DFI Masked Refresh Interval Register
- volatile uint32 DFITCTRLUPDI; //DFI tctrlupd_interval Register
- uint32 reserved10[(0x2ac-0x29c)/4];
- volatile uint32 DFITRCFG0; //DFI Training Configuration 0 Register
- volatile uint32 DFITRSTAT0; //DFI Training Status 0 Register
- volatile uint32 DFITRWRLVLEN; //DFI Training dfi_wrlvl_en Register
- volatile uint32 DFITRRDLVLEN; //DFI Training dfi_rdlvl_en Register
- volatile uint32 DFITRRDLVLGATEEN; //DFI Training dfi_rdlvl_gate_en Register
- //DFI Status Registers
- volatile uint32 DFISTSTAT0; //DFI Status Status 0 Register
- volatile uint32 DFISTCFG0; //DFI Status Configuration 0 Register
- volatile uint32 DFISTCFG1; //DFI Status configuration 1 Register
- uint32 reserved11;
- volatile uint32 DFITDRAMCLKEN; //DFI tdram_clk_enalbe Register
- volatile uint32 DFITDRAMCLKDIS; //DFI tdram_clk_disalbe Register
- volatile uint32 DFISTCFG2; //DFI Status configuration 2 Register
- volatile uint32 DFISTPARCLR; //DFI Status Parity Clear Register
- volatile uint32 DFISTPARLOG; //DFI Status Parity Log Register
- uint32 reserved12[(0x2f0-0x2e4)/4];
- //DFI Low Power Registers
- volatile uint32 DFILPCFG0; //DFI Low Power Configuration 0 Register
- uint32 reserved13[(0x300-0x2f4)/4];
- //DFI Training 2 Registers
- volatile uint32 DFITRWRLVLRESP0; //DFI Training dif_wrlvl_resp Status 0 Register
- volatile uint32 DFITRWRLVLRESP1; //DFI Training dif_wrlvl_resp Status 1 Register
- volatile uint32 DFITRWRLVLRESP2; //DFI Training dif_wrlvl_resp Status 2 Register
- volatile uint32 DFITRRDLVLRESP0; //DFI Training dif_rdlvl_resp Status 0 Register
- volatile uint32 DFITRRDLVLRESP1; //DFI Training dif_rdlvl_resp Status 1 Register
- volatile uint32 DFITRRDLVLRESP2; //DFI Training dif_rdlvl_resp Status 2 Register
- volatile uint32 DFITRWRLVLDELAY0; //DFI Training dif_wrlvl_delay Configuration 0 Register
- volatile uint32 DFITRWRLVLDELAY1; //DFI Training dif_wrlvl_delay Configuration 1 Register
- volatile uint32 DFITRWRLVLDELAY2; //DFI Training dif_wrlvl_delay Configuration 2 Register
- volatile uint32 DFITRRDLVLDELAY0; //DFI Training dif_rdlvl_delay Configuration 0 Register
- volatile uint32 DFITRRDLVLDELAY1; //DFI Training dif_rdlvl_delay Configuration 1 Register
- volatile uint32 DFITRRDLVLDELAY2; //DFI Training dif_rdlvl_delay Configuration 2 Register
- volatile uint32 DFITRRDLVLGATEDELAY0; //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
- volatile uint32 DFITRRDLVLGATEDELAY1; //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
- volatile uint32 DFITRRDLVLGATEDELAY2; //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
- volatile uint32 DFITRCMD; //DFI Training Command Register
- uint32 reserved14[(0x3f8-0x340)/4];
- //IP Status Registers
- volatile uint32 IPVR; //IP Version Register
- volatile uint32 IPTR; //IP Type Register
-}DDR_REG_T, *pDDR_REG_T;
-
-//PHY_REG2
-#define PHY_AUTO_CALIBRATION (1<<0)
-#define PHY_SW_CALIBRATION (1<<1)
-#define PHY_MEM_TYPE (6)
-
-//PHY_REG22,25,26,27,28
-#define PHY_RON_DISABLE (0)
-#define PHY_RON_309ohm (1)
-#define PHY_RON_155ohm (2)
-#define PHY_RON_103ohm (3)
-#define PHY_RON_77ohm (4)
-#define PHY_RON_63ohm (5)
-#define PHY_RON_52ohm (6)
-#define PHY_RON_45ohm (7)
-//#define PHY_RON_77ohm (8)
-#define PHY_RON_62ohm (9)
-//#define PHY_RON_52ohm (10)
-#define PHY_RON_44ohm (11)
-#define PHY_RON_39ohm (12)
-#define PHY_RON_34ohm (13)
-#define PHY_RON_31ohm (14)
-#define PHY_RON_28ohm (15)
-
-#define PHY_RTT_DISABLE (0)
-#define PHY_RTT_816ohm (1)
-#define PHY_RTT_431ohm (2)
-#define PHY_RTT_287ohm (3)
-#define PHY_RTT_216ohm (4)
-#define PHY_RTT_172ohm (5)
-#define PHY_RTT_145ohm (6)
-#define PHY_RTT_124ohm (7)
-#define PHY_RTT_215ohm (8)
-//#define PHY_RTT_172ohm (9)
-#define PHY_RTT_144ohm (10)
-#define PHY_RTT_123ohm (11)
-#define PHY_RTT_108ohm (12)
-#define PHY_RTT_96ohm (13)
-#define PHY_RTT_86ohm (14)
-#define PHY_RTT_78ohm (15)
-
-/* DDR PHY register struct */
-typedef volatile struct DDRPHY_REG_Tag
-{
- volatile uint32 PHY_REG1; //PHY soft reset Register
- volatile uint32 PHY_REG3; //Burst type select Register
- volatile uint32 PHY_REG2; //PHY DQS squelch calibration Register
- uint32 reserved1[(0x38-0x0a)/4];
- volatile uint32 PHY_REG4a; //CL,AL set register
- volatile uint32 PHY_REG4b; //dqs gata delay select bypass mode register
- uint32 reserved2[(0x54-0x40)/4];
- volatile uint32 PHY_REG16; //
- uint32 reserved3[(0x5c-0x58)/4];
- volatile uint32 PHY_REG18; //0x5c
- volatile uint32 PHY_REG19;
- uint32 reserved4[(0x68-0x64)/4];
- volatile uint32 PHY_REG21; //0x68
- uint32 reserved5[(0x70-0x6c)/4];
- volatile uint32 PHY_REG22; //0x70
- uint32 reserved6[(0x80-0x74)/4];
- volatile uint32 PHY_REG25; //0x80
- volatile uint32 PHY_REG26;
- volatile uint32 PHY_REG27;
- volatile uint32 PHY_REG28;
- uint32 reserved7[(0xd4-0x90)/4];
- volatile uint32 PHY_REG6; //0xd4
- volatile uint32 PHY_REG7;
- uint32 reserved8[(0xe0-0xdc)/4];
- volatile uint32 PHY_REG8; //0xe0
- volatile uint32 PHY_REG0e4; //use for DQS ODT off
- uint32 reserved9[(0x114-0xe8)/4];
- volatile uint32 PHY_REG9; //0x114
- volatile uint32 PHY_REG10;
- uint32 reserved10[(0x120-0x11c)/4];
- volatile uint32 PHY_REG11; //0x120
- volatile uint32 PHY_REG124; //use for DQS ODT off
- uint32 reserved11[(0x1c0-0x128)/4];
- volatile uint32 PHY_REG29; //0x1c0
- uint32 reserved12[(0x264-0x1c4)/4];
- volatile uint32 PHY_REG264; //use for phy soft reset
- uint32 reserved13[(0x2b0-0x268)/4];
- volatile uint32 PHY_REG2a; //0x2b0
- uint32 reserved14[(0x2c4-0x2b4)/4];
-// volatile uint32 PHY_TX_DeSkew[24]; //0x2c4-0x320
- volatile uint32 PHY_REG30;
- volatile uint32 PHY_REG31;
- volatile uint32 PHY_REG32;
- volatile uint32 PHY_REG33;
- volatile uint32 PHY_REG34;
- volatile uint32 PHY_REG35;
- volatile uint32 PHY_REG36;
- volatile uint32 PHY_REG37;
- volatile uint32 PHY_REG38;
- volatile uint32 PHY_REG39;
- volatile uint32 PHY_REG40;
- volatile uint32 PHY_REG41;
- volatile uint32 PHY_REG42;
- volatile uint32 PHY_REG43;
- volatile uint32 PHY_REG44;
- volatile uint32 PHY_REG45;
- volatile uint32 PHY_REG46;
- volatile uint32 PHY_REG47;
- volatile uint32 PHY_REG48;
- volatile uint32 PHY_REG49;
- volatile uint32 PHY_REG50;
- volatile uint32 PHY_REG51;
- volatile uint32 PHY_REG52;
- volatile uint32 PHY_REG53;
- uint32 reserved15[(0x328-0x324)/4];
-// volatile uint32 PHY_RX_DeSkew[11]; //0x328-0x350
- volatile uint32 PHY_REG54;
- volatile uint32 PHY_REG55;
- volatile uint32 PHY_REG56;
- volatile uint32 PHY_REG57;
- volatile uint32 PHY_REG58;
- volatile uint32 PHY_REG59;
- volatile uint32 PHY_REG5a;
- volatile uint32 PHY_REG5b;
- volatile uint32 PHY_REG5c;
- volatile uint32 PHY_REG5d;
- volatile uint32 PHY_REG5e;
- uint32 reserved16[(0x3c4-0x354)/4];
- volatile uint32 PHY_REG5f; //0x3c4
- uint32 reserved17[(0x3e0-0x3c8)/4];
- volatile uint32 PHY_REG60;
- volatile uint32 PHY_REG61;
- volatile uint32 PHY_REG62;
-}DDRPHY_REG_T, *pDDRPHY_REG_T;
-
-#define pCRU_Reg ((pCRU_REG)RK_CRU_VIRT)
-#define pGRF_Reg ((pREG_FILE)RK_GRF_VIRT)
-#define pDDR_Reg ((pDDR_REG_T)RK_DDR_VIRT)
-#define pPHY_Reg ((pDDRPHY_REG_T)(RK_DDR_VIRT+RK3036_DDR_PCTL_SIZE))
-#define SysSrv_DdrTiming (RK_CPU_AXI_BUS_VIRT+0xc)
-#define READ_CS_INFO() ((((pGRF_Reg->GRF_OS_REG[1])>>11)&0x1)+1)
-#define READ_COL_INFO() (9+(((pGRF_Reg->GRF_OS_REG[1])>>9)&0x3))
-#define READ_BK_INFO() (3-(((pGRF_Reg->GRF_OS_REG[1])>>8)&0x1))
-#define READ_CS0_ROW_INFO() (13+(((pGRF_Reg->GRF_OS_REG[1])>>6)&0x3))
-#define READ_CS1_ROW_INFO() (13+(((pGRF_Reg->GRF_OS_REG[1])>>4)&0x3))
-#define READ_BW_INFO() (2>>(((pGRF_Reg->GRF_OS_REG[1])&0xc)>>2)) //´úÂëÖÐ 0->8bit 1->16bit 2->32bit ÓëgrfÖж¨ÒåÏà·´
-#define READ_DIE_BW_INFO() (2>>((pGRF_Reg->GRF_OS_REG[1])&0x3))
-
-typedef enum PLL_ID_Tag
-{
- APLL=0,
- DPLL,
- CPLL,
- GPLL,
- PLL_MAX
-}PLL_ID;
-
-typedef enum DRAM_TYPE_Tag
-{
- LPDDR = 0,
- DDR,
- DDR2,
- DDR3,
- LPDDR2_S2,
- LPDDR2_S4,
-
- DRAM_MAX
-}DRAM_TYPE;
-
-struct ddr_freq_t {
- unsigned long screen_ft_us;
- unsigned long long t0;
- unsigned long long t1;
- unsigned long t2;
-};
-
-
-typedef struct PCTRL_TIMING_Tag
-{
- uint32 ddrFreq;
- //Memory Timing Registers
- uint32 togcnt1u; //Toggle Counter 1U Register
- uint32 tinit; //t_init Timing Register
- uint32 trsth; //Reset High Time Register
- uint32 togcnt100n; //Toggle Counter 100N Register
- uint32 trefi; //t_refi Timing Register
- uint32 tmrd; //t_mrd Timing Register
- uint32 trfc; //t_rfc Timing Register
- uint32 trp; //t_rp Timing Register
- uint32 trtw; //t_rtw Timing Register
- uint32 tal; //AL Latency Register
- uint32 tcl; //CL Timing Register
- uint32 tcwl; //CWL Register
- uint32 tras; //t_ras Timing Register
- uint32 trc; //t_rc Timing Register
- uint32 trcd; //t_rcd Timing Register
- uint32 trrd; //t_rrd Timing Register
- uint32 trtp; //t_rtp Timing Register
- uint32 twr; //t_wr Timing Register
- uint32 twtr; //t_wtr Timing Register
- uint32 texsr; //t_exsr Timing Register
- uint32 txp; //t_xp Timing Register
- uint32 txpdll; //t_xpdll Timing Register
- uint32 tzqcs; //t_zqcs Timing Register
- uint32 tzqcsi; //t_zqcsi Timing Register
- uint32 tdqs; //t_dqs Timing Register
- uint32 tcksre; //t_cksre Timing Register
- uint32 tcksrx; //t_cksrx Timing Register
- uint32 tcke; //t_cke Timing Register
- uint32 tmod; //t_mod Timing Register
- uint32 trstl; //Reset Low Timing Register
- uint32 tzqcl; //t_zqcl Timing Register
- uint32 tmrr; //t_mrr Timing Register
- uint32 tckesr; //t_ckesr Timing Register
- uint32 tdpd; //t_dpd Timing Register
-}PCTL_TIMING_T;
-
-struct ddr_change_freq_sram_param {
- uint32 freq;
- uint32 freq_slew;
-};
-
-
-typedef union NOC_TIMING_Tag
-{
- uint32 d32;
- struct
- {
- unsigned ActToAct : 6;
- unsigned RdToMiss : 6;
- unsigned WrToMiss : 6;
- unsigned BurstLen : 3;
- unsigned RdToWr : 5;
- unsigned WrToRd : 5;
- unsigned BwRatio : 1;
- } b;
-}NOC_TIMING_T;
-
-typedef struct BACKUP_REG_Tag
-{
- PCTL_TIMING_T pctl_timing;
- NOC_TIMING_T noc_timing;
- uint32 ddrMR[4];
- uint32 mem_type;
- uint32 ddr_speed_bin;
- uint32 ddr_capability_per_die;
-}BACKUP_REG_T;
-
-BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
-static BACKUP_REG_T *p_ddr_reg;
-
-uint32 DEFINE_PIE_DATA(ddr_freq);
-static uint32 *p_ddr_freq;
-uint32 DEFINE_PIE_DATA(ddr_sr_idle);
-uint32 DEFINE_PIE_DATA(ddr_dll_status); // ¼Ç¼ddr dllµÄ״̬£¬ÔÚselfrefresh exitʱѡÔñÊÇ·ñ½øÐÐdll reset
-
-
-
-static uint32_t ddr3_cl_cwl[22][4]={
-/* 0~330 330~400 400~533 speed
-* tCK >3 2.5~3 1.875~2.5 1.875~1.5
-* cl<<16, cwl cl<<16, cwl cl<<16, cwl */
- {((5<<16)|5), ((5<<16)|5), 0 , 0}, //DDR3_800D
- {((5<<16)|5), ((6<<16)|5), 0 , 0}, //DDR3_800E
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), 0}, //DDR3_1066E
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6), 0}, //DDR3_1066F
- {((5<<16)|5), ((6<<16)|5), ((8<<16)|6), 0}, //DDR3_1066G
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1333F
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((8<<16)|7)}, //DDR3_1333G
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1333H
- {((5<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)}, //DDR3_1333J
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_1600G
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_1600H
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1600J
- {((5<<16)|5), ((6<<16)|5), ((7<<16)|6), ((10<<16)|7)}, //DDR3_1600K
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_1866J
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((8<<16)|7)}, //DDR3_1866K
- {((6<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_1866L
- {((6<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)}, //DDR3_1866M
-
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((7<<16)|7)}, //DDR3_2133K
- {((5<<16)|5), ((5<<16)|5), ((6<<16)|6), ((8<<16)|7)}, //DDR3_2133L
- {((5<<16)|5), ((5<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_2133M
- {((6<<16)|5), ((6<<16)|5), ((7<<16)|6), ((9<<16)|7)}, //DDR3_2133N
-
- {((6<<16)|5), ((6<<16)|5), ((8<<16)|6), ((10<<16)|7)} //DDR3_DEFAULT
-
-};
-static uint32_t ddr3_tRC_tFAW[22]={
-/** tRC tFAW */
- ((50<<16)|50), //DDR3_800D
- ((53<<16)|50), //DDR3_800E
-
- ((49<<16)|50), //DDR3_1066E
- ((51<<16)|50), //DDR3_1066F
- ((53<<16)|50), //DDR3_1066G
-
- ((47<<16)|45), //DDR3_1333F
- ((48<<16)|45), //DDR3_1333G
- ((50<<16)|45), //DDR3_1333H
- ((51<<16)|45), //DDR3_1333J
-
- ((45<<16)|40), //DDR3_1600G
- ((47<<16)|40), //DDR3_1600H
- ((48<<16)|40), //DDR3_1600J
- ((49<<16)|40), //DDR3_1600K
-
- ((45<<16)|35), //DDR3_1866J
- ((46<<16)|35), //DDR3_1866K
- ((47<<16)|35), //DDR3_1866L
- ((48<<16)|35), //DDR3_1866M
-
- ((44<<16)|35), //DDR3_2133K
- ((45<<16)|35), //DDR3_2133L
- ((46<<16)|35), //DDR3_2133M
- ((47<<16)|35), //DDR3_2133N
-
- ((53<<16)|50) //DDR3_DEFAULT
-};
-
-
-/****************************************************************************
-Internal sram us delay function
-Cpu highest frequency is 1.6 GHz
-1 cycle = 1/1.6 ns
-1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
-*****************************************************************************/
-//__sramdata volatile uint32 loops_per_us;
-volatile uint32 DEFINE_PIE_DATA(loops_per_us);
-#define LPJ_100MHZ 999456UL
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_delayus(uint32_t us)
-Desc : ddr ÑÓʱº¯Êý
-Params : uint32_t us --ÑÓʱʱ¼ä
-Return : void
-Notes : loops_per_us Ϊȫ¾Ö±äÁ¿ ÐèÒª¸ù¾Ýarm freq¶ø¶¨
-----------------------------------------------------------------------*/
-static void __sramfunc ddr_delayus(uint32 us)
-{
- do
- {
- volatile unsigned int i = (DATA(loops_per_us)*us);
- if (i < 7) i = 7;
- barrier();
- asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
- } while (0);
-}
-
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
-Desc : ddr ¿½±´¼Ä´æÆ÷º¯Êý
-Params : pDest ->Ä¿±ê¼Ä´æÆ÷Ê×µØÖ·
- pSrc ->Ô´±ê¼Ä´æÆ÷Ê×µØÖ·
- words ->¿½±´³¤¶È
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-
-static __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
-{
- uint32 i;
-
- for(i=0; i<words; i++)
- {
- pDest[i] = pSrc[i];
- }
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_move_to_Lowpower_state(void)
-Desc : pctl ½øÈë lowpower state
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static __sramfunc void ddr_move_to_Lowpower_state(void)
-{
- volatile uint32 value;
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if(value == Low_power)
- {
- break;
- }
- switch(value)
- {
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- case Config:
- pDDR_Reg->SCTL = GO_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- case Access:
- pDDR_Reg->SCTL = SLEEP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
- break;
- default: //Transitional state
- break;
- }
- }
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_move_to_Access_state(void)
-Desc : pctl ½øÈë Access state
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static __sramfunc void ddr_move_to_Access_state(void)
-{
- volatile uint32 value;
-
- //set auto self-refresh idle
- //pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)| DATA(ddr_sr_idle) | (1<<31);
- pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)| 0 | (1<<31);
-
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if((value == Access)
- || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
- {
- break;
- }
- switch(value)
- {
- case Low_power:
- pDDR_Reg->SCTL = WAKEUP_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Access);
- break;
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- while((pDDR_Reg->STAT.b.ctl_stat) != Config);
- case Config:
- pDDR_Reg->SCTL = GO_STATE;
- dsb();
- while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
- || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
- break;
- default: //Transitional state
- break;
- }
- }
- pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_move_to_Config_state(void)
-Desc : pctl ½øÈë config state
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static __sramfunc void ddr_move_to_Config_state(void)
-{
- volatile uint32 value;
- pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
- while(1)
- {
- value = pDDR_Reg->STAT.b.ctl_stat;
- if(value == Config)
- {
- break;
- }
- switch(value)
- {
- case Low_power:
- pDDR_Reg->SCTL = WAKEUP_STATE;
- dsb();
- case Access:
- case Init_mem:
- pDDR_Reg->SCTL = CFG_STATE;
- dsb();
- break;
- default: //Transitional state
- break;
- }
- }
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
-Desc : ͨ¹ýд pctl MCMD¼Ä´æÆ÷Ïòddr·¢ËÍÃüÁî
-Params : rank ->ddr rank Êý
- cmd ->·¢ËÍÃüÁîÀàÐÍ
- arg ->·¢Ë͵ÄÊý¾Ý
-Return : void
-Notes : arg°üÀ¨bank_addrºÍcmd_addr
-----------------------------------------------------------------------*/
-static void __sramfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
-{
- pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
- dsb();
- while(pDDR_Reg->MCMD & start_cmd);
-}
-
-__sramdata uint32 copy_data[8]={0xffffffff,0x00000000,0x55555555,0xAAAAAAAA,
- 0xEEEEEEEE,0x11111111,0x22222222,0xDDDDDDDD};/**/
-EXPORT_PIE_SYMBOL(copy_data[8]);
-static uint32 * p_copy_data;
-
-/*----------------------------------------------------------------------
-Name : uint32_t __sramlocalfunc ddr_data_training(void)
-Desc : ¶Ôddr×ödata training
-Params : void
-Return : void
-Notes : ûÓÐ×ödata trainingУÑé
-----------------------------------------------------------------------*/
-static uint32_t __sramfunc ddr_data_training(void)
-{
- uint32 value;
- value = pDDR_Reg->TREFI;
- pDDR_Reg->TREFI = 0;
- // trigger DTT
- pPHY_Reg->PHY_REG2 = ((pPHY_Reg->PHY_REG2 & (~0x1)) | PHY_AUTO_CALIBRATION);
- // wait echo byte DTDONE
- dsb();
-// ddr_delayus(1);
- // stop DTT
- while((pPHY_Reg->PHY_REG62 & 0x3)!=0x3);
- pPHY_Reg->PHY_REG2 = (pPHY_Reg->PHY_REG2 & (~0x1));
- // send some auto refresh to complement the lost while DTT
- ddr_send_command(3, REF_cmd, 0);
- ddr_send_command(3, REF_cmd, 0);
- ddr_send_command(3, REF_cmd, 0);
- ddr_send_command(3, REF_cmd, 0);
-
- // resume auto refresh
- pDDR_Reg->TREFI = value;
-
- return(0);
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
-Desc : ÉèÖÃPHY dll ¹¤×÷ģʽ
-Params : freq -> ddr¹¤×÷ƵÂÊ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static void __sramfunc ddr_set_dll_bypass(uint32 freq)
-{
- if(freq <= PHY_DLL_DISABLE_FREQ)
- {
- pPHY_Reg->PHY_REG2a = 0x1F; //set cmd,left right dll bypass
- pPHY_Reg->PHY_REG19 = 0x08; //cmd slave dll
- pPHY_Reg->PHY_REG6 = 0x18; //left TX DQ DLL
- pPHY_Reg->PHY_REG7 = 0x00; //left TX DQS DLL
- pPHY_Reg->PHY_REG9 = 0x18; //right TX DQ DLL
- pPHY_Reg->PHY_REG10 = 0x00; //right TX DQS DLL
-
- }
- else
- {
- pPHY_Reg->PHY_REG2a = 0x03; //set cmd,left right dll bypass
- pPHY_Reg->PHY_REG19 = 0x08; //cmd slave dll
- pPHY_Reg->PHY_REG6 = 0x0c; //left TX DQ DLL
- pPHY_Reg->PHY_REG7 = 0x00; //left TX DQS DLL
- pPHY_Reg->PHY_REG9 = 0x0c; //right TX DQ DLL
- pPHY_Reg->PHY_REG10 = 0x00; //right TX DQS DLL
- }
- dsb();
- //ÆäËûÓëdllÏà¹ØµÄ¼Ä´æÆ÷ÓÐ:REG8(RX DQS),REG11(RX DQS),REG18(CMD),REG21(CK) ±£³ÖĬÈÏÖµ
-}
-
-static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id) //APLL-1;CPLL-2;DPLL-3;GPLL-4
-{
- uint32 ret = 0;
-
- // freq = (fin*fbdiv/(refdiv * postdiv1 * postdiv2))
- if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&1) == 1) // DPLL Normal mode
- ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0xfff)) // NF = 2*(CLKF+1)
- /((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0x3f)
- *((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>12)&0x7)*((pCRU_Reg->CRU_PLL_CON[pll_id][1]>>6)&0x7)); // OD = 2^CLKOD
- else
- ret = 24;
-
- return ret;
-}
-
-static __sramdata uint32 clkFbDiv;
-static __sramdata uint32 clkPostDiv1;
-static __sramdata uint32 clkPostDiv2;
-
-/*****************************************
-REFDIV FBDIV POSTDIV1/POSTDIV2 FOUTPOSTDIV freq Step FOUTPOSRDIV finally use
-==================================================================================================================
-1 17 - 66 4 100MHz - 400MHz 6MHz 200MHz <= 300MHz <= 150MHz
-1 17 - 66 3 133MHz - 533MHz 8MHz
-1 17 - 66 2 200MHz - 800MHz 12MHz 300MHz <= 600MHz 150MHz <= 300MHz
-1 17 - 66 1 400MHz - 1600MHz 24MHz 600MHz <= 1200MHz 300MHz <= 600MHz
-******************************************/
-//for minimum jitter operation, the highest VCO and FREF frequencies should be used.
-/*----------------------------------------------------------------------
-Name : uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
-Desc : ÉèÖÃddr pll
-Params : nMHZ -> ddr¹¤×÷ƵÂÊ
- set ->0»ñÈ¡ÉèÖõÄƵÂÊÐÅÏ¢
- 1ÉèÖÃddr pll
-Return : ÉèÖõÄƵÂÊÖµ
-Notes : ÔÚ±äƵʱÐèÒªÏÈset=0µ÷ÓÃÒ»´Îddr_set_pll£¬ÔÙset=1 µ÷ÓÃddr_set_pll
-----------------------------------------------------------------------*/
-static uint32 __sramfunc ddr_set_pll(uint32 nMHz, uint32 set)
-{
- uint32 ret = 0;
- int delay = 1000;
- uint32 pll_id=1; //DPLL
-
- if(nMHz == 24)
- {
- ret = 24;
- goto out;
- }
- if(!set)
- {
- if(nMHz <= 150) //ʵ¼ÊÊä³öƵÂÊ<300
- {
- clkPostDiv1 = 6;
- }
- else if(nMHz <=200)
- {
- clkPostDiv1 = 4;
- }
- else if(nMHz <= 300)
- {
- clkPostDiv1 = 3;
- }
- else if(nMHz <=450)
- {
- clkPostDiv1 = 2;
- }
- else
- {
- clkPostDiv1 = 1;
- }
- clkPostDiv2 = 1;
- clkFbDiv = (nMHz * 2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2)/24;//×îºóËÍÈëddrµÄÊÇÔÙ¾¹ý2·ÖƵ
- ret = (24 * clkFbDiv)/(2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2);
- }
- else
- {
- pCRU_Reg->CRU_MODE_CON = (0x1<<((pll_id*4) + 16)) | (0x0<<(pll_id*4)); //PLL slow-mode
-
- pCRU_Reg->CRU_PLL_CON[pll_id][0] = FBDIV(clkFbDiv) | POSTDIV1(clkPostDiv1);
- pCRU_Reg->CRU_PLL_CON[pll_id][1] = REFDIV(DDR_PLL_REFDIV) | POSTDIV2(clkPostDiv2) | (0x10001<<12);//interger mode
-
- ddr_delayus(1);
-
- while (delay > 0)
- {
- ddr_delayus(1);
- if (pCRU_Reg->CRU_PLL_CON[pll_id][1] & (PLL_LOCK_STATUS)) // wait for pll locked
- break;
- delay--;
- }
-
- pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3<<16) | 0x0); //clk_ddr_src:clk_ddrphy = 1:1
- pCRU_Reg->CRU_MODE_CON = (0x1<<((pll_id*4) + 16)) | (0x1<<(pll_id*4)); //PLL normal
- }
-out:
- return ret;
-}
-
-uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
-{
- return ddr_set_pll(nMHz,set);
-}
-EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
-
-/*----------------------------------------------------------------------
-Name : uint32_t ddr_get_parameter(uint32_t nMHz)
-Desc : »ñÈ¡ÅäÖòÎÊý
-Params : nMHZ -> ddr¹¤×÷ƵÂÊ
-Return : 0 ³É¹¦
- -1 ʧ°Ü
- -4 ƵÂÊÖµ³¬¹ý¿ÅÁ£×î´óƵÂÊ
-Notes :
-----------------------------------------------------------------------*/
-static uint32 ddr_get_parameter(uint32 nMHz)
-{
- uint32_t tmp;
- uint32_t ret = 0;
- uint32_t al;
- uint32_t bl;
- uint32_t cl;
- uint32_t cwl;
- PCTL_TIMING_T *p_pctl_timing = &(p_ddr_reg->pctl_timing);
- NOC_TIMING_T *p_noc_timing=&(p_ddr_reg->noc_timing);
-
- p_pctl_timing->togcnt1u = nMHz;
- p_pctl_timing->togcnt100n = nMHz/10;
- p_pctl_timing->tinit = 200;
- p_pctl_timing->trsth = 500;
-
- if(p_ddr_reg->mem_type == DDR3)
- {
- if(p_ddr_reg->ddr_speed_bin > DDR3_DEFAULT)
- {
- ret = -1;
- goto out;
- }
-
- #define DDR3_tREFI_7_8_us (78)
- #define DDR3_tMRD (4)
- #define DDR3_tRFC_512Mb (90)
- #define DDR3_tRFC_1Gb (110)
- #define DDR3_tRFC_2Gb (160)
- #define DDR3_tRFC_4Gb (300)
- #define DDR3_tRFC_8Gb (350)
- #define DDR3_tRTW (2) //register min valid value
- #define DDR3_tRAS (37)
- #define DDR3_tRRD (10)
- #define DDR3_tRTP (7)
- #define DDR3_tWR (15)
- #define DDR3_tWTR (7)
- #define DDR3_tXP (7)
- #define DDR3_tXPDLL (24)
- #define DDR3_tZQCS (80)
- #define DDR3_tZQCSI (10000)
- #define DDR3_tDQS (1)
- #define DDR3_tCKSRE (10)
- #define DDR3_tCKE_400MHz (7)
- #define DDR3_tCKE_533MHz (6)
- #define DDR3_tMOD (15)
- #define DDR3_tRSTL (100)
- #define DDR3_tZQCL (320)
- #define DDR3_tDLLK (512)
-
- al = 0;
- bl = 8;
- if(nMHz <= 330)
- {
- tmp = 0;
- }
- else if(nMHz<=400)
- {
- tmp = 1;
- }
- else if(nMHz<=533)
- {
- tmp = 2;
- }
- else //666MHz
- {
- tmp = 3;
- }
- if(nMHz < DDR3_DDR2_DLL_DISABLE_FREQ) //when dll bypss cl = cwl = 6;
- {
- cl = 6;
- cwl = 6;
- }
- else
- {
- cl = ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] >> 16;
- cwl = ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] & 0x0ff;
- }
- if(cl == 0)
- {
- ret = -4; //³¬¹ý¿ÅÁ£µÄ×î´óƵÂÊ
- }
- if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
- {
- p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
- }
- else
- {
- p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
- }
- p_ddr_reg->ddrMR[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
- p_ddr_reg->ddrMR[3] = 0;
- /**************************************************
- * PCTL Timing
- **************************************************/
- /*
- * tREFI, average periodic refresh interval, 7.8us
- */
- p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
- /*
- * tMRD, 4 tCK
- */
- p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
- /*
- * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
- */
- if(p_ddr_reg->ddr_capability_per_die <= 0x4000000) // 512Mb 90ns
- {
- tmp = DDR3_tRFC_512Mb;
- }
- else if(p_ddr_reg->ddr_capability_per_die <= 0x8000000) // 1Gb 110ns
- {
- tmp = DDR3_tRFC_1Gb;
- }
- else if(p_ddr_reg->ddr_capability_per_die <= 0x10000000) // 2Gb 160ns
- {
- tmp = DDR3_tRFC_2Gb;
- }
- else if(p_ddr_reg->ddr_capability_per_die <= 0x20000000) // 4Gb 300ns
- {
- tmp = DDR3_tRFC_4Gb;
- }
- else // 8Gb 350ns
- {
- tmp = DDR3_tRFC_8Gb;
- }
- p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
- /*
- * tXSR, =tDLLK=512 tCK
- */
- p_pctl_timing->texsr = DDR3_tDLLK;
- /*
- * tRP=CL
- */
- p_pctl_timing->trp = cl;
- /*
- * WrToMiss=WL*tCK + tWR + tRP + tRCD
- */
- p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
- /*
- * tRC=tRAS+tRP
- */
- p_pctl_timing->trc = ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
- p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
-
- p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
- p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
- p_pctl_timing->tal = al;
- p_pctl_timing->tcl = cl;
- p_pctl_timing->tcwl = cwl;
- /*
- * tRAS, 37.5ns(400MHz) 37.5ns(533MHz)
- */
- p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
- /*
- * tRCD=CL
- */
- p_pctl_timing->trcd = cl;
- /*
- * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
- * max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
- * max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
- *
- */
- tmp = ((DDR3_tRRD*nMHz+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->trrd = (tmp&0xF);
- /*
- * tRTP, max(4 tCK,7.5ns)
- */
- tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->trtp = tmp&0xF;
- /*
- * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
- */
- p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
- /*
- * tWR, 15ns
- */
- tmp = ((DDR3_tWR*nMHz+999)/1000);
- p_pctl_timing->twr = tmp&0x1F;
- if(tmp<9)
- tmp = tmp - 4;
- else
- tmp = tmp>>1;
- p_ddr_reg->ddrMR[0] = DDR3_BL8 | DDR3_CL(cl) | DDR3_WR(tmp);
-
- /*
- * tWTR, max(4 tCK,7.5ns)
- */
- tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 4)
- {
- tmp = 4;
- }
- p_pctl_timing->twtr = tmp&0xF;
- p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
- /*
- * tXP, max(3 tCK, 7.5ns)(<933MHz)
- */
- tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->txp = tmp&0x7;
- /*
- * tXPDLL, max(10 tCK,24ns)
- */
- tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
- if(tmp < 10)
- {
- tmp = 10;
- }
- p_pctl_timing->txpdll = tmp & 0x3F;
- /*
- * tZQCS, max(64 tCK, 80ns)
- */
- tmp = ((DDR3_tZQCS*nMHz+999)/1000);
- if(tmp < 64)
- {
- tmp = 64;
- }
- p_pctl_timing->tzqcs = tmp&0x7F;
- /*
- * tZQCSI,
- */
- p_pctl_timing->tzqcsi = DDR3_tZQCSI;
- /*
- * tDQS,
- */
- p_pctl_timing->tdqs = DDR3_tDQS;
- /*
- * tCKSRE, max(5 tCK, 10ns)
- */
- tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
- if(tmp < 5)
- {
- tmp = 5;
- }
- p_pctl_timing->tcksre = tmp & 0x1F;
- /*
- * tCKSRX, max(5 tCK, 10ns)
- */
- p_pctl_timing->tcksrx = tmp & 0x1F;
- /*
- * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
- */
- if(nMHz>=533)
- {
- tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
- }
- else
- {
- tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
- }
- if(tmp < 3)
- {
- tmp = 3;
- }
- p_pctl_timing->tcke = tmp & 0x7;
- /*
- * tCKESR, =tCKE + 1tCK
- */
- p_pctl_timing->tckesr = (tmp+1)&0xF;
- /*
- * tMOD, max(12 tCK,15ns)
- */
- tmp = ((DDR3_tMOD*nMHz+999)/1000);
- if(tmp < 12)
- {
- tmp = 12;
- }
- p_pctl_timing->tmod = tmp&0x1F;
- /*
- * tRSTL, 100ns
- */
- p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
- /*
- * tZQCL, max(256 tCK, 320ns)
- */
- tmp = ((DDR3_tZQCL*nMHz+999)/1000);
- if(tmp < 256)
- {
- tmp = 256;
- }
- p_pctl_timing->tzqcl = tmp&0x3FF;
- /*
- * tMRR, 0 tCK
- */
- p_pctl_timing->tmrr = 0;
- /*
- * tDPD, 0
- */
- p_pctl_timing->tdpd = 0;
-
- /**************************************************
- * NOC Timing
- **************************************************/
- p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
- }
- else
- {
- ret = -1;
- }
-
-out:
- return ret;
-}
-
-/*----------------------------------------------------------------------
-Name : uint32_t __sramlocalfunc ddr_update_timing(void)
-Desc : ¸üÐÂpctl phy Ïà¹Øtiming¼Ä´æÆ÷
-Params : void
-Return : 0 ³É¹¦
-Notes :
-----------------------------------------------------------------------*/
-static uint32 __sramfunc ddr_update_timing(void)
-{
- PCTL_TIMING_T *p_pctl_timing = &(DATA(ddr_reg).pctl_timing);
- NOC_TIMING_T *p_noc_timing = &(DATA(ddr_reg).noc_timing);
-
- ddr_copy((uint32 *)&(pDDR_Reg->TOGCNT1U), (uint32*)&(p_pctl_timing->togcnt1u), 34);
- pPHY_Reg->PHY_REG3 = (0x12 << 1) | (ddr2_ddr3_bl_8); //0x12Ϊ±£ÁôλµÄĬÈÏÖµ£¬ÒÔĬÈÏÖµ»Øд
- pPHY_Reg->PHY_REG4a = ((p_pctl_timing->tcl << 4) | (p_pctl_timing->tal));
- *(volatile uint32 *)SysSrv_DdrTiming = p_noc_timing->d32;
- // Update PCTL BL
-// if(DATA(ddr_reg).mem_type == DDR3)
- {
- pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
- pDDR_Reg->DFITRDDATAEN = (pDDR_Reg->TAL + pDDR_Reg->TCL)-3; //trdata_en = rl-3
- pDDR_Reg->DFITPHYWRLAT = pDDR_Reg->TCWL-1;
- }
- return 0;
-}
-
-/*----------------------------------------------------------------------
-Name : uint32_t __sramlocalfunc ddr_update_mr(void)
-Desc : ¸üпÅÁ£MR¼Ä´æÆ÷
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static uint32 __sramfunc ddr_update_mr(void)
-{
- uint32 cs;
-
- cs = READ_CS_INFO();
- cs = cs + (1 << cs); //case 0:1rank cs=1; case 1:2rank cs =3;
- if(DATA(ddr_freq) > DDR3_DDR2_DLL_DISABLE_FREQ)
- {
- if(DATA(ddr_dll_status) == DDR3_DLL_DISABLE) // off -> on
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((DATA(ddr_reg).ddrMR[1]))); //DLL enable
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((DATA(ddr_reg).ddrMR[0]))| DDR3_DLL_RESET)); //DLL reset
- ddr_delayus(2); //at least 200 DDR cycle
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
- DATA(ddr_dll_status) = DDR3_DLL_ENABLE;
- }
- else // on -> on
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((DATA(ddr_reg).ddrMR[1])));
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
- }
- }
- else
- {
- ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((DATA(ddr_reg).ddrMR[1])) | DDR3_DLL_DISABLE)); //DLL disable
- ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
- DATA(ddr_dll_status) = DDR3_DLL_DISABLE;
- }
- ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((DATA(ddr_reg).ddrMR[2])));
-
- return 0;
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_update_odt(void)
-Desc : update PHY odt & PHY driver impedance
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static void __sramfunc ddr_update_odt(void)
-{
- uint32 tmp;
-
- //adjust DRV and ODT
- if(DATA(ddr_freq) <= PHY_ODT_DISABLE_FREQ)
- {
- pPHY_Reg->PHY_REG27 = PHY_RTT_DISABLE; //dynamic RTT disable, Left 8bit ODT
- pPHY_Reg->PHY_REG28 = PHY_RTT_DISABLE; //Right 8bit ODT
- pPHY_Reg->PHY_REG0e4 = (0x0E & 0xc)|0x1;//off DQS ODT bit[1:0]=2'b01
- pPHY_Reg->PHY_REG124 = (0x0E & 0xc)|0x1;//off DQS ODT bit[1:0]=2'b01
- }
- else
- {
- pPHY_Reg->PHY_REG27 = ((PHY_RTT_215ohm<<4) | PHY_RTT_215ohm);
- pPHY_Reg->PHY_REG28 = ((PHY_RTT_215ohm<<4) | PHY_RTT_215ohm);
- pPHY_Reg->PHY_REG0e4 = 0x0E; //on DQS ODT default:0x0E
- pPHY_Reg->PHY_REG124 = 0x0E; //on DQS ODT default:0x0E
- }
-
- tmp = ((PHY_RON_45ohm<<4) | PHY_RON_45ohm);
- pPHY_Reg->PHY_REG16 = tmp; //CMD driver strength
- pPHY_Reg->PHY_REG22 = tmp; //CK driver strength
- pPHY_Reg->PHY_REG25 = tmp; //Left 8bit DQ driver strength
- pPHY_Reg->PHY_REG26 = tmp; //Right 8bit DQ driver strength
- dsb();
-}
-
-/*----------------------------------------------------------------------
-Name : __sramfunc void ddr_adjust_config(uint32_t dram_type)
-Desc :
-Params : dram_type ->¿ÅÁ£ÀàÐÍ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-#if 0
-__sramfunc void ddr_adjust_config(uint32_t dram_type)
-{
-// uint32 value;
- unsigned long save_sp;
- uint32 i;
- volatile uint32 n;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
-
- //get data training address before idle port
-// value = ddr_get_datatraing_addr(); //Inno PHY ²»ÐèÒªtraining address
-
- /** 1. Make sure there is no host access */
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- DDR_SAVE_SP(save_sp);
-
- for(i=0;i<2;i++) //8KB SRAM
- {
- n=temp[1024*i];
- barrier();
- }
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->PHY_REG1;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= *(volatile uint32_t *)SysSrv_DdrTiming;
- dsb();
-
- //enter config state
- ddr_move_to_Config_state();
-// pDDR_Reg->DFIODTCFG = ((1<<3) | (1<<11)); //loaderÖЩÁ˳õʼ»¯
- pPHY_Reg->PHY_REG5d = 0X77;
- pPHY_Reg->PHY_REG5e = 0X77;
- //set auto power down idle
- pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
-
- //enable the hardware low-power interface
- pDDR_Reg->SCFG.b.hw_low_power_en = 1;
-
- ddr_update_odt();
-
- //enter access state
- ddr_move_to_Access_state();
-
- DDR_RESTORE_SP(save_sp);
-}
-#endif
-
-static void __sramfunc idle_port(void)
-{
- int i;
- uint32 clk_gate[10];
-
- //save clock gate status
- for(i=0;i<10;i++)
- {
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
- }
- //enable all clock gate for request idle
- for(i=0;i<10;i++)
- {
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
- }
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+peri_pwr_idlereq))+(1 << peri_pwr_idlereq); //peri bit 12
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) == 0);// bit 23
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vio_pwr_idlereq))+(1 << vio_pwr_idlereq); //vio
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) == 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vpu_pwr_idlereq))+(1 << vpu_pwr_idlereq); //vpu
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) == 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+gpu_pwr_idlereq))+(1 << gpu_pwr_idlereq); //gpu
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) == 0);
-
- //resume clock gate status
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-}
-
-
-static void __sramfunc deidle_port(void)
-{
- int i;
- uint32 clk_gate[10];
-
- //save clock gate status
- for(i=0;i<10;i++)
- {
- clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
- }
- //enable all clock gate for request idle
- for(i=0;i<10;i++)
- {
- pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
- }
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+peri_pwr_idlereq))+(0 << peri_pwr_idlereq); //peri bit 12
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) != 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vio_pwr_idlereq))+(0 << vio_pwr_idlereq); //vio
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) != 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vpu_pwr_idlereq))+(0 << vpu_pwr_idlereq); //vpu
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) != 0);
-
- pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+gpu_pwr_idlereq))+(0 << gpu_pwr_idlereq); //gpu
- dsb();
- while( (pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) != 0);
-
- //resume clock gate status
- for(i=0;i<10;i++)
- pCRU_Reg->CRU_CLKGATE_CON[i]= (clk_gate[i] | 0xffff0000);
-
-}
-
-
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
-Desc : ½øÈë×ÔË¢ÐÂ
-Params : nMHz ->ddrƵÂÊ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-/*
-static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
-{
- ddr_move_to_Config_state();
- ddr_move_to_Lowpower_state();
- pPHY_Reg->PHY_REG264 &= ~(1<<1);
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2))); //phy soft reset
- dsb();
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
- ddr_delayus(1);
-}
-*/
-static uint32 dtt_buffer[8];
-
-/*----------------------------------------------------------------------
-Name : void ddr_dtt_check(void)
-Desc : data training check
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static void ddr_dtt_check(void)
-{
- uint32 i;
- for(i=0;i<8;i++)
- {
- dtt_buffer[i] = p_copy_data[i];
- }
- dsb();
- flush_cache_all();
- outer_flush_all();
- for(i=0;i<8;i++)
- {
- if(dtt_buffer[i] != p_copy_data[i])
- {
-// sram_printascii("DTT failed!\n");
- break;
- }
- dtt_buffer[i] = 0;
- }
-
-}
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_selfrefresh_exit(void)
-Desc : Í˳ö×ÔË¢ÐÂ
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-#if 0
-static void __sramfunc ddr_selfrefresh_exit(void)
-{
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
- dsb();
- ddr_delayus(1);
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
- pPHY_Reg->PHY_REG264 |= (1<<1);
- dsb();
- ddr_move_to_Config_state();
- ddr_data_training();
- ddr_move_to_Access_state();
-// ddr_dtt_check();
-}
-#endif
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
-Desc : ÉèÖÃddr pllÇ°µÄtiming¼°mr²ÎÊýµ÷Õû
-Params : freq_slew :±äƵбÂÊ 1Éýƽ 0½µÆµ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
-{
- uint32 value_100n, value_1u;
-
- if(freq_slew == 1)
- {
- value_100n = DATA(ddr_reg).pctl_timing.togcnt100n;
- value_1u = DATA(ddr_reg).pctl_timing.togcnt1u;
- DATA(ddr_reg).pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
- DATA(ddr_reg).pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
- ddr_update_timing();
- ddr_update_mr();
- DATA(ddr_reg).pctl_timing.togcnt100n = value_100n;
- DATA(ddr_reg).pctl_timing.togcnt1u = value_1u;
- }
- else
- {
- pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
- pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
- }
-
- pDDR_Reg->TZQCSI = 0;
-
-}
-
-
-
-/*----------------------------------------------------------------------
-Name : void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
-Desc : ÉèÖÃddr pllºóµÄtiming¼°mr²ÎÊýµ÷Õû
-Params : freq_slew :±äƵбÂÊ 1Éýƽ 0½µÆµ
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-static void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
-{
- if(freq_slew == 1)
- {
- pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
- pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
- pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl_timing.tzqcsi;
- }
- else
- {
- ddr_update_timing();
- ddr_update_mr();
- }
- ddr_data_training();
-}
-
-static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew)
-{
- idle_port();
-
- ddr_move_to_Config_state();
- DATA(ddr_freq) = freq;
- ddr_change_freq_in(freq_slew);
- ddr_move_to_Lowpower_state();
- pPHY_Reg->PHY_REG264 &= ~(1<<1);
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2))); //phy soft reset
- dsb();
- /** 3. change frequence */
- FUNC(ddr_set_pll)(freq,1);
- ddr_set_dll_bypass(freq); //set phy dll mode;
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
- pPHY_Reg->PHY_REG264 |= (1<<1);
- dsb();
- ddr_update_odt();
- ddr_move_to_Config_state();
- ddr_change_freq_out(freq_slew);
- ddr_move_to_Access_state();
-
- deidle_port();
-}
-
-void PIE_FUNC(ddr_change_freq_sram)(void *arg)
-{
- struct ddr_change_freq_sram_param *param = arg;
- /* Make sure ddr_SRE_2_SRX paramter less than 4 */
- ddr_SRE_2_SRX(param->freq, param->freq_slew);
-}
-EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
-
-/*----------------------------------------------------------------------
-Name : uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
-Desc : ddr±äƵ
-Params : nMHz -> ±äƵµÄƵÂÊÖµ
-Return : ƵÂÊÖµ
-Notes :
-----------------------------------------------------------------------*/
-static uint32 ddr_change_freq_sram(uint32 nMHz, struct ddr_freq_t ddr_freq_t)
-{
- uint32 ret;
- uint32 i;
- volatile uint32 n;
- unsigned long flags;
- volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
-
- struct ddr_change_freq_sram_param param;
- //uint32 freq;
- uint32 freq_slew;
- uint32 arm_freq;
-
- arm_freq= ddr_get_pll_freq(APLL);
- *kern_to_pie(rockchip_pie_chunk, &DATA(loops_per_us)) = LPJ_100MHZ*arm_freq/1000000;
- ret =(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll)))(nMHz,0);
- if(ret == *p_ddr_freq)
- {
- goto out;
- }
- else
- {
- freq_slew = (ret > *p_ddr_freq)? 1 : -1;
- }
- ddr_get_parameter(ret);
- //*kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq))= ret;
- /** 1. Make sure there is no host access */
- local_irq_save(flags);
- local_fiq_disable();
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
- //DDR_SAVE_SP(save_sp);
-
-#if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
- n = ddr_freq_t.screen_ft_us;
- n = ddr_freq_t.t0;
- dsb();
-
- if(ddr_freq_t.screen_ft_us > 0){
-
- ddr_freq_t.t1 = cpu_clock(0);
- ddr_freq_t.t2 = (u32)(ddr_freq_t.t1 - ddr_freq_t.t0); //ns
-
-
- if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe)){
-
- //DDR_RESTORE_SP(save_sp);
- local_fiq_enable();
- local_irq_restore(flags);
- return 0;
- }else{
- rk_fb_poll_wait_frame_complete();
- }
- }
-#endif
-
- for(i=0;i<2;i++) //8KB SRAM
- {
- n=temp[1024*i];
- barrier();
- }
- n= pDDR_Reg->SCFG.d32;
- n= pPHY_Reg->PHY_REG1;
- n= pCRU_Reg->CRU_PLL_CON[0][0];
- n= *(volatile uint32_t *)SysSrv_DdrTiming;
- n= pGRF_Reg->GRF_SOC_STATUS0;
- dsb();
- param.freq = ret;
- param.freq_slew = freq_slew;
- call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
- ¶m,
- rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
- /** 5. Issues a Mode Exit command */
- // DDR_RESTORE_SP(save_sp);
- ddr_dtt_check();
- local_fiq_enable();
- local_irq_restore(flags);
-// clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
-out:
- return ret;
-}
-
-static uint32 _ddr_change_freq_3036(uint32_t nMHz)
-{
- struct ddr_freq_t ddr_freq_t;
- ddr_freq_t.screen_ft_us = 0;
-
- return ddr_change_freq_sram(nMHz,ddr_freq_t);
-}
-
-EXPORT_SYMBOL(_ddr_change_freq_3036);
-
-static void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
-{
- ddr_move_to_Config_state();
- ddr_move_to_Lowpower_state();
- pPHY_Reg->PHY_REG264 &= ~(1<<1);
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2))); //phy soft reset
- dsb();
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2); //disable DDR PHY clock
- ddr_delayus(1);
-}
-
-static void __sramlocalfunc ddr_selfrefresh_exit(void)
-{
- pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2); //enable DDR PHY clock
- dsb();
- ddr_delayus(1);
- pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
- pPHY_Reg->PHY_REG264 |= (1<<1);
- dsb();
- ddr_move_to_Config_state();
- ddr_data_training();
- ddr_move_to_Access_state();
- /*ddr_dtt_check();*/
-}
-
-void PIE_FUNC(ddr_suspend)(void)
-{
- ddr_selfrefresh_enter(0);
- pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x0 << (1 * 4)); /*PLL slow-mode*/
- dsb();
- ddr_delayus(1);
- pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x1 << 13); /*PLL power-down*/
- dsb();
- ddr_delayus(1);
-}
-EXPORT_PIE_SYMBOL(FUNC(ddr_suspend));
-
-/*----------------------------------------------------------------------
-Name : void __sramfunc ddr_suspend(void)
-Desc : ½øÈëddr suspend
-Params : void
-Return : void
-Notes :
-----------------------------------------------------------------------*/
-#if 0
-void ddr_suspend(void)
-{
- uint32 i;
- volatile uint32 n;
- volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
- /** 1. Make sure there is no host access */
- flush_cache_all();
- outer_flush_all();
- flush_tlb_all();
-
- /*sram size = 8KB*/
- for (i = 0; i < 2; i++) {
- n = temp[1024 * i];
- barrier();
- }
- n = pDDR_Reg->SCFG.d32;
- n = pPHY_Reg->PHY_REG1;
- n = pCRU_Reg->CRU_PLL_CON[0][0];
- n = *(volatile uint32_t *)SysSrv_DdrTiming;
- n = pGRF_Reg->GRF_SOC_STATUS0;
- dsb();
-
- fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_suspend)) ();
-}
-EXPORT_SYMBOL(ddr_suspend);
-#endif
-
-void PIE_FUNC(ddr_resume)(void)
-{
- uint32 delay = 1000;
-
- pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x0 << 13); /*PLL no power-down*/
- dsb();
- while (delay > 0) {
- ddr_delayus(1);
- if (pCRU_Reg->CRU_PLL_CON[1][1] & (0x1 << 10))
- break;
- delay--;
- }
-
- pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x1 << (1 * 4)); /*PLL normal*/
- dsb();
-
- ddr_selfrefresh_exit();
-}
-
-EXPORT_PIE_SYMBOL(FUNC(ddr_resume));
-#if 0
-static uint32 ddr_get_cap(void)
-{
- uint32 cs, bank, row, col,row1;
-
- bank = READ_BK_INFO();
- row = READ_CS0_ROW_INFO();
- col = READ_COL_INFO();
- cs = READ_CS_INFO();
- if(cs>1)
- {
- row1 = READ_CS1_ROW_INFO();
- return ((1 << (row + col + bank + 1))+(1 << (row1 + col + bank + 1)));
- }
- else
- {
- return (1 << (row + col + bank + 1));
- }
-}
-#endif
-#if 0
-/*----------------------------------------------------------------------
-Name : int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
-Desc : ddr ³õʼ»¯º¯Êý
-Params : dram_speed_bin ->ddr¿ÅÁ£ÀàÐÍ
- freq ->ƵÂÊÖµ
-Return : 0 ³É¹¦
-Notes :
-----------------------------------------------------------------------*/
-static int ddr_init(uint32_t dram_speed_bin, uint32 freq)
-{
- volatile uint32_t value = 0;
- uint32_t cs,die=1;
-
- ddr_print("version 1.00 20140704 \n");
- cs = READ_CS_INFO(); //case 0:1rank ; case 1:2rank ;
-
- p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
- p_ddr_freq =kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
- p_ddr_reg->mem_type = ((pGRF_Reg->GRF_OS_REG[1] >> 13) &0x7);
- p_ddr_reg->ddr_speed_bin = dram_speed_bin;
- *p_ddr_freq= 0;
- *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
- *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_dll_status)) = DDR3_DLL_DISABLE;
- p_copy_data = kern_to_pie(rockchip_pie_chunk, ©_data[0]);
- if(p_ddr_reg->mem_type != DDR3)
- {
- ddr_print("ddr type error type=%d\n",(p_ddr_reg->mem_type));
- return -1;
- }
-
- switch(READ_DIE_BW_INFO())
- {
- case 0: //8bit
- die = 2;
- break;
- case 1: //16bit
- die = 1;
- break;
- default:
- ddr_print("ddr die BW error=%d\n",READ_DIE_BW_INFO());
- break;
- }
-
-
- //get capability per chip, not total size, used for calculate tRFC
- p_ddr_reg->ddr_capability_per_die = ddr_get_cap()/(cs * die);
- ddr_print("%d CS, ROW=%d, Bank=%d, COL=%d, Total Capability=%dMB\n",
- cs, \
- READ_CS0_ROW_INFO(), \
- (0x1<<(READ_BK_INFO())), \
- READ_COL_INFO(), \
- (ddr_get_cap()>>20));/*
-*/
- //ddr_adjust_config(p_ddr_reg->mem_type);
-
- if(freq != 0)
- value=_ddr_change_freq(freq);
-
- /*clk_set_rate(clk_get(NULL, "ddr"), 0);*/
- ddr_print("init success!!! freq=%dMHz\n", (int)value);
- return 0;
-}
-#endif
-
+++ /dev/null
-/*
- * arch/arm/mach-rk2928/ddr.c-- for ddr3&ddr2
- *
- * Function Driver for DDR controller
- *
- * Copyright (C) 2012 Fuzhou Rockchip Electronics Co.,Ltd
- * Author:
- * hcy@rock-chips.com
- * yk@rock-chips.com
- * typ@rock-chips.com
- *
- * v1.00
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <linux/cpu.h>
-#include <dt-bindings/clock/ddr.h>
-#include <linux/rockchip/cpu_axi.h>
-#include <linux/rockchip/cru.h>
-#include <linux/rk_fb.h>
-
-typedef uint32_t uint32;
-
-#define DDR3_DDR2_DLL_DISABLE_FREQ (300) /* ¿ÅÁ£dll disableµÄƵÂÊ*/
-#define DDR3_DDR2_ODT_DISABLE_FREQ (333) /*¿ÅÁ£odt disableµÄƵÂÊ*/
-#define SR_IDLE (0x1) /*unit:32*DDR clk cycle, and 0 for disable auto self-refresh*/
-#define PD_IDLE (0x40) /*unit:DDR clk cycle, and 0 for disable auto power-down*/
-#define PHY_ODT_DISABLE_FREQ (333) /*¶¨ÒåÖ÷¿Ø¶Ëodt disableµÄƵÂÊ*/
-#define PHY_DLL_DISABLE_FREQ (266) /*¶¨ÒåÖ÷¿Ø¶Ëdll bypassµÄƵÂÊ*/
-
-#define ddr_print(x...) printk("DDR DEBUG: " x)
-
-#define SRAM_CODE_OFFSET rockchip_sram_virt
-#define SRAM_SIZE rockchip_sram_size
-
-#ifdef CONFIG_FB_ROCKCHIP
-#define DDR_CHANGE_FREQ_IN_LCDC_VSYNC
-#endif
-
-/*#define PHY_RX_PHASE_CAL*/
-#define PHY_DE_SKEW_STEP (20)
-/***********************************
- * DDR3 define
- ***********************************/
-/*mr0 for ddr3*/
-#define DDR3_BL8 (0)
-#define DDR3_BC4_8 (1)
-#define DDR3_BC4 (2)
-#define DDR3_CL(n) (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
-#define DDR3_WR(n) (((n)&0x7)<<9)
-#define DDR3_DLL_RESET (1<<8)
-#define DDR3_DLL_DeRESET (0<<8)
-
-/*mr1 for ddr3*/
-#define DDR3_DLL_ENABLE (0)
-#define DDR3_DLL_DISABLE (1)
-#define DDR3_MR1_AL(n) (((n)&0x7)<<3)
-
-#define DDR3_DS_40 (0)
-#define DDR3_DS_34 (1<<1)
-#define DDR3_Rtt_Nom_DIS (0)
-#define DDR3_Rtt_Nom_60 (1<<2)
-#define DDR3_Rtt_Nom_120 (1<<6)
-#define DDR3_Rtt_Nom_40 ((1<<2)|(1<<6))
-
-/*mr2 for ddr3*/
-#define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
-#define DDR3_Rtt_WR_DIS (0)
-#define DDR3_Rtt_WR_60 (1<<9)
-#define DDR3_Rtt_WR_120 (2<<9)
-
-#define DDR_PLL_REFDIV (1)
-#define FBDIV(n) ((0xFFF<<16) | (n&0xfff))
-#define REFDIV(n) ((0x3F<<16) | (n&0x3f))
-#define POSTDIV1(n) ((0x7<<(12+16)) | ((n&0x7)<<12))
-#define POSTDIV2(n) ((0x7<<(6+16)) | ((n&0x7)<<6))
-
-#define PLL_LOCK_STATUS (0x1<<10)
- /*CRU Registers updated*/
-typedef volatile struct tagCRU_STRUCT {
- uint32 CRU_PLL_CON[4][4];
- uint32 CRU_MODE_CON;
- uint32 CRU_CLKSEL_CON[35];
- uint32 CRU_CLKGATE_CON[11]; /*0xd0*/
- uint32 reserved1; /*0xfc*/
- uint32 CRU_GLB_SRST_FST_VALUE; /*0x100*/
- uint32 CRU_GLB_SRST_SND_VALUE;
- uint32 reserved2[2];
- uint32 CRU_SOFTRST_CON[9]; /*0x110*/
- uint32 CRU_MISC_CON; /*0x134*/
- uint32 reserved3[2];
- uint32 CRU_GLB_CNT_TH; /*0x140*/
- uint32 reserved4[3];
- uint32 CRU_GLB_RST_ST; /*0x150*/
- uint32 reserved5[(0x1c0 - 0x154) / 4];
- uint32 CRU_SDMMC_CON[2]; /*0x1c0*/
- uint32 CRU_SDIO_CON[2];
- uint32 reserved6[2];
- uint32 CRU_EMMC_CON[2]; /*0x1d8*/
- uint32 reserved7[(0x1f0 - 0x1e0) / 4];
- uint32 CRU_PLL_PRG_EN;
-} CRU_REG, *pCRU_REG;
-
-typedef struct tagGPIO_LH {
- uint32 GPIOL;
- uint32 GPIOH;
-} GPIO_LH_T;
-
-typedef struct tagGPIO_IOMUX {
- uint32 GPIOA_IOMUX;
- uint32 GPIOB_IOMUX;
- uint32 GPIOC_IOMUX;
- uint32 GPIOD_IOMUX;
-} GPIO_IOMUX_T;
-
-/********************************
-*GRF ¼Ä´æÆ÷ÖÐGRF_OS_REG1 ´æddr rank£¬typeµÈÐÅÏ¢
-*GRF_SOC_CON2¼Ä´æÆ÷ÖпØÖÆc_sysreqÐźÅÏòpctl·¢ËͽøÈëlow power ÇëÇó
-*GRF_DDRC_STAT ¿É²éѯpctlÊÇ·ñ½ÓÊÜÇëÇó ½øÈëlow power
-********************************/
-/*REG FILE registers*/
-/*GRF_SOC_CON0*/
-#define DDR_MONITOR_EN ((1<<(16+6))+(1<<6))
-#define DDR_MONITOR_DISB ((1<<(16+6))+(0<<6))
-
-/*GRF_SOC_STATUS0*/
-#define sys_pwr_idle (1<<27)
-#define gpu_pwr_idle (1<<26)
-#define vpu_pwr_idle (1<<25)
-#define vio_pwr_idle (1<<24)
-#define peri_pwr_idle (1<<23)
-#define core_pwr_idle (1<<22)
-/*GRF_SOC_CON2*/
-#define core_pwr_idlereq (13)
-#define peri_pwr_idlereq (12)
-#define vio_pwr_idlereq (11)
-#define vpu_pwr_idlereq (10)
-#define gpu_pwr_idlereq (9)
-#define sys_pwr_idlereq (8)
-#define GRF_DDR_LP_EN (0x1<<(2+16))
-#define GRF_DDR_LP_DISB ((0x1<<(2+16))|(0x1<<2))
-
-/*grf updated*/
-typedef volatile struct tagREG_FILE {
- uint32 reserved0[(0xa8 - 0x0) / 4];
- GPIO_IOMUX_T GRF_GPIO_IOMUX[4]; /*0x00a8*/
- uint32 GRF_GPIO2C_IOMUX2; /*0xe8*/
- uint32 GRF_CIF_IOMUX[2];
- uint32 reserved1[(0x100 - 0xf4) / 4];
- uint32 GRF_GPIO_DS; /*0x100*/
- uint32 reserved2[(0x118 - 0x104) / 4];
- GPIO_LH_T GRF_GPIO_PULL[4]; /*0x118*/
- uint32 reserved3[1];
- uint32 GRF_ACODEC_CON; /*0x13c*/
- uint32 GRF_SOC_CON[3]; /*0x140*/
- uint32 GRF_SOC_STATUS0;
- uint32 GRF_LVDS_CON0; /*0x150*/
- uint32 reserved4[(0x15c - 0x154) / 4];
- uint32 GRF_DMAC_CON[3]; /*0x15c*/
- uint32 GRF_MAC_CON[2];
- uint32 GRF_TVE_CON; /*0x170*/
- uint32 reserved5[(0x17c - 0x174) / 4];
- uint32 GRF_UOC0_CON0; /*0x17c*/
- uint32 reserved6;
- uint32 GRF_UOC1_CON[5]; /*0x184*/
- uint32 reserved7;
- uint32 GRF_DDRC_STAT; /*0x19c*/
- uint32 reserved8;
- uint32 GRF_SOC_STATUS1; /*0x1a4*/
- uint32 GRF_CPU_CON[4];
- uint32 reserved9[(0x1c0 - 0x1b8) / 4];
- uint32 GRF_CPU_STATUS[2]; /*0x1c0*/
- uint32 GRF_OS_REG[8];
- uint32 reserved10[(0x200 - 0x1e8) / 4];
- uint32 GRF_PVTM_CON[4]; /*0x200*/
- uint32 GRF_PVTM_STATUS[4];
- /*uint32 reserved10[(0x220-0x214)/4];*/
- uint32 GRF_DFI_WRNUM; /*0X220*/
- uint32 GRF_DFI_RDNUM;
- uint32 GRF_DFI_ACTNUM;
- uint32 GRF_DFI_TIMERVAL;
- uint32 GRF_NIF_FIFO[4];
- uint32 reserved11[(0x280 - 0x240) / 4];
- uint32 GRF_USBPHY0_CON[8]; /*0x280*/
- uint32 GRF_USBPHY1_CON[8];
- uint32 GRF_UOC_STATUS0; /*0x2c0*/
- uint32 reserved12[(0x300 - 0x2c4) / 4];
- uint32 GRF_CHIP_TAG;
- uint32 GRF_SDMMC_DET_CNT;
- uint32 reserved13[(0x37c - 0x308) / 4];
- uint32 GRF_EFUSE_PRG_EN;
-} REG_FILE, *pREG_FILE;
-
-/*SCTL*/
-#define INIT_STATE (0)
-#define CFG_STATE (1)
-#define GO_STATE (2)
-#define SLEEP_STATE (3)
-#define WAKEUP_STATE (4)
-
-/*STAT*/
-#define Init_mem (0)
-#define Config (1)
-#define Config_req (2)
-#define Access (3)
-#define Access_req (4)
-#define Low_power (5)
-#define Low_power_entry_req (6)
-#define Low_power_exit_req (7)
-
-/*MCFG*/
-#define mddr_lpddr2_clk_stop_idle(n) ((n)<<24)
-#define pd_idle(n) ((n)<<8)
-#define mddr_en (2<<22)
-#define lpddr2_en (3<<22)
-#define ddr2_en (0<<5)
-#define ddr3_en (1<<5)
-#define lpddr2_s2 (0<<6)
-#define lpddr2_s4 (1<<6)
-#define mddr_lpddr2_bl_2 (0<<20)
-#define mddr_lpddr2_bl_4 (1<<20)
-#define mddr_lpddr2_bl_8 (2<<20)
-#define mddr_lpddr2_bl_16 (3<<20)
-#define ddr2_ddr3_bl_4 (0)
-#define ddr2_ddr3_bl_8 (1)
-#define tfaw_cfg(n) (((n)-4)<<18)
-#define pd_exit_slow (0<<17)
-#define pd_exit_fast (1<<17)
-#define pd_type(n) ((n)<<16)
-#define two_t_en(n) ((n)<<3)
-#define bl8int_en(n) ((n)<<2)
-#define cke_or_en(n) ((n)<<1)
-
-/*POWCTL*/
-#define power_up_start (1<<0)
-
-/*POWSTAT*/
-#define power_up_done (1<<0)
-
-/*DFISTSTAT0*/
-#define dfi_init_complete (1<<0)
-
-/*CMDTSTAT*/
-#define cmd_tstat (1<<0)
-
-/*CMDTSTATEN*/
-#define cmd_tstat_en (1<<1)
-
-/*MCMD*/
-#define Deselect_cmd (0)
-#define PREA_cmd (1)
-#define REF_cmd (2)
-#define MRS_cmd (3)
-#define ZQCS_cmd (4)
-#define ZQCL_cmd (5)
-#define RSTL_cmd (6)
-#define MRR_cmd (8)
-#define DPDE_cmd (9)
-
-#define lpddr2_op(n) ((n)<<12)
-#define lpddr2_ma(n) ((n)<<4)
-
-#define bank_addr(n) ((n)<<17)
-#define cmd_addr(n) ((n)<<4)
-
-#define start_cmd (1u<<31)
-
-typedef union STAT_Tag {
- uint32 d32;
- struct {
- unsigned ctl_stat:3;
- unsigned reserved3:1;
- unsigned lp_trig:3;
- unsigned reserved7_31:25;
- } b;
-} STAT_T;
-
-typedef union SCFG_Tag {
- uint32 d32;
- struct {
- unsigned hw_low_power_en:1;
- unsigned reserved1_5:5;
- unsigned nfifo_nif1_dis:1;
- unsigned reserved7:1;
- unsigned bbflags_timing:4;
- unsigned reserved12_31:20;
- } b;
-} SCFG_T;
-
-/* DDR Controller register struct */
-typedef volatile struct DDR_REG_Tag {
- /*Operational State, Control, and Status Registers*/
- SCFG_T SCFG; /*State Configuration Register*/
- volatile uint32 SCTL; /*State Control Register*/
- STAT_T STAT; /*State Status Register*/
- volatile uint32 INTRSTAT; /*Interrupt Status Register*/
- uint32 reserved0[(0x40 - 0x10) / 4];
- /*Initailization Control and Status Registers*/
- volatile uint32 MCMD; /*Memory Command Register*/
- volatile uint32 POWCTL; /*Power Up Control Registers*/
- volatile uint32 POWSTAT; /*Power Up Status Register*/
- volatile uint32 CMDTSTAT; /*Command Timing Status Register*/
- volatile uint32 CMDTSTATEN; /*Command Timing Status Enable Register*/
- uint32 reserved1[(0x60 - 0x54) / 4];
- volatile uint32 MRRCFG0; /*MRR Configuration 0 Register*/
- volatile uint32 MRRSTAT0; /*MRR Status 0 Register*/
- volatile uint32 MRRSTAT1; /*MRR Status 1 Register*/
- uint32 reserved2[(0x7c - 0x6c) / 4];
- /*Memory Control and Status Registers*/
- volatile uint32 MCFG1; /*Memory Configuration 1 Register*/
- volatile uint32 MCFG; /*Memory Configuration Register*/
- volatile uint32 PPCFG; /*Partially Populated Memories Configuration Register*/
- volatile uint32 MSTAT; /*Memory Status Register*/
- volatile uint32 LPDDR2ZQCFG; /*LPDDR2 ZQ Configuration Register*/
- uint32 reserved3;
- /*DTU Control and Status Registers*/
- volatile uint32 DTUPDES; /*DTU Status Register*/
- volatile uint32 DTUNA; /*DTU Number of Random Addresses Created Register*/
- volatile uint32 DTUNE; /*DTU Number of Errors Register*/
- volatile uint32 DTUPRD0; /*DTU Parallel Read 0*/
- volatile uint32 DTUPRD1; /*DTU Parallel Read 1*/
- volatile uint32 DTUPRD2; /*DTU Parallel Read 2*/
- volatile uint32 DTUPRD3; /*DTU Parallel Read 3*/
- volatile uint32 DTUAWDT; /*DTU Address Width*/
- uint32 reserved4[(0xc0 - 0xb4) / 4];
- /*Memory Timing Registers*/
- volatile uint32 TOGCNT1U; /*Toggle Counter 1U Register*/
- volatile uint32 TINIT; /*t_init Timing Register*/
- volatile uint32 TRSTH; /*Reset High Time Register*/
- volatile uint32 TOGCNT100N; /*Toggle Counter 100N Register*/
- volatile uint32 TREFI; /*t_refi Timing Register*/
- volatile uint32 TMRD; /*t_mrd Timing Register*/
- volatile uint32 TRFC; /*t_rfc Timing Register*/
- volatile uint32 TRP; /*t_rp Timing Register*/
- volatile uint32 TRTW; /*t_rtw Timing Register*/
- volatile uint32 TAL; /*AL Latency Register*/
- volatile uint32 TCL; /*CL Timing Register*/
- volatile uint32 TCWL; /*CWL Register*/
- volatile uint32 TRAS; /*t_ras Timing Register*/
- volatile uint32 TRC; /*t_rc Timing Register*/
- volatile uint32 TRCD; /*t_rcd Timing Register*/
- volatile uint32 TRRD; /*t_rrd Timing Register*/
- volatile uint32 TRTP; /*t_rtp Timing Register*/
- volatile uint32 TWR; /*t_wr Timing Register*/
- volatile uint32 TWTR; /*t_wtr Timing Register*/
- volatile uint32 TEXSR; /*t_exsr Timing Register*/
- volatile uint32 TXP; /*t_xp Timing Register*/
- volatile uint32 TXPDLL; /*t_xpdll Timing Register*/
- volatile uint32 TZQCS; /*t_zqcs Timing Register*/
- volatile uint32 TZQCSI; /*t_zqcsi Timing Register*/
- volatile uint32 TDQS; /*t_dqs Timing Register*/
- volatile uint32 TCKSRE; /*t_cksre Timing Register*/
- volatile uint32 TCKSRX; /*t_cksrx Timing Register*/
- volatile uint32 TCKE; /*t_cke Timing Register*/
- volatile uint32 TMOD; /*t_mod Timing Register*/
- volatile uint32 TRSTL; /*Reset Low Timing Register*/
- volatile uint32 TZQCL; /*t_zqcl Timing Register*/
- volatile uint32 TMRR; /*t_mrr Timing Register*/
- volatile uint32 TCKESR; /*t_ckesr Timing Register*/
- volatile uint32 TDPD; /*t_dpd Timing Register*/
- uint32 reserved5[(0x180 - 0x148) / 4];
- /*ECC Configuration, Control, and Status Registers*/
- volatile uint32 ECCCFG; /*ECC Configuration Register*/
- volatile uint32 ECCTST; /*ECC Test Register*/
- volatile uint32 ECCCLR; /*ECC Clear Register*/
- volatile uint32 ECCLOG; /*ECC Log Register*/
- uint32 reserved6[(0x200 - 0x190) / 4];
- /*DTU Control and Status Registers*/
- volatile uint32 DTUWACTL; /*DTU Write Address Control Register*/
- volatile uint32 DTURACTL; /*DTU Read Address Control Register*/
- volatile uint32 DTUCFG; /*DTU Configuration Control Register*/
- volatile uint32 DTUECTL; /*DTU Execute Control Register*/
- volatile uint32 DTUWD0; /*DTU Write Data 0*/
- volatile uint32 DTUWD1; /*DTU Write Data 1*/
- volatile uint32 DTUWD2; /*DTU Write Data 2*/
- volatile uint32 DTUWD3; /*DTU Write Data 3*/
- volatile uint32 DTUWDM; /*DTU Write Data Mask*/
- volatile uint32 DTURD0; /*DTU Read Data 0*/
- volatile uint32 DTURD1; /*DTU Read Data 1*/
- volatile uint32 DTURD2; /*DTU Read Data 2*/
- volatile uint32 DTURD3; /*DTU Read Data 3*/
- volatile uint32 DTULFSRWD; /*DTU LFSR Seed for Write Data Generation*/
- volatile uint32 DTULFSRRD; /*DTU LFSR Seed for Read Data Generation*/
- volatile uint32 DTUEAF; /*DTU Error Address FIFO*/
- /*DFI Control Registers*/
- volatile uint32 DFITCTRLDELAY; /*DFI tctrl_delay Register*/
- volatile uint32 DFIODTCFG; /*DFI ODT Configuration Register*/
- volatile uint32 DFIODTCFG1; /*DFI ODT Configuration 1 Register*/
- volatile uint32 DFIODTRANKMAP; /*DFI ODT Rank Mapping Register*/
- /*DFI Write Data Registers*/
- volatile uint32 DFITPHYWRDATA; /*DFI tphy_wrdata Register*/
- volatile uint32 DFITPHYWRLAT; /*DFI tphy_wrlat Register*/
- uint32 reserved7[(0x260 - 0x258) / 4];
- volatile uint32 DFITRDDATAEN; /*DFI trddata_en Register*/
- volatile uint32 DFITPHYRDLAT; /*DFI tphy_rddata Register*/
- uint32 reserved8[(0x270 - 0x268) / 4];
- /*DFI Update Registers*/
- volatile uint32 DFITPHYUPDTYPE0; /*DFI tphyupd_type0 Register*/
- volatile uint32 DFITPHYUPDTYPE1; /*DFI tphyupd_type1 Register*/
- volatile uint32 DFITPHYUPDTYPE2; /*DFI tphyupd_type2 Register*/
- volatile uint32 DFITPHYUPDTYPE3; /*DFI tphyupd_type3 Register*/
- volatile uint32 DFITCTRLUPDMIN; /*DFI tctrlupd_min Register*/
- volatile uint32 DFITCTRLUPDMAX; /*DFI tctrlupd_max Register*/
- volatile uint32 DFITCTRLUPDDLY; /*DFI tctrlupd_dly Register*/
- uint32 reserved9;
- volatile uint32 DFIUPDCFG; /*DFI Update Configuration Register*/
- volatile uint32 DFITREFMSKI; /*DFI Masked Refresh Interval Register*/
- volatile uint32 DFITCTRLUPDI; /*DFI tctrlupd_interval Register*/
- uint32 reserved10[(0x2ac - 0x29c) / 4];
- volatile uint32 DFITRCFG0; /*DFI Training Configuration 0 Register*/
- volatile uint32 DFITRSTAT0; /*DFI Training Status 0 Register*/
- volatile uint32 DFITRWRLVLEN; /*DFI Training dfi_wrlvl_en Register*/
- volatile uint32 DFITRRDLVLEN; /*DFI Training dfi_rdlvl_en Register*/
- volatile uint32 DFITRRDLVLGATEEN; /*DFI Training dfi_rdlvl_gate_en Register*/
- /*DFI Status Registers*/
- volatile uint32 DFISTSTAT0; /*DFI Status Status 0 Register*/
- volatile uint32 DFISTCFG0; /*DFI Status Configuration 0 Register*/
- volatile uint32 DFISTCFG1; /*DFI Status configuration 1 Register*/
- uint32 reserved11;
- volatile uint32 DFITDRAMCLKEN; /*DFI tdram_clk_enalbe Register*/
- volatile uint32 DFITDRAMCLKDIS; /*DFI tdram_clk_disalbe Register*/
- volatile uint32 DFISTCFG2; /*DFI Status configuration 2 Register*/
- volatile uint32 DFISTPARCLR; /*DFI Status Parity Clear Register*/
- volatile uint32 DFISTPARLOG; /*DFI Status Parity Log Register*/
- uint32 reserved12[(0x2f0 - 0x2e4) / 4];
- /*DFI Low Power Registers*/
- volatile uint32 DFILPCFG0; /*DFI Low Power Configuration 0 Register*/
- uint32 reserved13[(0x300 - 0x2f4) / 4];
- /*DFI Training 2 Registers*/
- volatile uint32 DFITRWRLVLRESP0; /*DFI Training dif_wrlvl_resp Status 0 Register*/
- volatile uint32 DFITRWRLVLRESP1; /*DFI Training dif_wrlvl_resp Status 1 Register*/
- volatile uint32 DFITRWRLVLRESP2; /*DFI Training dif_wrlvl_resp Status 2 Register*/
- volatile uint32 DFITRRDLVLRESP0; /*DFI Training dif_rdlvl_resp Status 0 Register*/
- volatile uint32 DFITRRDLVLRESP1; /*DFI Training dif_rdlvl_resp Status 1 Register*/
- volatile uint32 DFITRRDLVLRESP2; /*DFI Training dif_rdlvl_resp Status 2 Register*/
- volatile uint32 DFITRWRLVLDELAY0; /*DFI Training dif_wrlvl_delay Configuration 0 Register*/
- volatile uint32 DFITRWRLVLDELAY1; /*DFI Training dif_wrlvl_delay Configuration 1 Register*/
- volatile uint32 DFITRWRLVLDELAY2; /*DFI Training dif_wrlvl_delay Configuration 2 Register*/
- volatile uint32 DFITRRDLVLDELAY0; /*DFI Training dif_rdlvl_delay Configuration 0 Register*/
- volatile uint32 DFITRRDLVLDELAY1; /*DFI Training dif_rdlvl_delay Configuration 1 Register*/
- volatile uint32 DFITRRDLVLDELAY2; /*DFI Training dif_rdlvl_delay Configuration 2 Register*/
- volatile uint32 DFITRRDLVLGATEDELAY0; /*DFI Training dif_rdlvl_gate_delay Configuration 0 Register*/
- volatile uint32 DFITRRDLVLGATEDELAY1; /*DFI Training dif_rdlvl_gate_delay Configuration 1 Register*/
- volatile uint32 DFITRRDLVLGATEDELAY2; /*DFI Training dif_rdlvl_gate_delay Configuration 2 Register*/
- volatile uint32 DFITRCMD; /*DFI Training Command Register*/
- uint32 reserved14[(0x3f8 - 0x340) / 4];
- /*IP Status Registers*/
- volatile uint32 IPVR; /*IP Version Register*/
- volatile uint32 IPTR; /*IP Type Register*/
-} DDR_REG_T, *pDDR_REG_T;
-
-/*PHY_REG2*/
-#define PHY_AUTO_CALIBRATION (1<<0)
-#define PHY_SW_CALIBRATION (1<<1)
-/*PHY_REG1*/
-#define PHY_DDR2 (1)
-#define PHY_DDR3 (0)
-#define PHY_LPDDR2 (2)
-#define PHY_Burst8 (1<<2)
-
-#define PHY_RON_DISABLE (0)
-#define PHY_RON_309ohm (1)
-#define PHY_RON_155ohm (2)
-#define PHY_RON_103ohm (3)
-#define PHY_RON_77ohm (4)
-#define PHY_RON_63ohm (5)
-#define PHY_RON_52ohm (6)
-#define PHY_RON_45ohm (7)
-/*#define PHY_RON_77ohm (8)*/
-#define PHY_RON_62ohm (9)
-/*#define PHY_RON_52ohm (10)*/
-#define PHY_RON_44ohm (11)
-#define PHY_RON_39ohm (12)
-#define PHY_RON_34ohm (13)
-#define PHY_RON_31ohm (14)
-#define PHY_RON_28ohm (15)
-
-#define PHY_RTT_DISABLE (0)
-#define PHY_RTT_816ohm (1)
-#define PHY_RTT_431ohm (2)
-#define PHY_RTT_287ohm (3)
-#define PHY_RTT_216ohm (4)
-#define PHY_RTT_172ohm (5)
-#define PHY_RTT_145ohm (6)
-#define PHY_RTT_124ohm (7)
-#define PHY_RTT_215ohm (8)
-/*#define PHY_RTT_172ohm (9)*/
-#define PHY_RTT_144ohm (10)
-#define PHY_RTT_123ohm (11)
-#define PHY_RTT_108ohm (12)
-#define PHY_RTT_96ohm (13)
-#define PHY_RTT_86ohm (14)
-#define PHY_RTT_78ohm (15)
-
-#define PHY_DRV_ODT_SET(n) ((n<<4)|n)
-
-/* DDR PHY register struct updated */
-typedef volatile struct DDRPHY_REG_Tag {
- volatile uint32 PHY_REG0; /*PHY soft reset Register*/
- volatile uint32 PHY_REG1; /*phy working mode, burst length*/
- volatile uint32 PHY_REG2; /*PHY DQS squelch calibration Register*/
- volatile uint32 PHY_REG3; /*channel A read odt delay*/
- volatile uint32 PHY_REG4; /*channel B read odt dleay*/
- uint32 reserved0[(0x2c - 0x14) / 4];
- volatile uint32 PHY_REGb; /*cl,al*/
- volatile uint32 PHY_REGc; /*CWL set register*/
- uint32 reserved1[(0x44 - 0x34) / 4];
- volatile uint32 PHY_REG11; /*cmd drv*/
- volatile uint32 PHY_REG12; /*cmd weak pull up*/
- volatile uint32 PHY_REG13; /*cmd dll delay*/
- volatile uint32 PHY_REG14; /*CK dll delay*/
- uint32 reserved2; /*0x54*/
- volatile uint32 PHY_REG16; /*/CK drv*/
- uint32 reserved3[(0x80 - 0x5c) / 4];
- volatile uint32 PHY_REG20; /*left channel a drv*/
- volatile uint32 PHY_REG21; /*left channel a odt*/
- uint32 reserved4[(0x98 - 0x88) / 4];
- volatile uint32 PHY_REG26; /*left channel a dq write dll*/
- volatile uint32 PHY_REG27; /*left channel a dqs write dll*/
- volatile uint32 PHY_REG28; /*left channel a dqs read dll*/
- uint32 reserved5[(0xc0 - 0xa4) / 4];
- volatile uint32 PHY_REG30; /*right channel a drv*/
- volatile uint32 PHY_REG31; /*right channel a odt*/
- uint32 reserved6[(0xd8 - 0xc8) / 4];
- volatile uint32 PHY_REG36; /*right channel a dq write dll*/
- volatile uint32 PHY_REG37; /*right channel a dqs write dll*/
- volatile uint32 PHY_REG38; /*right channel a dqs read dll*/
- uint32 reserved7[(0x100 - 0xe4) / 4];
- volatile uint32 PHY_REG40; /*left channel b drv*/
- volatile uint32 PHY_REG41; /*left channel b odt*/
- uint32 reserved8[(0x118 - 0x108) / 4];
- volatile uint32 PHY_REG46; /*left channel b dq write dll*/
- volatile uint32 PHY_REG47; /*left channel b dqs write dll*/
- volatile uint32 PHY_REG48; /*left channel b dqs read dll*/
- uint32 reserved9[(0x140 - 0x124) / 4];
- volatile uint32 PHY_REG50; /*right channel b drv*/
- volatile uint32 PHY_REG51; /*right channel b odt*/
- uint32 reserved10[(0x158 - 0x148) / 4];
- volatile uint32 PHY_REG56; /*right channel b dq write dll*/
- volatile uint32 PHY_REG57; /*right channel b dqs write dll*/
- volatile uint32 PHY_REG58; /*right channel b dqs read dll*/
- uint32 reserved11[(0x290 - 0x164) / 4];
- volatile uint32 PHY_REGDLL; /*dll bypass switch reg*/
- uint32 reserved12[(0x2c0 - 0x294) / 4];
- volatile uint32 PHY_REG_skew[(0x3b0 - 0x2c0) / 4]; /*de-skew*/
- uint32 reserved13[(0x3e8 - 0x3b0) / 4];
- volatile uint32 PHY_REGfa; /*idqs*/
- volatile uint32 PHY_REGfb; /* left channel a calibration result*/
- volatile uint32 PHY_REGfc; /* right channel a calibration result*/
- volatile uint32 PHY_REGfd; /*left channel b calibration result*/
- volatile uint32 PHY_REGfe; /* right channel b calibration result*/
- volatile uint32 PHY_REGff; /*calibrationg done*/
-} DDRPHY_REG_T, *pDDRPHY_REG_T;
-
-#define pCRU_Reg ((pCRU_REG)RK_CRU_VIRT)
-#define pGRF_Reg ((pREG_FILE)RK_GRF_VIRT)
-#define pDDR_Reg ((pDDR_REG_T)RK_DDR_VIRT)
-#define pPHY_Reg ((pDDRPHY_REG_T)(RK_DDR_VIRT+RK3036_DDR_PCTL_SIZE))
-#define SysSrv_DdrTiming (RK_CPU_AXI_BUS_VIRT+0xc)
-#define PMU_PWEDN_ST (RK_PMU_VIRT + 0x8)
-#define READ_CS_INFO() ((((pGRF_Reg->GRF_OS_REG[1])>>11)&0x1)+1)
-#define READ_COL_INFO() (9+(((pGRF_Reg->GRF_OS_REG[1])>>9)&0x3))
-#define READ_BK_INFO() (3-(((pGRF_Reg->GRF_OS_REG[1])>>8)&0x1))
-#define READ_CS0_ROW_INFO() (13+(((pGRF_Reg->GRF_OS_REG[1])>>6)&0x3))
-#define READ_CS1_ROW_INFO() (13+(((pGRF_Reg->GRF_OS_REG[1])>>4)&0x3))
-#define READ_BW_INFO() (2>>(((pGRF_Reg->GRF_OS_REG[1])&0xc)>>2)) /*´úÂëÖÐ 0->8bit 1->16bit 2->32bit ÓëgrfÖж¨ÒåÏà·´*/
-#define READ_DIE_BW_INFO() (2>>((pGRF_Reg->GRF_OS_REG[1])&0x3))
-
-/***********************************
- * LPDDR2 define
- ***********************************/
-/*MR0 (Device Information)*/
-#define LPDDR2_DAI (0x1) /* 0:DAI complete, 1:DAI still in progress*/
-#define LPDDR2_DI (0x1<<1) /* 0:S2 or S4 SDRAM, 1:NVM*/
-#define LPDDR2_DNVI (0x1<<2) /* 0:DNV not supported, 1:DNV supported*/
-#define LPDDR2_RZQI (0x3<<3) /*00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float*/
- /*10:ZQ-pin may short to GND. 11:ZQ-pin self test completed, no error condition detected.*/
-
-/*MR1 (Device Feature)*/
-#define LPDDR2_BL4 (0x2)
-#define LPDDR2_BL8 (0x3)
-#define LPDDR2_BL16 (0x4)
-#define LPDDR2_nWR(n) (((n)-2)<<5)
-
-/*MR2 (Device Feature 2)*/
-#define LPDDR2_RL3_WL1 (0x1)
-#define LPDDR2_RL4_WL2 (0x2)
-#define LPDDR2_RL5_WL2 (0x3)
-#define LPDDR2_RL6_WL3 (0x4)
-#define LPDDR2_RL7_WL4 (0x5)
-#define LPDDR2_RL8_WL4 (0x6)
-
-/*MR3 (IO Configuration 1)*/
-#define LPDDR2_DS_34 (0x1)
-#define LPDDR2_DS_40 (0x2)
-#define LPDDR2_DS_48 (0x3)
-#define LPDDR2_DS_60 (0x4)
-#define LPDDR2_DS_80 (0x6)
-#define LPDDR2_DS_120 (0x7) /*optional*/
-
-/*MR4 (Device Temperature)*/
-#define LPDDR2_tREF_MASK (0x7)
-#define LPDDR2_4_tREF (0x1)
-#define LPDDR2_2_tREF (0x2)
-#define LPDDR2_1_tREF (0x3)
-#define LPDDR2_025_tREF (0x5)
-#define LPDDR2_025_tREF_DERATE (0x6)
-
-#define LPDDR2_TUF (0x1<<7)
-
-/*MR8 (Basic configuration 4)*/
-#define LPDDR2_S4 (0x0)
-#define LPDDR2_S2 (0x1)
-#define LPDDR2_N (0x2)
-#define LPDDR2_Density(mr8) (8<<(((mr8)>>2)&0xf)) /*Unit:MB*/
-#define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
-
-/*MR10 (Calibration)*/
-#define LPDDR2_ZQINIT (0xFF)
-#define LPDDR2_ZQCL (0xAB)
-#define LPDDR2_ZQCS (0x56)
-#define LPDDR2_ZQRESET (0xC3)
-
-/*MR16 (PASR Bank Mask)*/
-/*S2 SDRAM Only*/
-#define LPDDR2_PASR_Full (0x0)
-#define LPDDR2_PASR_1_2 (0x1)
-#define LPDDR2_PASR_1_4 (0x2)
-#define LPDDR2_PASR_1_8 (0x3)
-
-typedef enum PLL_ID_Tag {
- APLL = 0,
- DPLL,
- CPLL,
- GPLL,
- PLL_MAX
-} PLL_ID;
-
-typedef enum DRAM_TYPE_Tag {
- LPDDR = 0,
- DDR,
- DDR2,
- DDR3,
- LPDDR2S2,
- LPDDR2,
-
- DRAM_MAX
-} DRAM_TYPE;
-
-struct ddr_freq_t {
- unsigned long screen_ft_us;
- unsigned long long t0;
- unsigned long long t1;
- unsigned long t2;
-};
-
-typedef struct PCTRL_TIMING_Tag {
- uint32 ddrFreq;
- /*Memory Timing Registers*/
- uint32 togcnt1u; /*Toggle Counter 1U Register*/
- uint32 tinit; /*t_init Timing Register*/
- uint32 trsth; /*Reset High Time Register*/
- uint32 togcnt100n; /*Toggle Counter 100N Register*/
- uint32 trefi; /*t_refi Timing Register*/
- uint32 tmrd; /*t_mrd Timing Register*/
- uint32 trfc; /*t_rfc Timing Register*/
- uint32 trp; /*t_rp Timing Register*/
- uint32 trtw; /*t_rtw Timing Register*/
- uint32 tal; /*AL Latency Register*/
- uint32 tcl; /*CL Timing Register*/
- uint32 tcwl; /*CWL Register*/
- uint32 tras; /*t_ras Timing Register*/
- uint32 trc; /*t_rc Timing Register*/
- uint32 trcd; /*t_rcd Timing Register*/
- uint32 trrd; /*t_rrd Timing Register*/
- uint32 trtp; /*t_rtp Timing Register*/
- uint32 twr; /*t_wr Timing Register*/
- uint32 twtr; /*t_wtr Timing Register*/
- uint32 texsr; /*t_exsr Timing Register*/
- uint32 txp; /*t_xp Timing Register*/
- uint32 txpdll; /*t_xpdll Timing Register*/
- uint32 tzqcs; /*t_zqcs Timing Register*/
- uint32 tzqcsi; /*t_zqcsi Timing Register*/
- uint32 tdqs; /*t_dqs Timing Register*/
- uint32 tcksre; /*t_cksre Timing Register*/
- uint32 tcksrx; /*t_cksrx Timing Register*/
- uint32 tcke; /*t_cke Timing Register*/
- uint32 tmod; /*t_mod Timing Register*/
- uint32 trstl; /*Reset Low Timing Register*/
- uint32 tzqcl; /*t_zqcl Timing Register*/
- uint32 tmrr; /*t_mrr Timing Register*/
- uint32 tckesr; /*t_ckesr Timing Register*/
- uint32 tdpd; /*t_dpd Timing Register*/
-} PCTL_TIMING_T;
-
-struct ddr_change_freq_sram_param {
- uint32 freq;
- uint32 freq_slew;
-};
-
-typedef union NOC_TIMING_Tag {
- uint32 d32;
- struct {
- unsigned ActToAct:6;
- unsigned RdToMiss:6;
- unsigned WrToMiss:6;
- unsigned BurstLen:3;
- unsigned RdToWr:5;
- unsigned WrToRd:5;
- unsigned BwRatio:1;
- } b;
-} NOC_TIMING_T;
-
-typedef struct BACKUP_REG_Tag {
- PCTL_TIMING_T pctl_timing;
- NOC_TIMING_T noc_timing;
- uint32 ddrMR[4];
- uint32 mem_type;
- uint32 ddr_speed_bin;
- uint32 ddr_capability_per_die;
-} BACKUP_REG_T;
-
-BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
-static BACKUP_REG_T *p_ddr_reg;
-
-uint32 DEFINE_PIE_DATA(ddr_freq);
-static uint32 *p_ddr_freq;
-uint32 DEFINE_PIE_DATA(ddr_sr_idle);
-uint32 DEFINE_PIE_DATA(ddr_dll_status); /* ¼Ç¼ddr dllµÄ״̬£¬ÔÚselfrefresh exitʱѡÔñÊÇ·ñ½øÐÐdll reset*/
-
-static const uint32_t ddr3_cl_cwl[22][4] = {
-/* 0~330 330~400 400~533 speed
-* tCK >3 2.5~3 1.875~2.5 1.875~1.5
-* cl<<16, cwl cl<<16, cwl cl<<16, cwl */
- {((5 << 16) | 5), ((5 << 16) | 5), 0, 0}, /*DDR3_800D*/
- {((5 << 16) | 5), ((6 << 16) | 5), 0, 0}, /*DDR3_800E*/
-
- {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), 0}, /*DDR3_1066E*/
- {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), 0}, /*DDR3_1066F*/
- {((5 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), 0}, /*DDR3_1066G*/
-
- {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)}, /*DDR3_1333F*/
- {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_1333G*/
- {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_1333H*/
- {((5 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)}, /*DDR3_1333J*/
-
- {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)}, /*DDR3_1600G*/
- {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_1600H*/
- {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_1600J*/
- {((5 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((10 << 16) | 7)}, /*DDR3_1600K*/
-
- {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_1866J*/
- {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_1866K*/
- {((6 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_1866L*/
- {((6 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)}, /*DDR3_1866M*/
-
- {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((7 << 16) | 7)}, /*DDR3_2133K*/
- {((5 << 16) | 5), ((5 << 16) | 5), ((6 << 16) | 6), ((8 << 16) | 7)}, /*DDR3_2133L*/
- {((5 << 16) | 5), ((5 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_2133M*/
- {((6 << 16) | 5), ((6 << 16) | 5), ((7 << 16) | 6), ((9 << 16) | 7)}, /*DDR3_2133N*/
-
- {((6 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)} /*DDR3_DEFAULT*/
-};
-
-static const uint32_t ddr3_tRC_tFAW[22] = {
-/** tRC tFAW */
- ((50 << 16) | 50), /*DDR3_800D*/
- ((53 << 16) | 50), /*DDR3_800E*/
-
- ((49 << 16) | 50), /*DDR3_1066E*/
- ((51 << 16) | 50), /*DDR3_1066F*/
- ((53 << 16) | 50), /*DDR3_1066G*/
-
- ((47 << 16) | 45), /*DDR3_1333F*/
- ((48 << 16) | 45), /*DDR3_1333G*/
- ((50 << 16) | 45), /*DDR3_1333H*/
- ((51 << 16) | 45), /*DDR3_1333J*/
-
- ((45 << 16) | 40), /*DDR3_1600G*/
- ((47 << 16) | 40), /*DDR3_1600H*/
- ((48 << 16) | 40), /*DDR3_1600J*/
- ((49 << 16) | 40), /*DDR3_1600K*/
-
- ((45 << 16) | 35), /*DDR3_1866J*/
- ((46 << 16) | 35), /*DDR3_1866K*/
- ((47 << 16) | 35), /*DDR3_1866L*/
- ((48 << 16) | 35), /*DDR3_1866M*/
-
- ((44 << 16) | 35), /*DDR3_2133K*/
- ((45 << 16) | 35), /*DDR3_2133L*/
- ((46 << 16) | 35), /*DDR3_2133M*/
- ((47 << 16) | 35), /*DDR3_2133N*/
-
- ((53 << 16) | 50) /*DDR3_DEFAULT*/
-};
-
-/****************************************************************************
-*Internal sram us delay function
-*Cpu highest frequency is 1.6 GHz
-*1 cycle = 1/1.6 ns
-*1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
-******************************************************************************/
-volatile uint32 DEFINE_PIE_DATA(loops_per_us);
-#define LPJ_100MHZ 999456UL
-
-/*----------------------------------------------------------------------
-*Name : void __sramlocalfunc ddr_delayus(uint32_t us)
-*Desc : ddr ÑÓʱº¯Êý
-*Params : uint32_t us --ÑÓʱʱ¼ä
-*Return : void
-*Notes : loops_per_us Ϊȫ¾Ö±äÁ¿ ÐèÒª¸ù¾Ýarm freq¶ø¶¨
-*----------------------------------------------------------------------*/
-static void __sramfunc ddr_delayus(uint32 us)
-{
- do {
- volatile unsigned int i = (DATA(loops_per_us) * us);
- if (i < 7)
- i = 7;
- barrier();
- asm volatile (".align 4; 1: subs %0, %0, #1; bne 1b;":"+r" (i));
- } while (0);
-}
-
-/*----------------------------------------------------------------------
-*Name : __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
-*Desc : ddr ¿½±´¼Ä´æÆ÷º¯Êý
-*Params : pDest ->Ä¿±ê¼Ä´æÆ÷Ê×µØÖ·
-* pSrc ->Ô´±ê¼Ä´æÆ÷Ê×µØÖ·
-* words ->¿½±´³¤¶È
-*Return : void
-*Notes :
-*----------------------------------------------------------------------*/
-
-static __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
-{
- uint32 i;
-
- for (i = 0; i < words; i++) {
- pDest[i] = pSrc[i];
- }
-}
-
-/*----------------------------------------------------------------------
-*Name : __sramfunc void ddr_move_to_Lowpower_state(void)
-*Desc : pctl ½øÈë lowpower state
projects / firefly-linux-kernel-4.4.55.git / commitdiff