arch/arm/mach-rockchip/ddr_rk3036.c

   1 /*
   2  * arch/arm/mach-rk2928/ddr.c-- for ddr3&ddr2
   3  *
   4  * Function Driver for DDR controller
   5  *
   6  * Copyright (C) 2012 Fuzhou Rockchip Electronics Co.,Ltd
   7  * Author:
   8  * hcy@rock-chips.com
   9  * yk@rock-chips.com
  10  * typ@rock-chips.com
  11  *
  12  * v1.00
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/clk.h>
  19
  20 #include <asm/cacheflush.h>
  21 #include <asm/tlbflush.h>
  22 #include <linux/cpu.h>
  23 #include <dt-bindings/clock/ddr.h>
  24 #include <linux/rockchip/cpu_axi.h>
  25 #include <linux/rockchip/cru.h>
  26 #include <linux/rk_fb.h>
  27
  28
  29 typedef uint32_t uint32 ;
  30
  31
  32 #define DDR3_DDR2_DLL_DISABLE_FREQ    (300)  // ¿ÅÁ£dll disableµÄÆµÂÊ
  33 #define DDR3_DDR2_ODT_DISABLE_FREQ    (333)  //¿ÅÁ£odt disableµÄÆµÂÊ
  34 #define SR_IDLE                       (0x1)   //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
  35 #define PD_IDLE                       (0x40)  //unit:DDR clk cycle, and 0 for disable auto power-down
  36 #define PHY_ODT_DISABLE_FREQ          (333)  //¶¨ÒåÖ÷¿Ø¶Ëodt disableµÄÆµÂÊ
  37 #define PHY_DLL_DISABLE_FREQ          (266)  //¶¨ÒåÖ÷¿Ø¶Ëdll bypassµÄÆµÂÊ
  38
  39 #define ddr_print(x...) printk( "DDR DEBUG: " x )
  40
  41 #define SRAM_CODE_OFFSET        rockchip_sram_virt
  42 #define SRAM_SIZE               rockchip_sram_size
  43
  44
  45 /***********************************
  46  * DDR3 define
  47  ***********************************/
  48 //mr0 for ddr3
  49 #define DDR3_BL8          (0)
  50 #define DDR3_BC4_8        (1)
  51 #define DDR3_BC4          (2)
  52 #define DDR3_CL(n)        (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
  53 #define DDR3_WR(n)        (((n)&0x7)<<9)
  54 #define DDR3_DLL_RESET    (1<<8)
  55 #define DDR3_DLL_DeRESET  (0<<8)
  56
  57 //mr1 for ddr3
  58 #define DDR3_DLL_ENABLE    (0)
  59 #define DDR3_DLL_DISABLE   (1)
  60 #define DDR3_MR1_AL(n)  (((n)&0x7)<<3)
  61
  62 #define DDR3_DS_40            (0)
  63 #define DDR3_DS_34            (1<<1)
  64 #define DDR3_Rtt_Nom_DIS      (0)
  65 #define DDR3_Rtt_Nom_60       (1<<2)
  66 #define DDR3_Rtt_Nom_120      (1<<6)
  67 #define DDR3_Rtt_Nom_40       ((1<<2)|(1<<6))
  68
  69 //mr2 for ddr3
  70 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
  71 #define DDR3_Rtt_WR_DIS       (0)
  72 #define DDR3_Rtt_WR_60        (1<<9)
  73 #define DDR3_Rtt_WR_120       (2<<9)
  74
  75 #define DDR_PLL_REFDIV  (1)
  76 #define FBDIV(n)        ((0xFFF<<16) | (n&0xfff))
  77 #define REFDIV(n)       ((0x3F<<16) | (n&0x3f))
  78 #define POSTDIV1(n)     ((0x7<<(12+16)) | ((n&0x7)<<12))
  79 #define POSTDIV2(n)     ((0x7<<(6+16)) | ((n&0x7)<<6))
  80
  81 #define PLL_LOCK_STATUS  (0x1<<10)
  82  //CRU Registers
  83 typedef volatile struct tagCRU_STRUCT
  84 {
  85     uint32 CRU_PLL_CON[4][4];
  86     uint32 CRU_MODE_CON;
  87     uint32 CRU_CLKSEL_CON[35];
  88     uint32 CRU_CLKGATE_CON[10];
  89     uint32 reserved1[2];
  90     uint32 CRU_GLB_SRST_FST_VALUE;
  91     uint32 CRU_GLB_SRST_SND_VALUE;
  92     uint32 reserved2[2];
  93     uint32 CRU_SOFTRST_CON[9];
  94     uint32 CRU_MISC_CON;
  95     uint32 reserved3[2];
  96     uint32 CRU_GLB_CNT_TH;
  97     uint32 CRU_SDMMC_CON[2];
  98     uint32 CRU_SDIO_CON[2];
  99     uint32 CRU_EMMC_CON[2];
 100     uint32 reserved4;
 101     uint32 CRU_RST_ST;
 102     uint32 reserved5[(0x1f0-0x164)/4];
 103     uint32 CRU_PLL_MASK_CON;
 104 } CRU_REG, *pCRU_REG;
 105
 106 typedef struct tagGPIO_LH
 107 {
 108     uint32 GPIOL;
 109     uint32 GPIOH;
 110 }GPIO_LH_T;
 111
 112 typedef struct tagGPIO_IOMUX
 113 {
 114     uint32 GPIOA_IOMUX;
 115     uint32 GPIOB_IOMUX;
 116     uint32 GPIOC_IOMUX;
 117     uint32 GPIOD_IOMUX;
 118 }GPIO_IOMUX_T;
 119
 120 /********************************
 121 GRF ¼Ä´æÆ÷ÖÐGRF_OS_REG1 ´æddr rank£¬typeµÈÐÅÏ¢
 122 GRF_SOC_CON2¼Ä´æÆ÷ÖÐ¿ØÖÆc_sysreqÐÅºÅÏòpctl·¢ËÍ½øÈëlow power ÇëÇó
 123 GRF_DDRC_STAT ¿É²éÑ¯pctlÊÇ·ñ½ÓÊÜÇëÇó ½øÈëlow power
 124 ********************************/
 125 //REG FILE registers
 126 //GRF_SOC_STATUS0
 127 #define sys_pwr_idle     (1<<27)
 128 #define gpu_pwr_idle     (1<<26)
 129 #define vpu_pwr_idle     (1<<25)
 130 #define vio_pwr_idle     (1<<24)
 131 #define peri_pwr_idle    (1<<23)
 132 #define core_pwr_idle     (1<<22)
 133 //GRF_SOC_CON2
 134 #define core_pwr_idlereq    (13)
 135 #define peri_pwr_idlereq    (12)
 136 #define vio_pwr_idlereq     (11)
 137 #define vpu_pwr_idlereq     (10)
 138 #define gpu_pwr_idlereq     (9)
 139 #define sys_pwr_idlereq     (8)
 140
 141 typedef volatile struct tagREG_FILE
 142 {
 143     uint32 reserved0[(0xa8-0x0)/4];
 144     GPIO_IOMUX_T GRF_GPIO_IOMUX[3]; // 0x00a8
 145     uint32 reserved1[(0x100-0xd8)/4];
 146     uint32 GRF_GPIO_DS;             //0x100
 147     uint32 reserved2[(0x118-0x104)/4];
 148     GPIO_LH_T GRF_GPIO_PULL[3];     // 0x118
 149     uint32 reserved3[(0x140-0x130)/4];
 150     uint32 GRF_SOC_CON[3];          // 0x140
 151     uint32 GRF_SOC_STATUS0;
 152     //uint32 GRF_LVDS_CON0;
 153     uint32 reserved4;               //0x150
 154     uint32 GRF_SOC_CON3;
 155     uint32 reserved5[(0x15c-0x158)/4];
 156     uint32 GRF_DMAC_CON[3];        //0x15c
 157     uint32 reserved6[(0x17c-0x168)/4];
 158     uint32 GRF_UOC0_CON5;         //0x17c
 159     uint32 reserved7[(0x190-0x180)/4];
 160     uint32 GRF_UOC1_CON4;         //0x190
 161     uint32 GRF_UOC1_COM5;
 162     uint32 reserved8;
 163     uint32 GRF_DDRC_STAT;
 164     uint32 GRF_UOC_CON6;
 165     uint32 GRF_SOC_STATUS1;
 166     uint32 GRF_CPU_CON[4];
 167     uint32 reserved9[(0x1c0-0x1b8)/4];
 168     uint32 GRF_CPU_STATUS[2];
 169     uint32 GRF_OS_REG[8];
 170     uint32 reserved10[(0x200-0x1e8)/4];
 171     uint32 GRF_DLL_CON[4];          //0X200
 172     uint32 GRF_DLL_STATUS[4];
 173     //uint32 reserved10[(0x220-0x214)/4];
 174     uint32 GRF_DFI_WRNUM;           //0X220
 175     uint32 GRF_DFI_RDNUM;
 176     uint32 GRF_DFI_ACTNUM;
 177     uint32 GRF_DFI_TIMERVAL;
 178     uint32 GRF_NIF_FIFO[4];
 179     uint32 reserved11[(0x280-0x240)/4];
 180     uint32 GRF_USBPHY0_CON[8];
 181     uint32 GRF_USBPHY1_CON[8];
 182     uint32 reserved12[(0x300-0x2c0)/4];
 183     uint32 GRF_CHIP_TAG;
 184     uint32 GRF_SDMMC_DET_CNT;
 185 } REG_FILE, *pREG_FILE;
 186
 187 //SCTL
 188 #define INIT_STATE                     (0)
 189 #define CFG_STATE                      (1)
 190 #define GO_STATE                       (2)
 191 #define SLEEP_STATE                    (3)
 192 #define WAKEUP_STATE                   (4)
 193
 194 //STAT
 195 #define Init_mem                       (0)
 196 #define Config                         (1)
 197 #define Config_req                     (2)
 198 #define Access                         (3)
 199 #define Access_req                     (4)
 200 #define Low_power                      (5)
 201 #define Low_power_entry_req            (6)
 202 #define Low_power_exit_req             (7)
 203
 204 //MCFG
 205 #define mddr_lpddr2_clk_stop_idle(n)   ((n)<<24)
 206 #define pd_idle(n)                     ((n)<<8)
 207 #define mddr_en                        (2<<22)
 208 #define lpddr2_en                      (3<<22)
 209 #define ddr2_en                        (0<<5)
 210 #define ddr3_en                        (1<<5)
 211 #define lpddr2_s2                      (0<<6)
 212 #define lpddr2_s4                      (1<<6)
 213 #define mddr_lpddr2_bl_2               (0<<20)
 214 #define mddr_lpddr2_bl_4               (1<<20)
 215 #define mddr_lpddr2_bl_8               (2<<20)
 216 #define mddr_lpddr2_bl_16              (3<<20)
 217 #define ddr2_ddr3_bl_4                 (0)
 218 #define ddr2_ddr3_bl_8                 (1)
 219 #define tfaw_cfg(n)                    (((n)-4)<<18)
 220 #define pd_exit_slow                   (0<<17)
 221 #define pd_exit_fast                   (1<<17)
 222 #define pd_type(n)                     ((n)<<16)
 223 #define two_t_en(n)                    ((n)<<3)
 224 #define bl8int_en(n)                   ((n)<<2)
 225 #define cke_or_en(n)                   ((n)<<1)
 226
 227 //POWCTL
 228 #define power_up_start                 (1<<0)
 229
 230 //POWSTAT
 231 #define power_up_done                  (1<<0)
 232
 233 //DFISTSTAT0
 234 #define dfi_init_complete              (1<<0)
 235
 236 //CMDTSTAT
 237 #define cmd_tstat                      (1<<0)
 238
 239 //CMDTSTATEN
 240 #define cmd_tstat_en                   (1<<1)
 241
 242 //MCMD
 243 #define Deselect_cmd                   (0)
 244 #define PREA_cmd                       (1)
 245 #define REF_cmd                        (2)
 246 #define MRS_cmd                        (3)
 247 #define ZQCS_cmd                       (4)
 248 #define ZQCL_cmd                       (5)
 249 #define RSTL_cmd                       (6)
 250 #define MRR_cmd                        (8)
 251 #define DPDE_cmd                       (9)
 252
 253 #define lpddr2_op(n)                   ((n)<<12)
 254 #define lpddr2_ma(n)                   ((n)<<4)
 255
 256 #define bank_addr(n)                   ((n)<<17)
 257 #define cmd_addr(n)                    ((n)<<4)
 258
 259 #define start_cmd                      (1u<<31)
 260
 261 typedef union STAT_Tag
 262 {
 263     uint32 d32;
 264     struct
 265     {
 266         unsigned ctl_stat : 3;
 267         unsigned reserved3 : 1;
 268         unsigned lp_trig : 3;
 269         unsigned reserved7_31 : 25;
 270     }b;
 271 }STAT_T;
 272
 273 typedef union SCFG_Tag
 274 {
 275     uint32 d32;
 276     struct
 277     {
 278         unsigned hw_low_power_en : 1;
 279         unsigned reserved1_5 : 5;
 280         unsigned nfifo_nif1_dis : 1;
 281         unsigned reserved7 : 1;
 282         unsigned bbflags_timing : 4;
 283         unsigned reserved12_31 : 20;
 284     } b;
 285 }SCFG_T;
 286
 287 /* DDR Controller register struct */
 288 typedef volatile struct DDR_REG_Tag
 289 {
 290     //Operational State, Control, and Status Registers
 291     SCFG_T SCFG;                   //State Configuration Register
 292     volatile uint32 SCTL;                   //State Control Register
 293     STAT_T STAT;                   //State Status Register
 294     volatile uint32 INTRSTAT;               //Interrupt Status Register
 295     uint32 reserved0[(0x40-0x10)/4];
 296     //Initailization Control and Status Registers
 297     volatile uint32 MCMD;                   //Memory Command Register
 298     volatile uint32 POWCTL;                 //Power Up Control Registers
 299     volatile uint32 POWSTAT;                //Power Up Status Register
 300     volatile uint32 CMDTSTAT;               //Command Timing Status Register
 301     volatile uint32 CMDTSTATEN;             //Command Timing Status Enable Register
 302     uint32 reserved1[(0x60-0x54)/4];
 303     volatile uint32 MRRCFG0;                //MRR Configuration 0 Register
 304     volatile uint32 MRRSTAT0;               //MRR Status 0 Register
 305     volatile uint32 MRRSTAT1;               //MRR Status 1 Register
 306     uint32 reserved2[(0x7c-0x6c)/4];
 307     //Memory Control and Status Registers
 308     volatile uint32 MCFG1;                  //Memory Configuration 1 Register
 309     volatile uint32 MCFG;                   //Memory Configuration Register
 310     volatile uint32 PPCFG;                  //Partially Populated Memories Configuration Register
 311     volatile uint32 MSTAT;                  //Memory Status Register
 312     volatile uint32 LPDDR2ZQCFG;            //LPDDR2 ZQ Configuration Register
 313     uint32 reserved3;
 314     //DTU Control and Status Registers
 315     volatile uint32 DTUPDES;                //DTU Status Register
 316     volatile uint32 DTUNA;                  //DTU Number of Random Addresses Created Register
 317     volatile uint32 DTUNE;                  //DTU Number of Errors Register
 318     volatile uint32 DTUPRD0;                //DTU Parallel Read 0
 319     volatile uint32 DTUPRD1;                //DTU Parallel Read 1
 320     volatile uint32 DTUPRD2;                //DTU Parallel Read 2
 321     volatile uint32 DTUPRD3;                //DTU Parallel Read 3
 322     volatile uint32 DTUAWDT;                //DTU Address Width
 323     uint32 reserved4[(0xc0-0xb4)/4];
 324     //Memory Timing Registers
 325     volatile uint32 TOGCNT1U;               //Toggle Counter 1U Register
 326     volatile uint32 TINIT;                  //t_init Timing Register
 327     volatile uint32 TRSTH;                  //Reset High Time Register
 328     volatile uint32 TOGCNT100N;             //Toggle Counter 100N Register
 329     volatile uint32 TREFI;                  //t_refi Timing Register
 330     volatile uint32 TMRD;                   //t_mrd Timing Register
 331     volatile uint32 TRFC;                   //t_rfc Timing Register
 332     volatile uint32 TRP;                    //t_rp Timing Register
 333     volatile uint32 TRTW;                   //t_rtw Timing Register
 334     volatile uint32 TAL;                    //AL Latency Register
 335     volatile uint32 TCL;                    //CL Timing Register
 336     volatile uint32 TCWL;                   //CWL Register
 337     volatile uint32 TRAS;                   //t_ras Timing Register
 338     volatile uint32 TRC;                    //t_rc Timing Register
 339     volatile uint32 TRCD;                   //t_rcd Timing Register
 340     volatile uint32 TRRD;                   //t_rrd Timing Register
 341     volatile uint32 TRTP;                   //t_rtp Timing Register
 342     volatile uint32 TWR;                    //t_wr Timing Register
 343     volatile uint32 TWTR;                   //t_wtr Timing Register
 344     volatile uint32 TEXSR;                  //t_exsr Timing Register
 345     volatile uint32 TXP;                    //t_xp Timing Register
 346     volatile uint32 TXPDLL;                 //t_xpdll Timing Register
 347     volatile uint32 TZQCS;                  //t_zqcs Timing Register
 348     volatile uint32 TZQCSI;                 //t_zqcsi Timing Register
 349     volatile uint32 TDQS;                   //t_dqs Timing Register
 350     volatile uint32 TCKSRE;                 //t_cksre Timing Register
 351     volatile uint32 TCKSRX;                 //t_cksrx Timing Register
 352     volatile uint32 TCKE;                   //t_cke Timing Register
 353     volatile uint32 TMOD;                   //t_mod Timing Register
 354     volatile uint32 TRSTL;                  //Reset Low Timing Register
 355     volatile uint32 TZQCL;                  //t_zqcl Timing Register
 356     volatile uint32 TMRR;                   //t_mrr Timing Register
 357     volatile uint32 TCKESR;                 //t_ckesr Timing Register
 358     volatile uint32 TDPD;                   //t_dpd Timing Register
 359     uint32 reserved5[(0x180-0x148)/4];
 360     //ECC Configuration, Control, and Status Registers
 361     volatile uint32 ECCCFG;                   //ECC Configuration Register
 362     volatile uint32 ECCTST;                   //ECC Test Register
 363     volatile uint32 ECCCLR;                   //ECC Clear Register
 364     volatile uint32 ECCLOG;                   //ECC Log Register
 365     uint32 reserved6[(0x200-0x190)/4];
 366     //DTU Control and Status Registers
 367     volatile uint32 DTUWACTL;                 //DTU Write Address Control Register
 368     volatile uint32 DTURACTL;                 //DTU Read Address Control Register
 369     volatile uint32 DTUCFG;                   //DTU Configuration Control Register
 370     volatile uint32 DTUECTL;                  //DTU Execute Control Register
 371     volatile uint32 DTUWD0;                   //DTU Write Data 0
 372     volatile uint32 DTUWD1;                   //DTU Write Data 1
 373     volatile uint32 DTUWD2;                   //DTU Write Data 2
 374     volatile uint32 DTUWD3;                   //DTU Write Data 3
 375     volatile uint32 DTUWDM;                   //DTU Write Data Mask
 376     volatile uint32 DTURD0;                   //DTU Read Data 0
 377     volatile uint32 DTURD1;                   //DTU Read Data 1
 378     volatile uint32 DTURD2;                   //DTU Read Data 2
 379     volatile uint32 DTURD3;                   //DTU Read Data 3
 380     volatile uint32 DTULFSRWD;                //DTU LFSR Seed for Write Data Generation
 381     volatile uint32 DTULFSRRD;                //DTU LFSR Seed for Read Data Generation
 382     volatile uint32 DTUEAF;                   //DTU Error Address FIFO
 383     //DFI Control Registers
 384     volatile uint32 DFITCTRLDELAY;            //DFI tctrl_delay Register
 385     volatile uint32 DFIODTCFG;                //DFI ODT Configuration Register
 386     volatile uint32 DFIODTCFG1;               //DFI ODT Configuration 1 Register
 387     volatile uint32 DFIODTRANKMAP;            //DFI ODT Rank Mapping Register
 388     //DFI Write Data Registers
 389     volatile uint32 DFITPHYWRDATA;            //DFI tphy_wrdata Register
 390     volatile uint32 DFITPHYWRLAT;             //DFI tphy_wrlat Register
 391     uint32 reserved7[(0x260-0x258)/4];
 392     volatile uint32 DFITRDDATAEN;             //DFI trddata_en Register
 393     volatile uint32 DFITPHYRDLAT;             //DFI tphy_rddata Register
 394     uint32 reserved8[(0x270-0x268)/4];
 395     //DFI Update Registers
 396     volatile uint32 DFITPHYUPDTYPE0;          //DFI tphyupd_type0 Register
 397     volatile uint32 DFITPHYUPDTYPE1;          //DFI tphyupd_type1 Register
 398     volatile uint32 DFITPHYUPDTYPE2;          //DFI tphyupd_type2 Register
 399     volatile uint32 DFITPHYUPDTYPE3;          //DFI tphyupd_type3 Register
 400     volatile uint32 DFITCTRLUPDMIN;           //DFI tctrlupd_min Register
 401     volatile uint32 DFITCTRLUPDMAX;           //DFI tctrlupd_max Register
 402     volatile uint32 DFITCTRLUPDDLY;           //DFI tctrlupd_dly Register
 403     uint32 reserved9;
 404     volatile uint32 DFIUPDCFG;                //DFI Update Configuration Register
 405     volatile uint32 DFITREFMSKI;              //DFI Masked Refresh Interval Register
 406     volatile uint32 DFITCTRLUPDI;             //DFI tctrlupd_interval Register
 407     uint32 reserved10[(0x2ac-0x29c)/4];
 408     volatile uint32 DFITRCFG0;                //DFI Training Configuration 0 Register
 409     volatile uint32 DFITRSTAT0;               //DFI Training Status 0 Register
 410     volatile uint32 DFITRWRLVLEN;             //DFI Training dfi_wrlvl_en Register
 411     volatile uint32 DFITRRDLVLEN;             //DFI Training dfi_rdlvl_en Register
 412     volatile uint32 DFITRRDLVLGATEEN;         //DFI Training dfi_rdlvl_gate_en Register
 413     //DFI Status Registers
 414     volatile uint32 DFISTSTAT0;               //DFI Status Status 0 Register
 415     volatile uint32 DFISTCFG0;                //DFI Status Configuration 0 Register
 416     volatile uint32 DFISTCFG1;                //DFI Status configuration 1 Register
 417     uint32 reserved11;
 418     volatile uint32 DFITDRAMCLKEN;            //DFI tdram_clk_enalbe Register
 419     volatile uint32 DFITDRAMCLKDIS;           //DFI tdram_clk_disalbe Register
 420     volatile uint32 DFISTCFG2;                //DFI Status configuration 2 Register
 421     volatile uint32 DFISTPARCLR;              //DFI Status Parity Clear Register
 422     volatile uint32 DFISTPARLOG;              //DFI Status Parity Log Register
 423     uint32 reserved12[(0x2f0-0x2e4)/4];
 424     //DFI Low Power Registers
 425     volatile uint32 DFILPCFG0;                //DFI Low Power Configuration 0 Register
 426     uint32 reserved13[(0x300-0x2f4)/4];
 427     //DFI Training 2 Registers
 428     volatile uint32 DFITRWRLVLRESP0;          //DFI Training dif_wrlvl_resp Status 0 Register
 429     volatile uint32 DFITRWRLVLRESP1;          //DFI Training dif_wrlvl_resp Status 1 Register
 430     volatile uint32 DFITRWRLVLRESP2;          //DFI Training dif_wrlvl_resp Status 2 Register
 431     volatile uint32 DFITRRDLVLRESP0;          //DFI Training dif_rdlvl_resp Status 0 Register
 432     volatile uint32 DFITRRDLVLRESP1;          //DFI Training dif_rdlvl_resp Status 1 Register
 433     volatile uint32 DFITRRDLVLRESP2;          //DFI Training dif_rdlvl_resp Status 2 Register
 434     volatile uint32 DFITRWRLVLDELAY0;         //DFI Training dif_wrlvl_delay Configuration 0 Register
 435     volatile uint32 DFITRWRLVLDELAY1;         //DFI Training dif_wrlvl_delay Configuration 1 Register
 436     volatile uint32 DFITRWRLVLDELAY2;         //DFI Training dif_wrlvl_delay Configuration 2 Register
 437     volatile uint32 DFITRRDLVLDELAY0;         //DFI Training dif_rdlvl_delay Configuration 0 Register
 438     volatile uint32 DFITRRDLVLDELAY1;         //DFI Training dif_rdlvl_delay Configuration 1 Register
 439     volatile uint32 DFITRRDLVLDELAY2;         //DFI Training dif_rdlvl_delay Configuration 2 Register
 440     volatile uint32 DFITRRDLVLGATEDELAY0;     //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
 441     volatile uint32 DFITRRDLVLGATEDELAY1;     //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
 442     volatile uint32 DFITRRDLVLGATEDELAY2;     //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
 443     volatile uint32 DFITRCMD;                 //DFI Training Command Register
 444     uint32 reserved14[(0x3f8-0x340)/4];
 445     //IP Status Registers
 446     volatile uint32 IPVR;                     //IP Version Register
 447     volatile uint32 IPTR;                     //IP Type Register
 448 }DDR_REG_T, *pDDR_REG_T;
 449
 450 //PHY_REG2
 451 #define PHY_AUTO_CALIBRATION (1<<0)
 452 #define PHY_SW_CALIBRATION   (1<<1)
 453 #define PHY_MEM_TYPE         (6)
 454
 455 //PHY_REG22,25,26,27,28
 456 #define PHY_RON_DISABLE     (0)
 457 #define PHY_RON_309ohm      (1)
 458 #define PHY_RON_155ohm      (2)
 459 #define PHY_RON_103ohm      (3)
 460 #define PHY_RON_77ohm       (4)
 461 #define PHY_RON_63ohm       (5)
 462 #define PHY_RON_52ohm       (6)
 463 #define PHY_RON_45ohm       (7)
 464 //#define PHY_RON_77ohm       (8)
 465 #define PHY_RON_62ohm       (9)
 466 //#define PHY_RON_52ohm       (10)
 467 #define PHY_RON_44ohm       (11)
 468 #define PHY_RON_39ohm       (12)
 469 #define PHY_RON_34ohm       (13)
 470 #define PHY_RON_31ohm       (14)
 471 #define PHY_RON_28ohm       (15)
 472
 473 #define PHY_RTT_DISABLE     (0)
 474 #define PHY_RTT_816ohm      (1)
 475 #define PHY_RTT_431ohm      (2)
 476 #define PHY_RTT_287ohm      (3)
 477 #define PHY_RTT_216ohm      (4)
 478 #define PHY_RTT_172ohm      (5)
 479 #define PHY_RTT_145ohm      (6)
 480 #define PHY_RTT_124ohm      (7)
 481 #define PHY_RTT_215ohm      (8)
 482 //#define PHY_RTT_172ohm      (9)
 483 #define PHY_RTT_144ohm      (10)
 484 #define PHY_RTT_123ohm      (11)
 485 #define PHY_RTT_108ohm      (12)
 486 #define PHY_RTT_96ohm       (13)
 487 #define PHY_RTT_86ohm       (14)
 488 #define PHY_RTT_78ohm       (15)
 489
 490 /* DDR PHY register struct */
 491 typedef volatile struct DDRPHY_REG_Tag
 492 {
 493     volatile uint32 PHY_REG1;               //PHY soft reset Register
 494     volatile uint32 PHY_REG3;               //Burst type select Register
 495     volatile uint32 PHY_REG2;               //PHY DQS squelch calibration Register
 496     uint32 reserved1[(0x38-0x0a)/4];
 497     volatile uint32 PHY_REG4a;              //CL,AL set register
 498     volatile uint32 PHY_REG4b;              //dqs gata delay select bypass mode register
 499     uint32 reserved2[(0x54-0x40)/4];
 500     volatile uint32 PHY_REG16;              //
 501     uint32 reserved3[(0x5c-0x58)/4];
 502     volatile uint32 PHY_REG18;              //0x5c
 503     volatile uint32 PHY_REG19;
 504     uint32 reserved4[(0x68-0x64)/4];
 505     volatile uint32 PHY_REG21;              //0x68
 506     uint32 reserved5[(0x70-0x6c)/4];
 507     volatile uint32 PHY_REG22;              //0x70
 508     uint32 reserved6[(0x80-0x74)/4];
 509     volatile uint32 PHY_REG25;              //0x80
 510     volatile uint32 PHY_REG26;
 511     volatile uint32 PHY_REG27;
 512     volatile uint32 PHY_REG28;
 513     uint32 reserved7[(0xd4-0x90)/4];
 514     volatile uint32 PHY_REG6;               //0xd4
 515     volatile uint32 PHY_REG7;
 516     uint32 reserved8[(0xe0-0xdc)/4];
 517     volatile uint32 PHY_REG8;               //0xe0
 518     volatile uint32 PHY_REG0e4;             //use for DQS ODT off
 519     uint32 reserved9[(0x114-0xe8)/4];
 520     volatile uint32 PHY_REG9;               //0x114
 521     volatile uint32 PHY_REG10;
 522     uint32 reserved10[(0x120-0x11c)/4];
 523     volatile uint32 PHY_REG11;              //0x120
 524     volatile uint32 PHY_REG124;             //use for DQS ODT off
 525     uint32 reserved11[(0x1c0-0x128)/4];
 526     volatile uint32 PHY_REG29;              //0x1c0
 527     uint32 reserved12[(0x264-0x1c4)/4];
 528         volatile uint32 PHY_REG264;             //use for phy soft reset
 529         uint32 reserved13[(0x2b0-0x268)/4];
 530     volatile uint32 PHY_REG2a;              //0x2b0
 531     uint32 reserved14[(0x2c4-0x2b4)/4];
 532 //    volatile uint32 PHY_TX_DeSkew[24];        //0x2c4-0x320
 533     volatile uint32 PHY_REG30;
 534     volatile uint32 PHY_REG31;
 535     volatile uint32 PHY_REG32;
 536     volatile uint32 PHY_REG33;
 537     volatile uint32 PHY_REG34;
 538     volatile uint32 PHY_REG35;
 539     volatile uint32 PHY_REG36;
 540     volatile uint32 PHY_REG37;
 541     volatile uint32 PHY_REG38;
 542     volatile uint32 PHY_REG39;
 543     volatile uint32 PHY_REG40;
 544     volatile uint32 PHY_REG41;
 545     volatile uint32 PHY_REG42;
 546     volatile uint32 PHY_REG43;
 547     volatile uint32 PHY_REG44;
 548     volatile uint32 PHY_REG45;
 549     volatile uint32 PHY_REG46;
 550     volatile uint32 PHY_REG47;
 551     volatile uint32 PHY_REG48;
 552     volatile uint32 PHY_REG49;
 553     volatile uint32 PHY_REG50;
 554     volatile uint32 PHY_REG51;
 555     volatile uint32 PHY_REG52;
 556     volatile uint32 PHY_REG53;
 557     uint32 reserved15[(0x328-0x324)/4];
 558 //    volatile uint32 PHY_RX_DeSkew[11];      //0x328-0x350
 559     volatile uint32 PHY_REG54;
 560     volatile uint32 PHY_REG55;
 561     volatile uint32 PHY_REG56;
 562     volatile uint32 PHY_REG57;
 563     volatile uint32 PHY_REG58;
 564     volatile uint32 PHY_REG59;
 565     volatile uint32 PHY_REG5a;
 566     volatile uint32 PHY_REG5b;
 567     volatile uint32 PHY_REG5c;
 568     volatile uint32 PHY_REG5d;
 569     volatile uint32 PHY_REG5e;
 570     uint32 reserved16[(0x3c4-0x354)/4];
 571     volatile uint32 PHY_REG5f;              //0x3c4
 572     uint32 reserved17[(0x3e0-0x3c8)/4];
 573     volatile uint32 PHY_REG60;
 574     volatile uint32 PHY_REG61;
 575     volatile uint32 PHY_REG62;
 576 }DDRPHY_REG_T, *pDDRPHY_REG_T;
 577
 578 #define pCRU_Reg               ((pCRU_REG)RK_CRU_VIRT)
 579 #define pGRF_Reg               ((pREG_FILE)RK_GRF_VIRT)
 580 #define pDDR_Reg               ((pDDR_REG_T)RK_DDR_VIRT)
 581 #define pPHY_Reg               ((pDDRPHY_REG_T)(RK_DDR_VIRT+RK3036_DDR_PCTL_SIZE))
 582 #define SysSrv_DdrTiming       (RK_CPU_AXI_BUS_VIRT+0xc)
 583 #define READ_CS_INFO()   ((((pGRF_Reg->GRF_OS_REG[1])>>11)&0x1)+1)
 584 #define READ_COL_INFO()  (9+(((pGRF_Reg->GRF_OS_REG[1])>>9)&0x3))
 585 #define READ_BK_INFO()   (3-(((pGRF_Reg->GRF_OS_REG[1])>>8)&0x1))
 586 #define READ_CS0_ROW_INFO()  (13+(((pGRF_Reg->GRF_OS_REG[1])>>6)&0x3))
 587 #define READ_CS1_ROW_INFO()  (13+(((pGRF_Reg->GRF_OS_REG[1])>>4)&0x3))
 588 #define READ_BW_INFO()   (2>>(((pGRF_Reg->GRF_OS_REG[1])&0xc)>>2))    //´úÂëÖÐ 0->8bit 1->16bit 2->32bit  ÓëgrfÖÐ¶¨ÒåÏà·´
 589 #define READ_DIE_BW_INFO()   (2>>((pGRF_Reg->GRF_OS_REG[1])&0x3))
 590
 591 typedef enum PLL_ID_Tag
 592 {
 593     APLL=0,
 594     DPLL,
 595     CPLL,
 596     GPLL,
 597     PLL_MAX
 598 }PLL_ID;
 599
 600 typedef enum DRAM_TYPE_Tag
 601 {
 602     LPDDR = 0,
 603     DDR,
 604     DDR2,
 605     DDR3,
 606     LPDDR2_S2,
 607     LPDDR2_S4,
 608
 609     DRAM_MAX
 610 }DRAM_TYPE;
 611
 612 struct ddr_freq_t {
 613     unsigned long screen_ft_us;
 614     unsigned long long t0;
 615     unsigned long long t1;
 616     unsigned long t2;
 617 };
 618
 619
 620 typedef struct PCTRL_TIMING_Tag
 621 {
 622     uint32 ddrFreq;
 623     //Memory Timing Registers
 624     uint32 togcnt1u;               //Toggle Counter 1U Register
 625     uint32 tinit;                  //t_init Timing Register
 626     uint32 trsth;                  //Reset High Time Register
 627     uint32 togcnt100n;             //Toggle Counter 100N Register
 628     uint32 trefi;                  //t_refi Timing Register
 629     uint32 tmrd;                   //t_mrd Timing Register
 630     uint32 trfc;                   //t_rfc Timing Register
 631     uint32 trp;                    //t_rp Timing Register
 632     uint32 trtw;                   //t_rtw Timing Register
 633     uint32 tal;                    //AL Latency Register
 634     uint32 tcl;                    //CL Timing Register
 635     uint32 tcwl;                   //CWL Register
 636     uint32 tras;                   //t_ras Timing Register
 637     uint32 trc;                    //t_rc Timing Register
 638     uint32 trcd;                   //t_rcd Timing Register
 639     uint32 trrd;                   //t_rrd Timing Register
 640     uint32 trtp;                   //t_rtp Timing Register
 641     uint32 twr;                    //t_wr Timing Register
 642     uint32 twtr;                   //t_wtr Timing Register
 643     uint32 texsr;                  //t_exsr Timing Register
 644     uint32 txp;                    //t_xp Timing Register
 645     uint32 txpdll;                 //t_xpdll Timing Register
 646     uint32 tzqcs;                  //t_zqcs Timing Register
 647     uint32 tzqcsi;                 //t_zqcsi Timing Register
 648     uint32 tdqs;                   //t_dqs Timing Register
 649     uint32 tcksre;                 //t_cksre Timing Register
 650     uint32 tcksrx;                 //t_cksrx Timing Register
 651     uint32 tcke;                   //t_cke Timing Register
 652     uint32 tmod;                   //t_mod Timing Register
 653     uint32 trstl;                  //Reset Low Timing Register
 654     uint32 tzqcl;                  //t_zqcl Timing Register
 655     uint32 tmrr;                   //t_mrr Timing Register
 656     uint32 tckesr;                 //t_ckesr Timing Register
 657     uint32 tdpd;                   //t_dpd Timing Register
 658 }PCTL_TIMING_T;
 659
 660 struct ddr_change_freq_sram_param {
 661     uint32 freq;
 662     uint32 freq_slew;
 663 };
 664
 665
 666 typedef union NOC_TIMING_Tag
 667 {
 668     uint32 d32;
 669     struct
 670     {
 671         unsigned ActToAct : 6;
 672         unsigned RdToMiss : 6;
 673         unsigned WrToMiss : 6;
 674         unsigned BurstLen : 3;
 675         unsigned RdToWr : 5;
 676         unsigned WrToRd : 5;
 677         unsigned BwRatio : 1;
 678     } b;
 679 }NOC_TIMING_T;
 680
 681 typedef struct BACKUP_REG_Tag
 682 {
 683     PCTL_TIMING_T pctl_timing;
 684     NOC_TIMING_T noc_timing;
 685     uint32 ddrMR[4];
 686     uint32 mem_type;
 687     uint32 ddr_speed_bin;
 688     uint32 ddr_capability_per_die;
 689 }BACKUP_REG_T;
 690
 691 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
 692 static BACKUP_REG_T *p_ddr_reg;
 693
 694 uint32 DEFINE_PIE_DATA(ddr_freq);
 695 static uint32 *p_ddr_freq;
 696 uint32 DEFINE_PIE_DATA(ddr_sr_idle);
 697 uint32 DEFINE_PIE_DATA(ddr_dll_status);  // ¼ÇÂ¼ddr dllµÄ×´Ì¬£¬ÔÚselfrefresh exitÊ±Ñ¡ÔñÊÇ·ñ½øÐÐdll reset
 698
 699
 700
 701 static uint32_t  ddr3_cl_cwl[22][4]={
 702 /*   0~330           330~400         400~533        speed
 703 * tCK  >3             2.5~3          1.875~2.5     1.875~1.5
 704 *    cl<<16, cwl    cl<<16, cwl     cl<<16, cwl              */
 705     {((5<<16)|5),   ((5<<16)|5),    0          ,   0}, //DDR3_800D
 706     {((5<<16)|5),   ((6<<16)|5),    0          ,   0}, //DDR3_800E
 707
 708     {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   0}, //DDR3_1066E
 709     {((5<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   0}, //DDR3_1066F
 710     {((5<<16)|5),   ((6<<16)|5),    ((8<<16)|6),   0}, //DDR3_1066G
 711
 712     {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((7<<16)|7)}, //DDR3_1333F
 713     {((5<<16)|5),   ((5<<16)|5),    ((7<<16)|6),   ((8<<16)|7)}, //DDR3_1333G
 714     {((5<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   ((9<<16)|7)}, //DDR3_1333H
 715     {((5<<16)|5),   ((6<<16)|5),    ((8<<16)|6),   ((10<<16)|7)}, //DDR3_1333J
 716
 717     {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((7<<16)|7)}, //DDR3_1600G
 718     {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((8<<16)|7)}, //DDR3_1600H
 719     {((5<<16)|5),   ((5<<16)|5),    ((7<<16)|6),   ((9<<16)|7)}, //DDR3_1600J
 720     {((5<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   ((10<<16)|7)}, //DDR3_1600K
 721
 722     {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((8<<16)|7)}, //DDR3_1866J
 723     {((5<<16)|5),   ((5<<16)|5),    ((7<<16)|6),   ((8<<16)|7)}, //DDR3_1866K
 724     {((6<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   ((9<<16)|7)}, //DDR3_1866L
 725     {((6<<16)|5),   ((6<<16)|5),    ((8<<16)|6),   ((10<<16)|7)}, //DDR3_1866M
 726
 727     {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((7<<16)|7)}, //DDR3_2133K
 728     {((5<<16)|5),   ((5<<16)|5),    ((6<<16)|6),   ((8<<16)|7)}, //DDR3_2133L
 729     {((5<<16)|5),   ((5<<16)|5),    ((7<<16)|6),   ((9<<16)|7)}, //DDR3_2133M
 730     {((6<<16)|5),   ((6<<16)|5),    ((7<<16)|6),   ((9<<16)|7)},  //DDR3_2133N
 731
 732     {((6<<16)|5),   ((6<<16)|5),    ((8<<16)|6),   ((10<<16)|7)} //DDR3_DEFAULT
 733
 734 };
 735 static uint32_t  ddr3_tRC_tFAW[22]={
 736 /**    tRC    tFAW   */
 737     ((50<<16)|50), //DDR3_800D
 738     ((53<<16)|50), //DDR3_800E
 739
 740     ((49<<16)|50), //DDR3_1066E
 741     ((51<<16)|50), //DDR3_1066F
 742     ((53<<16)|50), //DDR3_1066G
 743
 744     ((47<<16)|45), //DDR3_1333F
 745     ((48<<16)|45), //DDR3_1333G
 746     ((50<<16)|45), //DDR3_1333H
 747     ((51<<16)|45), //DDR3_1333J
 748
 749     ((45<<16)|40), //DDR3_1600G
 750     ((47<<16)|40), //DDR3_1600H
 751     ((48<<16)|40), //DDR3_1600J
 752     ((49<<16)|40), //DDR3_1600K
 753
 754     ((45<<16)|35), //DDR3_1866J
 755     ((46<<16)|35), //DDR3_1866K
 756     ((47<<16)|35), //DDR3_1866L
 757     ((48<<16)|35), //DDR3_1866M
 758
 759     ((44<<16)|35), //DDR3_2133K
 760     ((45<<16)|35), //DDR3_2133L
 761     ((46<<16)|35), //DDR3_2133M
 762     ((47<<16)|35), //DDR3_2133N
 763
 764     ((53<<16)|50)  //DDR3_DEFAULT
 765 };
 766
 767
 768 /****************************************************************************
 769 Internal sram us delay function
 770 Cpu highest frequency is 1.6 GHz
 771 1 cycle = 1/1.6 ns
 772 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
 773 *****************************************************************************/
 774 //__sramdata volatile uint32 loops_per_us;
 775 volatile uint32 DEFINE_PIE_DATA(loops_per_us);
 776 #define LPJ_100MHZ  999456UL
 777
 778 /*----------------------------------------------------------------------
 779 Name    : void __sramlocalfunc ddr_delayus(uint32_t us)
 780 Desc    : ddr ÑÓÊ±º¯Êý
 781 Params  : uint32_t us  --ÑÓÊ±Ê±¼ä
 782 Return  : void
 783 Notes   : loops_per_us ÎªÈ«¾Ö±äÁ¿ ÐèÒª¸ù¾Ýarm freq¶ø¶¨
 784 ----------------------------------------------------------------------*/
 785 static void __sramfunc ddr_delayus(uint32 us)
 786 {
 787     do
 788     {
 789         volatile unsigned int i = (DATA(loops_per_us)*us);
 790         if (i < 7) i = 7;
 791         barrier();
 792         asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
 793     } while (0);
 794 }
 795
 796
 797 /*----------------------------------------------------------------------
 798 Name    : __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
 799 Desc    : ddr ¿½±´¼Ä´æÆ÷º¯Êý
 800 Params  : pDest ->Ä¿±ê¼Ä´æÆ÷Ê×µØÖ·
 801           pSrc  ->Ô´±ê¼Ä´æÆ÷Ê×µØÖ·
 802           words ->¿½±´³¤¶È
 803 Return  : void
 804 Notes   :
 805 ----------------------------------------------------------------------*/
 806
 807 static __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
 808 {
 809     uint32 i;
 810
 811     for(i=0; i<words; i++)
 812     {
 813         pDest[i] = pSrc[i];
 814     }
 815 }
 816
 817 /*----------------------------------------------------------------------
 818 Name    : __sramfunc void ddr_move_to_Lowpower_state(void)
 819 Desc    : pctl ½øÈë lowpower state
 820 Params  : void
 821 Return  : void
 822 Notes   :
 823 ----------------------------------------------------------------------*/
 824 static __sramfunc void ddr_move_to_Lowpower_state(void)
 825 {
 826     volatile uint32 value;
 827
 828     while(1)
 829     {
 830         value = pDDR_Reg->STAT.b.ctl_stat;
 831         if(value == Low_power)
 832         {
 833             break;
 834         }
 835         switch(value)
 836         {
 837             case Init_mem:
 838                 pDDR_Reg->SCTL = CFG_STATE;
 839                 dsb();
 840                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
 841             case Config:
 842                 pDDR_Reg->SCTL = GO_STATE;
 843                 dsb();
 844                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
 845             case Access:
 846                 pDDR_Reg->SCTL = SLEEP_STATE;
 847                 dsb();
 848                 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
 849                 break;
 850             default:  //Transitional state
 851                 break;
 852         }
 853     }
 854 }
 855
 856 /*----------------------------------------------------------------------
 857 Name    : __sramfunc void ddr_move_to_Access_state(void)
 858 Desc    : pctl ½øÈë Access state
 859 Params  : void
 860 Return  : void
 861 Notes   :
 862 ----------------------------------------------------------------------*/
 863 static __sramfunc void ddr_move_to_Access_state(void)
 864 {
 865     volatile uint32 value;
 866
 867     //set auto self-refresh idle
 868     //pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)| DATA(ddr_sr_idle) | (1<<31);
 869         pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00)| 0 | (1<<31);
 870
 871     while(1)
 872     {
 873         value = pDDR_Reg->STAT.b.ctl_stat;
 874         if((value == Access)
 875            || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
 876         {
 877             break;
 878         }
 879         switch(value)
 880         {
 881             case Low_power:
 882                 pDDR_Reg->SCTL = WAKEUP_STATE;
 883                 dsb();
 884                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
 885                 break;
 886             case Init_mem:
 887                 pDDR_Reg->SCTL = CFG_STATE;
 888                 dsb();
 889                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
 890             case Config:
 891                 pDDR_Reg->SCTL = GO_STATE;
 892                 dsb();
 893                 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
 894                       || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
 895                 break;
 896             default:  //Transitional state
 897                 break;
 898         }
 899     }
 900     pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 0);//de_hw_wakeup :enable auto sr if sr_idle != 0
 901 }
 902
 903 /*----------------------------------------------------------------------
 904 Name    : __sramfunc void ddr_move_to_Config_state(void)
 905 Desc    : pctl ½øÈë config state
 906 Params  : void
 907 Return  : void
 908 Notes   :
 909 ----------------------------------------------------------------------*/
 910 static __sramfunc void ddr_move_to_Config_state(void)
 911 {
 912     volatile uint32 value;
 913     pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | 1); //hw_wakeup :disable auto sr
 914     while(1)
 915     {
 916         value = pDDR_Reg->STAT.b.ctl_stat;
 917         if(value == Config)
 918         {
 919             break;
 920         }
 921         switch(value)
 922         {
 923             case Low_power:
 924                 pDDR_Reg->SCTL = WAKEUP_STATE;
 925                 dsb();
 926             case Access:
 927             case Init_mem:
 928                 pDDR_Reg->SCTL = CFG_STATE;
 929                 dsb();
 930                 break;
 931             default:  //Transitional state
 932                 break;
 933         }
 934     }
 935 }
 936
 937 /*----------------------------------------------------------------------
 938 Name    : void __sramlocalfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
 939 Desc    : Í¨¹ýÐ´ pctl MCMD¼Ä´æÆ÷Ïòddr·¢ËÍÃüÁî
 940 Params  : rank ->ddr rank Êý
 941           cmd  ->·¢ËÍÃüÁîÀàÐÍ
 942           arg  ->·¢ËÍµÄÊý¾Ý
 943 Return  : void
 944 Notes   : arg°üÀ¨bank_addrºÍcmd_addr
 945 ----------------------------------------------------------------------*/
 946 static void __sramfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
 947 {
 948     pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
 949     dsb();
 950     while(pDDR_Reg->MCMD & start_cmd);
 951 }
 952
 953 __sramdata uint32 copy_data[8]={0xffffffff,0x00000000,0x55555555,0xAAAAAAAA,
 954                                 0xEEEEEEEE,0x11111111,0x22222222,0xDDDDDDDD};/**/
 955 EXPORT_PIE_SYMBOL(copy_data[8]);
 956 static uint32 * p_copy_data;
 957
 958 /*----------------------------------------------------------------------
 959 Name    : uint32_t __sramlocalfunc ddr_data_training(void)
 960 Desc    : ¶Ôddr×ödata training
 961 Params  : void
 962 Return  : void
 963 Notes   : Ã»ÓÐ×ödata trainingÐ£Ñé
 964 ----------------------------------------------------------------------*/
 965 static uint32_t __sramfunc ddr_data_training(void)
 966 {
 967     uint32 value;
 968     value = pDDR_Reg->TREFI;
 969     pDDR_Reg->TREFI = 0;
 970     // trigger DTT
 971     pPHY_Reg->PHY_REG2 = ((pPHY_Reg->PHY_REG2 & (~0x1)) | PHY_AUTO_CALIBRATION);
 972     // wait echo byte DTDONE
 973         dsb();
 974 //    ddr_delayus(1);
 975     // stop DTT
 976     while((pPHY_Reg->PHY_REG62 & 0x3)!=0x3);
 977     pPHY_Reg->PHY_REG2 = (pPHY_Reg->PHY_REG2 & (~0x1));
 978     // send some auto refresh to complement the lost while DTT
 979     ddr_send_command(3, REF_cmd, 0);
 980     ddr_send_command(3, REF_cmd, 0);
 981     ddr_send_command(3, REF_cmd, 0);
 982     ddr_send_command(3, REF_cmd, 0);
 983
 984     // resume auto refresh
 985     pDDR_Reg->TREFI = value;
 986
 987     return(0);
 988 }
 989
 990 /*----------------------------------------------------------------------
 991 Name    : void __sramlocalfunc ddr_set_dll_bypass(uint32 freq)
 992 Desc    : ÉèÖÃPHY dll ¹¤×÷Ä£Ê½
 993 Params  : freq -> ddr¹¤×÷ÆµÂÊ
 994 Return  : void
 995 Notes   :
 996 ----------------------------------------------------------------------*/
 997 static void __sramfunc ddr_set_dll_bypass(uint32 freq)
 998 {
 999     if(freq <= PHY_DLL_DISABLE_FREQ)
1000     {
1001         pPHY_Reg->PHY_REG2a = 0x1F;         //set cmd,left right dll bypass
1002         pPHY_Reg->PHY_REG19 = 0x08;         //cmd slave dll
1003         pPHY_Reg->PHY_REG6 = 0x18;          //left TX DQ DLL
1004         pPHY_Reg->PHY_REG7 = 0x00;          //left TX DQS DLL
1005         pPHY_Reg->PHY_REG9 = 0x18;          //right TX DQ DLL
1006         pPHY_Reg->PHY_REG10 = 0x00;         //right TX DQS DLL
1007
1008     }
1009     else
1010     {
1011         pPHY_Reg->PHY_REG2a = 0x03;         //set cmd,left right dll bypass
1012         pPHY_Reg->PHY_REG19 = 0x08;         //cmd slave dll
1013         pPHY_Reg->PHY_REG6 = 0x0c;          //left TX DQ DLL
1014         pPHY_Reg->PHY_REG7 = 0x00;          //left TX DQS DLL
1015         pPHY_Reg->PHY_REG9 = 0x0c;          //right TX DQ DLL
1016         pPHY_Reg->PHY_REG10 = 0x00;         //right TX DQS DLL
1017     }
1018     dsb();
1019     //ÆäËûÓëdllÏà¹ØµÄ¼Ä´æÆ÷ÓÐ:REG8(RX DQS),REG11(RX DQS),REG18(CMD),REG21(CK) ±£³ÖÄ¬ÈÏÖµ
1020 }
1021
1022 static noinline uint32 ddr_get_pll_freq(PLL_ID pll_id)   //APLL-1;CPLL-2;DPLL-3;GPLL-4
1023 {
1024     uint32 ret = 0;
1025
1026     // freq = (fin*fbdiv/(refdiv * postdiv1 * postdiv2))
1027     if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&1) == 1)             // DPLL Normal mode
1028         ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0xfff))    // NF = 2*(CLKF+1)
1029                 /((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0x3f)
1030                 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>12)&0x7)*((pCRU_Reg->CRU_PLL_CON[pll_id][1]>>6)&0x7));             // OD = 2^CLKOD
1031     else
1032         ret = 24;
1033
1034     return ret;
1035 }
1036
1037 static __sramdata uint32 clkFbDiv;
1038 static __sramdata uint32 clkPostDiv1;
1039 static __sramdata uint32 clkPostDiv2;
1040
1041 /*****************************************
1042 REFDIV   FBDIV     POSTDIV1/POSTDIV2      FOUTPOSTDIV           freq Step        FOUTPOSRDIV            finally use
1043 ==================================================================================================================
1044 1        17 - 66   4                      100MHz - 400MHz          6MHz          200MHz  <= 300MHz             <= 150MHz
1045 1        17 - 66   3                      133MHz - 533MHz          8MHz
1046 1        17 - 66   2                      200MHz - 800MHz          12MHz         300MHz  <= 600MHz      150MHz <= 300MHz
1047 1        17 - 66   1                      400MHz - 1600MHz         24MHz         600MHz  <= 1200MHz     300MHz <= 600MHz
1048 ******************************************/
1049 //for minimum jitter operation, the highest VCO and FREF frequencies should be used.
1050 /*----------------------------------------------------------------------
1051 Name    : uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
1052 Desc    : ÉèÖÃddr pll
1053 Params  : nMHZ -> ddr¹¤×÷ÆµÂÊ
1054           set  ->0»ñÈ¡ÉèÖÃµÄÆµÂÊÐÅÏ¢
1055                  1ÉèÖÃddr pll
1056 Return  : ÉèÖÃµÄÆµÂÊÖµ
1057 Notes   : ÔÚ±äÆµÊ±ÐèÒªÏÈset=0µ÷ÓÃÒ»´Îddr_set_pll£¬ÔÙset=1 µ÷ÓÃddr_set_pll
1058 ----------------------------------------------------------------------*/
1059 static uint32 __sramfunc ddr_set_pll(uint32 nMHz, uint32 set)
1060 {
1061     uint32 ret = 0;
1062     int delay = 1000;
1063     uint32 pll_id=1;  //DPLL
1064
1065     if(nMHz == 24)
1066     {
1067         ret = 24;
1068         goto out;
1069     }
1070     if(!set)
1071     {
1072         if(nMHz <= 150) //Êµ¼ÊÊä³öÆµÂÊ<300
1073         {
1074             clkPostDiv1 = 6;
1075         }
1076         else if(nMHz <=200)
1077         {
1078             clkPostDiv1 = 4;
1079         }
1080         else if(nMHz <= 300)
1081         {
1082             clkPostDiv1 = 3;
1083         }
1084         else if(nMHz <=450)
1085         {
1086             clkPostDiv1 = 2;
1087         }
1088         else
1089         {
1090             clkPostDiv1 = 1;
1091         }
1092         clkPostDiv2 = 1;
1093         clkFbDiv = (nMHz * 2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2)/24;//×îºóËÍÈëddrµÄÊÇÔÙ¾¹ý2·ÖÆµ
1094         ret = (24 * clkFbDiv)/(2 * DDR_PLL_REFDIV * clkPostDiv1 * clkPostDiv2);
1095     }
1096     else
1097     {
1098         pCRU_Reg->CRU_MODE_CON = (0x1<<((pll_id*4) +  16)) | (0x0<<(pll_id*4));            //PLL slow-mode
1099
1100         pCRU_Reg->CRU_PLL_CON[pll_id][0] = FBDIV(clkFbDiv) | POSTDIV1(clkPostDiv1);
1101         pCRU_Reg->CRU_PLL_CON[pll_id][1] = REFDIV(DDR_PLL_REFDIV) | POSTDIV2(clkPostDiv2) | (0x10001<<12);//interger mode
1102
1103         ddr_delayus(1);
1104
1105         while (delay > 0)
1106         {
1107             ddr_delayus(1);
1108                 if (pCRU_Reg->CRU_PLL_CON[pll_id][1] & (PLL_LOCK_STATUS))        // wait for pll locked
1109                         break;
1110                 delay--;
1111         }
1112
1113         pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3<<16) | 0x0);           //clk_ddr_src:clk_ddrphy = 1:1
1114         pCRU_Reg->CRU_MODE_CON = (0x1<<((pll_id*4) +  16))  | (0x1<<(pll_id*4));            //PLL normal
1115     }
1116 out:
1117     return ret;
1118 }
1119
1120 uint32 PIE_FUNC(ddr_set_pll)(uint32 nMHz, uint32 set)
1121 {
1122     return ddr_set_pll(nMHz,set);
1123 }
1124 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1125
1126 /*----------------------------------------------------------------------
1127 Name    : uint32_t ddr_get_parameter(uint32_t nMHz)
1128 Desc    : »ñÈ¡ÅäÖÃ²ÎÊý
1129 Params  : nMHZ -> ddr¹¤×÷ÆµÂÊ
1130 Return  : 0 ³É¹¦
1131           -1 Ê§°Ü
1132           -4 ÆµÂÊÖµ³¬¹ý¿ÅÁ£×î´óÆµÂÊ
1133 Notes   :
1134 ----------------------------------------------------------------------*/
1135 static uint32 ddr_get_parameter(uint32 nMHz)
1136 {
1137     uint32_t tmp;
1138     uint32_t ret = 0;
1139     uint32_t al;
1140     uint32_t bl;
1141     uint32_t cl;
1142     uint32_t cwl;
1143     PCTL_TIMING_T *p_pctl_timing = &(p_ddr_reg->pctl_timing);
1144     NOC_TIMING_T  *p_noc_timing=&(p_ddr_reg->noc_timing);
1145
1146     p_pctl_timing->togcnt1u = nMHz;
1147     p_pctl_timing->togcnt100n = nMHz/10;
1148     p_pctl_timing->tinit = 200;
1149     p_pctl_timing->trsth = 500;
1150
1151     if(p_ddr_reg->mem_type == DDR3)
1152     {
1153         if(p_ddr_reg->ddr_speed_bin > DDR3_DEFAULT)
1154         {
1155             ret = -1;
1156             goto out;
1157         }
1158
1159         #define DDR3_tREFI_7_8_us    (78)
1160         #define DDR3_tMRD            (4)
1161         #define DDR3_tRFC_512Mb      (90)
1162         #define DDR3_tRFC_1Gb        (110)
1163         #define DDR3_tRFC_2Gb        (160)
1164         #define DDR3_tRFC_4Gb        (300)
1165         #define DDR3_tRFC_8Gb        (350)
1166         #define DDR3_tRTW            (2)   //register min valid value
1167         #define DDR3_tRAS            (37)
1168         #define DDR3_tRRD            (10)
1169         #define DDR3_tRTP            (7)
1170         #define DDR3_tWR             (15)
1171         #define DDR3_tWTR            (7)
1172         #define DDR3_tXP             (7)
1173         #define DDR3_tXPDLL          (24)
1174         #define DDR3_tZQCS           (80)
1175         #define DDR3_tZQCSI          (10000)
1176         #define DDR3_tDQS            (1)
1177         #define DDR3_tCKSRE          (10)
1178         #define DDR3_tCKE_400MHz     (7)
1179         #define DDR3_tCKE_533MHz     (6)
1180         #define DDR3_tMOD            (15)
1181         #define DDR3_tRSTL           (100)
1182         #define DDR3_tZQCL           (320)
1183         #define DDR3_tDLLK           (512)
1184
1185         al = 0;
1186         bl = 8;
1187         if(nMHz <= 330)
1188         {
1189             tmp = 0;
1190         }
1191         else if(nMHz<=400)
1192         {
1193             tmp = 1;
1194         }
1195         else if(nMHz<=533)
1196         {
1197             tmp = 2;
1198         }
1199         else //666MHz
1200         {
1201             tmp = 3;
1202         }
1203         if(nMHz < DDR3_DDR2_DLL_DISABLE_FREQ)       //when dll bypss cl = cwl = 6;
1204         {
1205             cl = 6;
1206             cwl = 6;
1207         }
1208         else
1209         {
1210             cl = ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] >> 16;
1211             cwl = ddr3_cl_cwl[p_ddr_reg->ddr_speed_bin][tmp] & 0x0ff;
1212         }
1213         if(cl == 0)
1214         {
1215             ret = -4; //³¬¹ý¿ÅÁ£µÄ×î´óÆµÂÊ
1216         }
1217         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
1218         {
1219             p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
1220         }
1221         else
1222         {
1223             p_ddr_reg->ddrMR[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
1224         }
1225         p_ddr_reg->ddrMR[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
1226         p_ddr_reg->ddrMR[3] = 0;
1227         /**************************************************
1228          * PCTL Timing
1229          **************************************************/
1230         /*
1231          * tREFI, average periodic refresh interval, 7.8us
1232          */
1233         p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
1234         /*
1235          * tMRD, 4 tCK
1236          */
1237         p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
1238         /*
1239          * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
1240          */
1241         if(p_ddr_reg->ddr_capability_per_die <= 0x4000000)         // 512Mb 90ns
1242         {
1243             tmp = DDR3_tRFC_512Mb;
1244         }
1245         else if(p_ddr_reg->ddr_capability_per_die <= 0x8000000)    // 1Gb 110ns
1246         {
1247             tmp = DDR3_tRFC_1Gb;
1248         }
1249         else if(p_ddr_reg->ddr_capability_per_die <= 0x10000000)   // 2Gb 160ns
1250         {
1251             tmp = DDR3_tRFC_2Gb;
1252         }
1253         else if(p_ddr_reg->ddr_capability_per_die <= 0x20000000)   // 4Gb 300ns
1254         {
1255             tmp = DDR3_tRFC_4Gb;
1256         }
1257         else    // 8Gb  350ns
1258         {
1259             tmp = DDR3_tRFC_8Gb;
1260         }
1261         p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
1262         /*
1263          * tXSR, =tDLLK=512 tCK
1264          */
1265         p_pctl_timing->texsr = DDR3_tDLLK;
1266         /*
1267          * tRP=CL
1268          */
1269         p_pctl_timing->trp = cl;
1270         /*
1271          * WrToMiss=WL*tCK + tWR + tRP + tRCD
1272          */
1273         p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
1274         /*
1275          * tRC=tRAS+tRP
1276          */
1277         p_pctl_timing->trc = ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
1278         p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[p_ddr_reg->ddr_speed_bin]>>16)*nMHz+999)/1000)&0x3F);
1279
1280         p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
1281         p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
1282         p_pctl_timing->tal = al;
1283         p_pctl_timing->tcl = cl;
1284         p_pctl_timing->tcwl = cwl;
1285         /*
1286          * tRAS, 37.5ns(400MHz)     37.5ns(533MHz)
1287          */
1288         p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
1289         /*
1290          * tRCD=CL
1291          */
1292         p_pctl_timing->trcd = cl;
1293         /*
1294          * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
1295          *        max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
1296          *        max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
1297          *
1298          */
1299         tmp = ((DDR3_tRRD*nMHz+999)/1000);
1300         if(tmp < 4)
1301         {
1302             tmp = 4;
1303         }
1304         p_pctl_timing->trrd = (tmp&0xF);
1305         /*
1306          * tRTP, max(4 tCK,7.5ns)
1307          */
1308         tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
1309         if(tmp < 4)
1310         {
1311             tmp = 4;
1312         }
1313         p_pctl_timing->trtp = tmp&0xF;
1314         /*
1315          * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
1316          */
1317         p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
1318         /*
1319          * tWR, 15ns
1320          */
1321         tmp = ((DDR3_tWR*nMHz+999)/1000);
1322         p_pctl_timing->twr = tmp&0x1F;
1323         if(tmp<9)
1324             tmp = tmp - 4;
1325         else
1326             tmp = tmp>>1;
1327         p_ddr_reg->ddrMR[0] = DDR3_BL8 | DDR3_CL(cl) | DDR3_WR(tmp);
1328
1329         /*
1330          * tWTR, max(4 tCK,7.5ns)
1331          */
1332         tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
1333         if(tmp < 4)
1334         {
1335             tmp = 4;
1336         }
1337         p_pctl_timing->twtr = tmp&0xF;
1338         p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
1339         /*
1340          * tXP, max(3 tCK, 7.5ns)(<933MHz)
1341          */
1342         tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
1343         if(tmp < 3)
1344         {
1345             tmp = 3;
1346         }
1347         p_pctl_timing->txp = tmp&0x7;
1348         /*
1349          * tXPDLL, max(10 tCK,24ns)
1350          */
1351         tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
1352         if(tmp < 10)
1353         {
1354             tmp = 10;
1355         }
1356         p_pctl_timing->txpdll = tmp & 0x3F;
1357         /*
1358          * tZQCS, max(64 tCK, 80ns)
1359          */
1360         tmp = ((DDR3_tZQCS*nMHz+999)/1000);
1361         if(tmp < 64)
1362         {
1363             tmp = 64;
1364         }
1365         p_pctl_timing->tzqcs = tmp&0x7F;
1366         /*
1367          * tZQCSI,
1368          */
1369         p_pctl_timing->tzqcsi = DDR3_tZQCSI;
1370         /*
1371          * tDQS,
1372          */
1373         p_pctl_timing->tdqs = DDR3_tDQS;
1374         /*
1375          * tCKSRE, max(5 tCK, 10ns)
1376          */
1377         tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
1378         if(tmp < 5)
1379         {
1380             tmp = 5;
1381         }
1382         p_pctl_timing->tcksre = tmp & 0x1F;
1383         /*
1384          * tCKSRX, max(5 tCK, 10ns)
1385          */
1386         p_pctl_timing->tcksrx = tmp & 0x1F;
1387         /*
1388          * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
1389          */
1390         if(nMHz>=533)
1391         {
1392             tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
1393         }
1394         else
1395         {
1396             tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
1397         }
1398         if(tmp < 3)
1399         {
1400             tmp = 3;
1401         }
1402         p_pctl_timing->tcke = tmp & 0x7;
1403         /*
1404          * tCKESR, =tCKE + 1tCK
1405          */
1406         p_pctl_timing->tckesr = (tmp+1)&0xF;
1407         /*
1408          * tMOD, max(12 tCK,15ns)
1409          */
1410         tmp = ((DDR3_tMOD*nMHz+999)/1000);
1411         if(tmp < 12)
1412         {
1413             tmp = 12;
1414         }
1415         p_pctl_timing->tmod = tmp&0x1F;
1416         /*
1417          * tRSTL, 100ns
1418          */
1419         p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
1420         /*
1421          * tZQCL, max(256 tCK, 320ns)
1422          */
1423         tmp = ((DDR3_tZQCL*nMHz+999)/1000);
1424         if(tmp < 256)
1425         {
1426             tmp = 256;
1427         }
1428         p_pctl_timing->tzqcl = tmp&0x3FF;
1429         /*
1430          * tMRR, 0 tCK
1431          */
1432         p_pctl_timing->tmrr = 0;
1433         /*
1434          * tDPD, 0
1435          */
1436         p_pctl_timing->tdpd = 0;
1437
1438         /**************************************************
1439          * NOC Timing
1440          **************************************************/
1441         p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
1442     }
1443     else
1444     {
1445         ret = -1;
1446     }
1447
1448 out:
1449     return ret;
1450 }
1451
1452 /*----------------------------------------------------------------------
1453 Name    : uint32_t __sramlocalfunc ddr_update_timing(void)
1454 Desc    : ¸üÐÂpctl phy Ïà¹Øtiming¼Ä´æÆ÷
1455 Params  : void
1456 Return  : 0 ³É¹¦
1457 Notes   :
1458 ----------------------------------------------------------------------*/
1459 static uint32 __sramfunc ddr_update_timing(void)
1460 {
1461     PCTL_TIMING_T *p_pctl_timing = &(DATA(ddr_reg).pctl_timing);
1462     NOC_TIMING_T  *p_noc_timing = &(DATA(ddr_reg).noc_timing);
1463
1464     ddr_copy((uint32 *)&(pDDR_Reg->TOGCNT1U), (uint32*)&(p_pctl_timing->togcnt1u), 34);
1465     pPHY_Reg->PHY_REG3 = (0x12 << 1) | (ddr2_ddr3_bl_8);   //0x12Îª±£ÁôÎ»µÄÄ¬ÈÏÖµ£¬ÒÔÄ¬ÈÏÖµ»ØÐ´
1466     pPHY_Reg->PHY_REG4a = ((p_pctl_timing->tcl << 4) | (p_pctl_timing->tal));
1467     *(volatile uint32 *)SysSrv_DdrTiming = p_noc_timing->d32;
1468     // Update PCTL BL
1469 //    if(DATA(ddr_reg).mem_type == DDR3)
1470     {
1471         pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | ddr2_ddr3_bl_8 | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
1472         pDDR_Reg->DFITRDDATAEN   = (pDDR_Reg->TAL + pDDR_Reg->TCL)-3;  //trdata_en = rl-3
1473         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL-1;
1474     }
1475     return 0;
1476 }
1477
1478 /*----------------------------------------------------------------------
1479 Name    : uint32_t __sramlocalfunc ddr_update_mr(void)
1480 Desc    : ¸üÐÂ¿ÅÁ£MR¼Ä´æÆ÷
1481 Params  : void
1482 Return  : void
1483 Notes   :
1484 ----------------------------------------------------------------------*/
1485 static uint32 __sramfunc ddr_update_mr(void)
1486 {
1487     uint32 cs;
1488
1489     cs = READ_CS_INFO();
1490     cs = cs + (1 << cs);                               //case 0:1rank cs=1; case 1:2rank cs =3;
1491     if(DATA(ddr_freq) > DDR3_DDR2_DLL_DISABLE_FREQ)
1492     {
1493         if(DATA(ddr_dll_status) == DDR3_DLL_DISABLE)  // off -> on
1494         {
1495             ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((DATA(ddr_reg).ddrMR[1])));  //DLL enable
1496             ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((DATA(ddr_reg).ddrMR[0]))| DDR3_DLL_RESET));  //DLL reset
1497             ddr_delayus(2);  //at least 200 DDR cycle
1498             ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
1499             DATA(ddr_dll_status) = DDR3_DLL_ENABLE;
1500         }
1501         else // on -> on
1502         {
1503             ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((DATA(ddr_reg).ddrMR[1])));
1504             ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
1505         }
1506     }
1507     else
1508     {
1509         ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((DATA(ddr_reg).ddrMR[1])) | DDR3_DLL_DISABLE));  //DLL disable
1510         ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((DATA(ddr_reg).ddrMR[0])));
1511         DATA(ddr_dll_status) = DDR3_DLL_DISABLE;
1512     }
1513     ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((DATA(ddr_reg).ddrMR[2])));
1514
1515     return 0;
1516 }
1517
1518 /*----------------------------------------------------------------------
1519 Name    : void __sramlocalfunc ddr_update_odt(void)
1520 Desc    : update PHY odt & PHY driver impedance
1521 Params  : void
1522 Return  : void
1523 Notes   :
1524 ----------------------------------------------------------------------*/
1525 static void __sramfunc ddr_update_odt(void)
1526 {
1527     uint32 tmp;
1528
1529     //adjust DRV and ODT
1530     if(DATA(ddr_freq) <= PHY_ODT_DISABLE_FREQ)
1531     {
1532         pPHY_Reg->PHY_REG27 = PHY_RTT_DISABLE;  //dynamic RTT disable, Left 8bit ODT
1533         pPHY_Reg->PHY_REG28 = PHY_RTT_DISABLE;  //Right 8bit ODT
1534         pPHY_Reg->PHY_REG0e4 = (0x0E & 0xc)|0x1;//off DQS ODT  bit[1:0]=2'b01
1535         pPHY_Reg->PHY_REG124 = (0x0E & 0xc)|0x1;//off DQS ODT  bit[1:0]=2'b01
1536     }
1537     else
1538     {
1539         pPHY_Reg->PHY_REG27 = ((PHY_RTT_215ohm<<4) | PHY_RTT_215ohm);
1540         pPHY_Reg->PHY_REG28 = ((PHY_RTT_215ohm<<4) | PHY_RTT_215ohm);
1541         pPHY_Reg->PHY_REG0e4 = 0x0E;           //on DQS ODT default:0x0E
1542         pPHY_Reg->PHY_REG124 = 0x0E;           //on DQS ODT default:0x0E
1543     }
1544
1545     tmp = ((PHY_RON_45ohm<<4) | PHY_RON_45ohm);
1546     pPHY_Reg->PHY_REG16 = tmp;  //CMD driver strength
1547     pPHY_Reg->PHY_REG22 = tmp;  //CK driver strength
1548     pPHY_Reg->PHY_REG25 = tmp;  //Left 8bit DQ driver strength
1549     pPHY_Reg->PHY_REG26 = tmp;  //Right 8bit DQ driver strength
1550     dsb();
1551 }
1552
1553 /*----------------------------------------------------------------------
1554 Name    : __sramfunc void ddr_adjust_config(uint32_t dram_type)
1555 Desc    :
1556 Params  : dram_type ->¿ÅÁ£ÀàÐÍ
1557 Return  : void
1558 Notes   :
1559 ----------------------------------------------------------------------*/
1560 #if 0
1561 __sramfunc void ddr_adjust_config(uint32_t dram_type)
1562 {
1563 //    uint32 value;
1564     unsigned long save_sp;
1565     uint32 i;
1566     volatile uint32 n;
1567     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
1568
1569     //get data training address before idle port
1570 //    value = ddr_get_datatraing_addr();    //Inno PHY ²»ÐèÒªtraining address
1571
1572     /** 1. Make sure there is no host access */
1573     flush_cache_all();
1574     outer_flush_all();
1575     flush_tlb_all();
1576     DDR_SAVE_SP(save_sp);
1577
1578     for(i=0;i<2;i++)        //8KB SRAM
1579     {
1580         n=temp[1024*i];
1581         barrier();
1582     }
1583     n= pDDR_Reg->SCFG.d32;
1584     n= pPHY_Reg->PHY_REG1;
1585     n= pCRU_Reg->CRU_PLL_CON[0][0];
1586     n= *(volatile uint32_t *)SysSrv_DdrTiming;
1587     dsb();
1588
1589     //enter config state
1590     ddr_move_to_Config_state();
1591 //    pDDR_Reg->DFIODTCFG = ((1<<3) | (1<<11));  //loaderÖÐÂ©ÁË³õÊ¼»¯
1592     pPHY_Reg->PHY_REG5d = 0X77;
1593     pPHY_Reg->PHY_REG5e = 0X77;
1594     //set auto power down idle
1595     pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
1596
1597     //enable the hardware low-power interface
1598     pDDR_Reg->SCFG.b.hw_low_power_en = 1;
1599
1600     ddr_update_odt();
1601
1602     //enter access state
1603     ddr_move_to_Access_state();
1604
1605     DDR_RESTORE_SP(save_sp);
1606 }
1607 #endif
1608
1609 static void __sramfunc idle_port(void)
1610 {
1611     int i;
1612     uint32 clk_gate[10];
1613
1614     //save clock gate status
1615     for(i=0;i<10;i++)
1616     {
1617         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1618     }
1619     //enable all clock gate for request idle
1620     for(i=0;i<10;i++)
1621     {
1622         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1623     }
1624
1625     pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+peri_pwr_idlereq))+(1 << peri_pwr_idlereq);         //peri   bit 12
1626     dsb();
1627     while( (pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) == 0);//   bit 23
1628
1629     pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vio_pwr_idlereq))+(1 << vio_pwr_idlereq);          //vio
1630     dsb();
1631     while( (pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) == 0);
1632
1633     pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vpu_pwr_idlereq))+(1 << vpu_pwr_idlereq);          //vpu
1634     dsb();
1635     while( (pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) == 0);
1636
1637     pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+gpu_pwr_idlereq))+(1 << gpu_pwr_idlereq);          //gpu
1638     dsb();
1639     while( (pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) == 0);
1640
1641         //resume clock gate status
1642     for(i=0;i<10;i++)
1643         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1644 }
1645
1646
1647 static void __sramfunc deidle_port(void)
1648 {
1649     int i;
1650     uint32 clk_gate[10];
1651
1652     //save clock gate status
1653     for(i=0;i<10;i++)
1654     {
1655         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1656     }
1657     //enable all clock gate for request idle
1658     for(i=0;i<10;i++)
1659     {
1660         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1661     }
1662
1663     pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+peri_pwr_idlereq))+(0 << peri_pwr_idlereq);         //peri   bit 12
1664     dsb();
1665     while( (pGRF_Reg->GRF_SOC_STATUS0 & peri_pwr_idle) != 0);
1666
1667     pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vio_pwr_idlereq))+(0 << vio_pwr_idlereq);          //vio
1668     dsb();
1669     while( (pGRF_Reg->GRF_SOC_STATUS0 & vio_pwr_idle) != 0);
1670
1671     pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+vpu_pwr_idlereq))+(0 << vpu_pwr_idlereq);          //vpu
1672     dsb();
1673     while( (pGRF_Reg->GRF_SOC_STATUS0 & vpu_pwr_idle) != 0);
1674
1675     pGRF_Reg->GRF_SOC_CON[2] = (1 << (16+gpu_pwr_idlereq))+(0 << gpu_pwr_idlereq);          //gpu
1676     dsb();
1677     while( (pGRF_Reg->GRF_SOC_STATUS0 & gpu_pwr_idle) != 0);
1678
1679     //resume clock gate status
1680     for(i=0;i<10;i++)
1681         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1682
1683 }
1684
1685
1686
1687 /*----------------------------------------------------------------------
1688 Name    : void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
1689 Desc    : ½øÈë×ÔË¢ÐÂ
1690 Params  : nMHz ->ddrÆµÂÊ
1691 Return  : void
1692 Notes   :
1693 ----------------------------------------------------------------------*/
1694 /*
1695 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
1696 {
1697     ddr_move_to_Config_state();
1698     ddr_move_to_Lowpower_state();
1699         pPHY_Reg->PHY_REG264 &= ~(1<<1);
1700     pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2)));     //phy soft reset
1701     dsb();
1702     pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2);  //disable DDR PHY clock
1703     ddr_delayus(1);
1704 }
1705 */
1706 static uint32 dtt_buffer[8];
1707
1708 /*----------------------------------------------------------------------
1709 Name    : void ddr_dtt_check(void)
1710 Desc    : data training check
1711 Params  : void
1712 Return  : void
1713 Notes   :
1714 ----------------------------------------------------------------------*/
1715 static void ddr_dtt_check(void)
1716 {
1717     uint32 i;
1718     for(i=0;i<8;i++)
1719     {
1720         dtt_buffer[i] = p_copy_data[i];
1721     }
1722     dsb();
1723     flush_cache_all();
1724     outer_flush_all();
1725     for(i=0;i<8;i++)
1726     {
1727         if(dtt_buffer[i] != p_copy_data[i])
1728         {
1729 //            sram_printascii("DTT failed!\n");
1730             break;
1731         }
1732         dtt_buffer[i] = 0;
1733     }
1734
1735 }
1736
1737 /*----------------------------------------------------------------------
1738 Name    : void __sramlocalfunc ddr_selfrefresh_exit(void)
1739 Desc    : ÍË³ö×ÔË¢ÐÂ
1740 Params  : void
1741 Return  : void
1742 Notes   :
1743 ----------------------------------------------------------------------*/
1744 #if 0
1745 static void __sramfunc ddr_selfrefresh_exit(void)
1746 {
1747     pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2);  //enable DDR PHY clock
1748     dsb();
1749     ddr_delayus(1);
1750         pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
1751         pPHY_Reg->PHY_REG264 |= (1<<1);
1752         dsb();
1753     ddr_move_to_Config_state();
1754     ddr_data_training();
1755     ddr_move_to_Access_state();
1756 //    ddr_dtt_check();
1757 }
1758 #endif
1759 /*----------------------------------------------------------------------
1760 Name    : void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
1761 Desc    : ÉèÖÃddr pllÇ°µÄtiming¼°mr²ÎÊýµ÷Õû
1762 Params  : freq_slew :±äÆµÐ±ÂÊ 1ÉýÆ½  0½µÆµ
1763 Return  : void
1764 Notes   :
1765 ----------------------------------------------------------------------*/
1766 static void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew)
1767 {
1768     uint32 value_100n, value_1u;
1769
1770     if(freq_slew == 1)
1771     {
1772         value_100n = DATA(ddr_reg).pctl_timing.togcnt100n;
1773         value_1u = DATA(ddr_reg).pctl_timing.togcnt1u;
1774         DATA(ddr_reg).pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
1775         DATA(ddr_reg).pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
1776         ddr_update_timing();
1777         ddr_update_mr();
1778         DATA(ddr_reg).pctl_timing.togcnt100n = value_100n;
1779         DATA(ddr_reg).pctl_timing.togcnt1u = value_1u;
1780     }
1781     else
1782     {
1783         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
1784         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
1785     }
1786
1787     pDDR_Reg->TZQCSI = 0;
1788
1789 }
1790
1791
1792
1793 /*----------------------------------------------------------------------
1794 Name    : void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
1795 Desc    : ÉèÖÃddr pllºóµÄtiming¼°mr²ÎÊýµ÷Õû
1796 Params  : freq_slew :±äÆµÐ±ÂÊ 1ÉýÆ½  0½µÆµ
1797 Return  : void
1798 Notes   :
1799 ----------------------------------------------------------------------*/
1800 static void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew)
1801 {
1802     if(freq_slew == 1)
1803     {
1804         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n;
1805         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl_timing.togcnt1u;
1806         pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl_timing.tzqcsi;
1807     }
1808     else
1809     {
1810         ddr_update_timing();
1811         ddr_update_mr();
1812     }
1813     ddr_data_training();
1814 }
1815
1816 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32 freq_slew)
1817 {
1818     idle_port();
1819
1820     ddr_move_to_Config_state();
1821     DATA(ddr_freq) = freq;
1822     ddr_change_freq_in(freq_slew);
1823     ddr_move_to_Lowpower_state();
1824     pPHY_Reg->PHY_REG264 &= ~(1<<1);
1825     pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2)));     //phy soft reset
1826     dsb();
1827     /** 3. change frequence  */
1828     FUNC(ddr_set_pll)(freq,1);
1829     ddr_set_dll_bypass(freq);    //set phy dll mode;
1830         pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
1831         pPHY_Reg->PHY_REG264 |= (1<<1);
1832         dsb();
1833         ddr_update_odt();
1834     ddr_move_to_Config_state();
1835     ddr_change_freq_out(freq_slew);
1836     ddr_move_to_Access_state();
1837
1838     deidle_port();
1839 }
1840
1841 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
1842 {
1843     struct ddr_change_freq_sram_param *param = arg;
1844     /* Make sure ddr_SRE_2_SRX paramter less than 4 */
1845     ddr_SRE_2_SRX(param->freq, param->freq_slew);
1846 }
1847 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
1848
1849 /*----------------------------------------------------------------------
1850 Name    : uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
1851 Desc    : ddr±äÆµ
1852 Params  : nMHz -> ±äÆµµÄÆµÂÊÖµ
1853 Return  : ÆµÂÊÖµ
1854 Notes   :
1855 ----------------------------------------------------------------------*/
1856 static uint32 ddr_change_freq_sram(uint32 nMHz, struct ddr_freq_t ddr_freq_t)
1857 {
1858     uint32 ret;
1859     uint32 i;
1860     volatile uint32 n;
1861     unsigned long flags;
1862     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
1863
1864     struct ddr_change_freq_sram_param param;
1865     //uint32 freq;
1866         uint32 freq_slew;
1867         uint32 arm_freq;
1868
1869     arm_freq= ddr_get_pll_freq(APLL);
1870     *kern_to_pie(rockchip_pie_chunk, &DATA(loops_per_us)) = LPJ_100MHZ*arm_freq/1000000;
1871     ret =(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll)))(nMHz,0);
1872     if(ret == *p_ddr_freq)
1873     {
1874         goto out;
1875     }
1876     else
1877     {
1878         freq_slew = (ret > *p_ddr_freq)? 1 : -1;
1879     }
1880     ddr_get_parameter(ret);
1881     //*kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq))= ret;
1882     /** 1. Make sure there is no host access */
1883     local_irq_save(flags);
1884         local_fiq_disable();
1885     flush_cache_all();
1886         outer_flush_all();
1887         flush_tlb_all();
1888         //DDR_SAVE_SP(save_sp);
1889
1890 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
1891         n = ddr_freq_t.screen_ft_us;
1892         n = ddr_freq_t.t0;
1893         dsb();
1894
1895         if(ddr_freq_t.screen_ft_us > 0){
1896
1897             ddr_freq_t.t1 = cpu_clock(0);
1898             ddr_freq_t.t2 = (u32)(ddr_freq_t.t1 - ddr_freq_t.t0);   //ns
1899
1900
1901             if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe)){
1902
1903             //DDR_RESTORE_SP(save_sp);
1904             local_fiq_enable();
1905             local_irq_restore(flags);
1906             return 0;
1907             }else{
1908                 rk_fb_poll_wait_frame_complete();
1909             }
1910         }
1911 #endif
1912
1913         for(i=0;i<2;i++)    //8KB SRAM
1914         {
1915             n=temp[1024*i];
1916         barrier();
1917         }
1918     n= pDDR_Reg->SCFG.d32;
1919     n= pPHY_Reg->PHY_REG1;
1920     n= pCRU_Reg->CRU_PLL_CON[0][0];
1921     n= *(volatile uint32_t *)SysSrv_DdrTiming;
1922     n= pGRF_Reg->GRF_SOC_STATUS0;
1923     dsb();
1924     param.freq = ret;
1925     param.freq_slew = freq_slew;
1926     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
1927                     &param,
1928                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
1929     /** 5. Issues a Mode Exit command   */
1930    // DDR_RESTORE_SP(save_sp);
1931     ddr_dtt_check();
1932     local_fiq_enable();
1933     local_irq_restore(flags);
1934 //    clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
1935 out:
1936     return ret;
1937 }
1938
1939 static uint32 _ddr_change_freq_3036(uint32_t nMHz)
1940 {
1941         struct ddr_freq_t ddr_freq_t;
1942         ddr_freq_t.screen_ft_us = 0;
1943
1944         return ddr_change_freq_sram(nMHz,ddr_freq_t);
1945 }
1946
1947 EXPORT_SYMBOL(_ddr_change_freq_3036);
1948
1949 static void __sramlocalfunc ddr_selfrefresh_enter(uint32 nMHz)
1950 {
1951     ddr_move_to_Config_state();
1952     ddr_move_to_Lowpower_state();
1953         pPHY_Reg->PHY_REG264 &= ~(1<<1);
1954     pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 & (~(0x3<<2)));     //phy soft reset
1955     dsb();
1956     pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (1<<2);  //disable DDR PHY clock
1957     ddr_delayus(1);
1958 }
1959
1960 static void __sramlocalfunc ddr_selfrefresh_exit(void)
1961 {
1962     pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (0<<2);  //enable DDR PHY clock
1963     dsb();
1964     ddr_delayus(1);
1965         pPHY_Reg->PHY_REG1 = (pPHY_Reg->PHY_REG1 | (0x3 << 2)); //phy soft de-reset
1966         pPHY_Reg->PHY_REG264 |= (1<<1);
1967         dsb();
1968     ddr_move_to_Config_state();
1969     ddr_data_training();
1970     ddr_move_to_Access_state();
1971     /*ddr_dtt_check();*/
1972 }
1973
1974 void PIE_FUNC(ddr_suspend)(void)
1975 {
1976         ddr_selfrefresh_enter(0);
1977         pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x0 << (1 * 4));    /*PLL slow-mode*/
1978         dsb();
1979         ddr_delayus(1);
1980         pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x1 << 13);        /*PLL power-down*/
1981         dsb();
1982         ddr_delayus(1);
1983 }
1984 EXPORT_PIE_SYMBOL(FUNC(ddr_suspend));
1985
1986 /*----------------------------------------------------------------------
1987 Name    : void __sramfunc ddr_suspend(void)
1988 Desc    : ½øÈëddr suspend
1989 Params  : void
1990 Return  : void
1991 Notes   :
1992 ----------------------------------------------------------------------*/
1993 #if 0
1994 void ddr_suspend(void)
1995 {
1996         uint32 i;
1997         volatile uint32 n;
1998         volatile unsigned int *temp = (volatile unsigned int *)SRAM_CODE_OFFSET;
1999         /** 1. Make sure there is no host access */
2000         flush_cache_all();
2001         outer_flush_all();
2002         flush_tlb_all();
2003
2004         /*sram size = 8KB*/
2005         for (i = 0; i < 2; i++) {
2006                 n = temp[1024 * i];
2007                 barrier();
2008         }
2009         n = pDDR_Reg->SCFG.d32;
2010         n = pPHY_Reg->PHY_REG1;
2011         n = pCRU_Reg->CRU_PLL_CON[0][0];
2012         n = *(volatile uint32_t *)SysSrv_DdrTiming;
2013         n = pGRF_Reg->GRF_SOC_STATUS0;
2014         dsb();
2015
2016         fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_suspend)) ();
2017 }
2018 EXPORT_SYMBOL(ddr_suspend);
2019 #endif
2020
2021 void PIE_FUNC(ddr_resume)(void)
2022 {
2023         uint32 delay = 1000;
2024
2025         pCRU_Reg->CRU_PLL_CON[1][1] = ((0x1 << 13) << 16) | (0x0 << 13);        /*PLL no power-down*/
2026         dsb();
2027         while (delay > 0) {
2028                 ddr_delayus(1);
2029                 if (pCRU_Reg->CRU_PLL_CON[1][1] & (0x1 << 10))
2030                         break;
2031                 delay--;
2032         }
2033
2034         pCRU_Reg->CRU_MODE_CON = (0x1 << ((1 * 4) + 16)) | (0x1 << (1 * 4));    /*PLL normal*/
2035         dsb();
2036
2037         ddr_selfrefresh_exit();
2038 }
2039
2040 EXPORT_PIE_SYMBOL(FUNC(ddr_resume));
2041 #if 0
2042 static uint32 ddr_get_cap(void)
2043 {
2044     uint32 cs, bank, row, col,row1;
2045
2046     bank = READ_BK_INFO();
2047     row = READ_CS0_ROW_INFO();
2048     col = READ_COL_INFO();
2049     cs = READ_CS_INFO();
2050     if(cs>1)
2051     {
2052         row1 = READ_CS1_ROW_INFO();
2053         return ((1 << (row + col + bank + 1))+(1 << (row1 + col + bank + 1)));
2054     }
2055     else
2056     {
2057         return (1 << (row + col + bank + 1));
2058     }
2059 }
2060 #endif
2061 #if 0
2062 /*----------------------------------------------------------------------
2063 Name    : int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
2064 Desc    : ddr  ³õÊ¼»¯º¯Êý
2065 Params  : dram_speed_bin ->ddr¿ÅÁ£ÀàÐÍ
2066           freq ->ÆµÂÊÖµ
2067 Return  : 0 ³É¹¦
2068 Notes   :
2069 ----------------------------------------------------------------------*/
2070 static int ddr_init(uint32_t dram_speed_bin, uint32 freq)
2071 {
2072     volatile uint32_t value = 0;
2073     uint32_t cs,die=1;
2074
2075     ddr_print("version 1.00 20140704 \n");
2076     cs = READ_CS_INFO();    //case 0:1rank ; case 1:2rank ;
2077
2078     p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
2079     p_ddr_freq =kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq));
2080     p_ddr_reg->mem_type = ((pGRF_Reg->GRF_OS_REG[1] >> 13) &0x7);
2081     p_ddr_reg->ddr_speed_bin = dram_speed_bin;
2082     *p_ddr_freq= 0;
2083     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
2084     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_dll_status)) = DDR3_DLL_DISABLE;
2085     p_copy_data = kern_to_pie(rockchip_pie_chunk, &copy_data[0]);
2086     if(p_ddr_reg->mem_type != DDR3)
2087     {
2088         ddr_print("ddr type error type=%d\n",(p_ddr_reg->mem_type));
2089         return -1;
2090     }
2091
2092     switch(READ_DIE_BW_INFO())
2093     {
2094         case 0:         //8bit
2095             die = 2;
2096             break;
2097                 case 1:         //16bit
2098                         die = 1;
2099                         break;
2100         default:
2101             ddr_print("ddr die BW error=%d\n",READ_DIE_BW_INFO());
2102             break;
2103     }
2104
2105
2106     //get capability per chip, not total size, used for calculate tRFC
2107     p_ddr_reg->ddr_capability_per_die = ddr_get_cap()/(cs * die);
2108     ddr_print("%d CS, ROW=%d, Bank=%d, COL=%d, Total Capability=%dMB\n",
2109                                                                     cs, \
2110                                                                     READ_CS0_ROW_INFO(), \
2111                                                                     (0x1<<(READ_BK_INFO())), \
2112                                                                     READ_COL_INFO(), \
2113                                                                     (ddr_get_cap()>>20));/*
2114 */
2115     //ddr_adjust_config(p_ddr_reg->mem_type);
2116
2117     if(freq != 0)
2118         value=_ddr_change_freq(freq);
2119
2120     /*clk_set_rate(clk_get(NULL, "ddr"), 0);*/
2121     ddr_print("init success!!! freq=%dMHz\n", (int)value);
2122     return 0;
2123 }
2124 #endif
2125