arch/arm/mach-rockchip/ddr_rk30.c

   1 /*
   2  * Function Driver for DDR controller
   3  *
   4  * Copyright (C) 2011-2014 Fuzhou Rockchip Electronics Co.,Ltd
   5  * Author:
   6  * hcy@rock-chips.com
   7  * yk@rock-chips.com
   8  *
   9  * v1.00
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/clk.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/tlbflush.h>
  19 #include <linux/cpu.h>
  20 #include <dt-bindings/clock/ddr.h>
  21
  22 #include <linux/rockchip/cru.h>
  23
  24 typedef uint32_t uint32;
  25
  26 /***********************************
  27  * Global Control Macro
  28  ***********************************/
  29 //#define ENABLE_DDR_CLCOK_GPLL_PATH  //for RK3188
  30
  31 #define DDR3_DDR2_ODT_DISABLE_FREQ    (333)
  32 #define DDR3_DDR2_DLL_DISABLE_FREQ    (333)
  33 #define SR_IDLE                       (0x1)   //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
  34 #define PD_IDLE                       (0X40)  //unit:DDR clk cycle, and 0 for disable auto power-down
  35
  36 #if (DDR3_DDR2_ODT_DISABLE_FREQ > DDR3_DDR2_DLL_DISABLE_FREQ)
  37 #error
  38 #endif
  39
  40 #define ddr_print(x...) printk( "DDR DEBUG: " x )
  41
  42 /***********************************
  43  * ARCH Relative Macro and Struction
  44  ***********************************/
  45 #define PMU_BASE_ADDR           RK_PMU_VIRT
  46 #define SDRAMC_BASE_ADDR        RK30_DDR_PCTL_BASE
  47 #define DDR_PUBL_BASE           RK30_DDR_PUBL_BASE
  48 #define CRU_BASE_ADDR           RK_CRU_VIRT
  49 #define REG_FILE_BASE_ADDR      RK_GRF_VIRT
  50 #define SysSrv_DdrConf          (RK_CPU_AXI_BUS_VIRT+0x08)
  51 #define SysSrv_DdrTiming        (RK_CPU_AXI_BUS_VIRT+0x0c)
  52 #define SysSrv_DdrMode          (RK_CPU_AXI_BUS_VIRT+0x10)
  53 #define SysSrv_ReadLatency      (RK_CPU_AXI_BUS_VIRT+0x14)
  54
  55 #define SRAM_CODE_OFFSET        rockchip_sram_virt
  56 #define SRAM_SIZE               rockchip_sram_size
  57
  58 /*
  59  * PMU
  60  */
  61 //PMU_MISC_CON1
  62 #define idle_req_cpu_cfg    (1<<1)
  63 #define idle_req_peri_cfg   (1<<2)
  64 #define idle_req_gpu_cfg    (1<<3)
  65 #define idle_req_video_cfg  (1<<4)
  66 #define idle_req_vio_cfg    (1<<5)
  67 #define idle_req_core_cfg   (1<<14)
  68 #define idle_req_dma_cfg    (1<<16)
  69
  70 //PMU_PWRDN_ST
  71 #define idle_cpu    (1<<26)
  72 #define idle_peri   (1<<25)
  73 #define idle_gpu    (1<<24)
  74 #define idle_video  (1<<23)
  75 #define idle_vio    (1<<22)
  76 #define idle_core    (1<<15)
  77 #define idle_dma    (1<<14)
  78
  79 #define pd_a9_0_pwr_st    (1<<0)
  80 #define pd_a9_1_pwr_st    (1<<1)
  81 #define pd_peri_pwr_st    (1<<6)
  82 #define pd_vio_pwr_st    (1<<7)
  83 #define pd_video_pwr_st    (1<<8)
  84 #define pd_gpu_pwr_st    (1<<9)
  85
  86 struct ddr_freq_t {
  87     unsigned long screen_ft_us;
  88     unsigned long long t0;
  89     unsigned long long t1;
  90     unsigned long t2;
  91 };
  92
  93 //PMU registers
  94 typedef volatile struct tagPMU_FILE
  95 {
  96     uint32 PMU_WAKEUP_CFG[2];
  97     uint32 PMU_PWRDN_CON;
  98     uint32 PMU_PWRDN_ST;
  99     uint32 PMU_INT_CON;
 100     uint32 PMU_INT_ST;
 101     uint32 PMU_MISC_CON;
 102     uint32 PMU_OSC_CNT;
 103     uint32 PMU_PLL_CNT;
 104     uint32 PMU_PMU_CNT;
 105     uint32 PMU_DDRIO_PWRON_CNT;
 106     uint32 PMU_WAKEUP_RST_CLR_CNT;
 107     uint32 PMU_SCU_PWRDWN_CNT;
 108     uint32 PMU_SCU_PWRUP_CNT;
 109     uint32 PMU_MISC_CON1;
 110     uint32 PMU_GPIO6_CON;
 111     uint32 PMU_PMU_SYS_REG[4];
 112 } PMU_FILE, *pPMU_FILE;
 113
 114 //PMU_NOC_REQ
 115 #define idle_req_bp2ap_rk319x      (1<<8)
 116 #define idle_req_dma_cfg_rk319x    (1<<7)
 117 #define idle_req_vio_cfg_rk319x    (1<<4)
 118 #define idle_req_video_cfg_rk319x  (1<<3)
 119 #define idle_req_gpu_cfg_rk319x    (1<<2)
 120 #define idle_req_peri_cfg_rk319x   (1<<1)
 121
 122 //PMU_NOC_ST
 123 #define idle_bp2ap_rk319x  (1<<8)
 124 #define idle_dma_rk319x    (1<<7)
 125 #define idle_vio_rk319x    (1<<4)
 126 #define idle_video_rk319x  (1<<3)
 127 #define idle_gpu_rk319x    (1<<2)
 128 #define idle_peri_rk319x   (1<<1)
 129
 130 //PMU_PWRDN_ST
 131 #define pd_peri_pwr_st_rk319x    (1<<10)
 132 #define pd_vio_pwr_st_rk319x     (1<<9)
 133 #define pd_video_pwr_st_rk319x   (1<<8)
 134 #define pd_gpu_pwr_st_rk319x     (1<<7)
 135 #define pd_a9_1_pwr_st_rk319x    (1<<1)
 136 #define pd_a9_0_pwr_st_rk319x    (1<<0)
 137
 138 //PMU registers
 139 typedef volatile struct tagPMU_FILE_RK319X
 140 {
 141     uint32 PMU_WAKEUP_CFG[3];
 142     uint32 PMU_PWRDN_CON;
 143     uint32 PMU_PWRDN_ST;
 144     uint32 PMU_PWRMODE_CON;
 145     uint32 PMU_SFT_CON;
 146     uint32 PMU_INT_CON;
 147     uint32 PMU_INT_ST;
 148     uint32 PMU_GPIO_INT_ST;
 149     uint32 PMU_GPIO_2EDGE_INT_ST;
 150     uint32 PMU_NOC_REQ;
 151     uint32 PMU_NOC_ST;
 152     uint32 PMU_POWER_ST;
 153     uint32 reserved1[3];
 154     uint32 PMU_OSC_CNT;
 155     uint32 PMU_PLLLOCK_CNT;
 156     uint32 PMU_PLLRST_CNT;
 157     uint32 PMU_STABLE_CNT;
 158     uint32 PMU_DDRIO_PWRON_CNT;
 159     uint32 reserved2[2];
 160     uint32 PMU_WAKEUP_RST_CLR_CNT;
 161     uint32 reserved3;
 162     uint32 PMU_DDR_SREF_ST;
 163     uint32 reserved4[2];
 164     uint32 PMU_PMU_SYS_REG[4];
 165 } PMU_FILE_RK319X, *pPMU_FILE_RK319X;
 166
 167 /*
 168  * CRU
 169  */
 170 typedef enum PLL_ID_Tag
 171 {
 172     APLL=0,
 173     DPLL,
 174     CPLL,
 175     GPLL,
 176     PLL_MAX
 177 }PLL_ID;
 178
 179 #define PLL_RESET  (((0x1<<5)<<16) | (0x1<<5))
 180 #define PLL_DE_RESET  (((0x1<<5)<<16) | (0x0<<5))
 181 #define NR(n)      ((0x3F<<(8+16)) | (((n)-1)<<8))
 182 #define NO(n)      ((0xF<<16) | ((n)-1))
 183 #define NF(n)      ((0x1FFF<<16) | ((n)-1))
 184 #define NB(n)      ((0xFFF<<16) | ((n)-1))
 185
 186 //RK3066B
 187 #define PLL_RESET_RK3066B  (((0x1<<1)<<16) | (0x1<<1))
 188 #define PLL_DE_RESET_RK3066B  (((0x1<<1)<<16) | (0x0<<1))
 189 #define NR_RK3066B(n)      ((0x3F<<(8+16)) | (((n)-1)<<8))
 190 #define NO_RK3066B(n)      ((0x3F<<16) | ((n)-1))
 191 #define NF_RK3066B(n)      ((0xFFFF<<16) | ((n)-1))
 192
 193  //CRU Registers
 194 typedef volatile struct tagCRU_STRUCT
 195 {
 196     uint32 CRU_PLL_CON[4][4];
 197     uint32 CRU_MODE_CON;
 198     uint32 CRU_CLKSEL_CON[35];
 199     uint32 CRU_CLKGATE_CON[10];
 200     uint32 reserved1[2];
 201     uint32 CRU_GLB_SRST_FST_VALUE;
 202     uint32 CRU_GLB_SRST_SND_VALUE;
 203     uint32 reserved2[2];
 204     uint32 CRU_SOFTRST_CON[9];
 205     uint32 CRU_MISC_CON;
 206     uint32 reserved3[2];
 207     uint32 CRU_GLB_CNT_TH;
 208 } CRU_REG, *pCRU_REG;
 209
 210 typedef volatile struct tagCRU_STRUCT_RK319X
 211 {
 212     uint32 CRU_PLL_CON[4][4];
 213     uint32 CRU_MODE_CON;
 214     uint32 CRU_CLKSEL_CON[35];
 215     uint32 CRU_CLKGATE_CON[16];
 216     uint32 CRU_SOFTRST_CON[12];
 217     uint32 CRU_GLB_CNT_TH;
 218     uint32 CRU_MISC_CON;
 219     uint32 CRU_TSADC_CON;
 220     uint32 reserved1[(0x160-0x14c)/4];
 221     uint32 CRU_GLB_SRST_FST_VALUE;
 222     uint32 CRU_GLB_SRST_SND_VALUE;
 223     uint32 CRU_GLB_BB_SRST_FST_VALUE;
 224     uint32 CRU_GLB_BB_SRST_SND_VALUE;
 225 } CRU_REG_RK319X, *pCRU_REG_RK319X;
 226
 227 /*
 228  * GRF
 229  */
 230 typedef struct tagGPIO_LH
 231 {
 232     uint32 GPIOL;
 233     uint32 GPIOH;
 234 }GPIO_LH_T;
 235
 236 typedef struct tagGPIO_IOMUX
 237 {
 238     uint32 GPIOA_IOMUX;
 239     uint32 GPIOB_IOMUX;
 240     uint32 GPIOC_IOMUX;
 241     uint32 GPIOD_IOMUX;
 242 }GPIO_IOMUX_T;
 243
 244 //REG FILE registers
 245 typedef volatile struct tagREG_FILE
 246 {
 247     GPIO_LH_T GRF_GPIO_DIR[7];
 248     GPIO_LH_T GRF_GPIO_DO[7];
 249     GPIO_LH_T GRF_GPIO_EN[7];
 250     GPIO_IOMUX_T GRF_GPIO_IOMUX[7];
 251     GPIO_LH_T GRF_GPIO_PULL[7];
 252     uint32 GRF_SOC_CON[3];
 253     uint32 GRF_SOC_STATUS0;
 254     uint32 GRF_DMAC1_CON[3];
 255     uint32 GRF_DMAC2_CON[4];
 256     uint32 GRF_UOC0_CON[3];
 257     uint32 GRF_UOC1_CON[4];
 258     uint32 GRF_DDRC_CON0;
 259     uint32 GRF_DDRC_STAT;
 260     uint32 reserved[(0x1c8-0x1a0)/4];
 261     uint32 GRF_OS_REG[4];
 262 } REG_FILE, *pREG_FILE;
 263
 264 //REG FILE registers
 265 typedef volatile struct tagREG_FILE_RK3066B
 266 {
 267     GPIO_LH_T GRF_GPIO_DIR[4];
 268     GPIO_LH_T GRF_GPIO_DO[4];
 269     GPIO_LH_T GRF_GPIO_EN[4];
 270     GPIO_IOMUX_T GRF_GPIO_IOMUX[4];
 271     uint32 GRF_SOC_CON[3];
 272     uint32 GRF_SOC_STATUS0;
 273     uint32 GRF_DMAC0_CON[3];
 274     uint32 GRF_DMAC1_CON[4];
 275     uint32 reserved0[(0xec-0xcc)/4];
 276     uint32 GRF_DDRC_CON0;
 277     uint32 GRF_DDRC_STAT;
 278     uint32 GRF_IO_CON[5];
 279     uint32 reserved1;
 280     uint32 GRF_UOC0_CON[4];
 281     uint32 GRF_UOC1_CON[4];
 282     uint32 GRF_UOC2_CON[2];
 283     uint32 reserved2;
 284     uint32 GRF_UOC3_CON[2];
 285     uint32 GRF_EHCI_STAT;
 286     uint32 GRF_OS_REG[8];
 287 } REG_FILE_RK3066B, *pREG_FILE_RK3066B;
 288
 289 typedef struct tagGPIO
 290 {
 291     uint32 GPIOA;
 292     uint32 GPIOB;
 293     uint32 GPIOC;
 294     uint32 GPIOD;
 295 }GPIO_T;
 296
 297 //REG FILE registers
 298 typedef volatile struct tagREG_FILE_RK319X
 299 {
 300     GPIO_T GRF_GPIO_IOMUX[5]; // 0x0010
 301     GPIO_T reserved1;
 302     uint32 GRF_SOC_CON[5];          // 0x0060
 303     uint32 GRF_SOC_STATUS0;
 304     uint32 GRF_SOC_STATUS1;
 305     uint32 GRF_SOC_STATUS2;
 306     uint32 GRF_DMAC1_CON[3];
 307     uint32 GRF_DMAC2_CON[4];
 308     uint32 GRF_CPU_CON[6];
 309     uint32 GRF_CPU_STATUS[2];
 310     uint32 GRF_DDRC_CON0;
 311     uint32 GRF_DDRC_STAT;
 312     uint32 GRF_UOC0_CON[4];
 313     uint32 GRF_U0C1_CON[4];
 314     uint32 GRF_UOC2_CON[2];
 315     uint32 GRF_UOC3_CON[2];
 316     uint32 GRF_PVTM_CON[3];
 317     uint32 GRF_PVTM_STATUS[3];
 318     uint32 reserved2;
 319     uint32 GRF_NIF_FIFO[4];
 320     uint32 GRF_OS_REG[4];
 321     uint32 GRF_SOC_CON5_8[4];
 322     uint32 reserved3;
 323     GPIO_T GRF_GPIO_PULL_1_4[4];
 324     uint32 reserved4[2];
 325     uint32 GRF_IO_VSEL;
 326     uint32 reserved5[2];
 327     uint32 GRF_GPIO1L_SR;
 328     uint32 GRF_GPIO1H_SR;
 329     uint32 GRF_GPIO2L_SR;
 330     uint32 GRF_GPIO2H_SR;
 331     uint32 GRF_GPIO3L_SR;
 332     uint32 GRF_GPIO3H_SR;
 333     uint32 GRF_GPIO4L_SR;
 334     uint32 GRF_GPIO4H_SR;
 335     GPIO_T GRF_GPIO_E[5];
 336     uint32 reserved6[2];
 337     uint32 GRF_FLASH_DATA_PULL;
 338     uint32 GRF_FLASH_DATA_E;
 339     uint32 GRF_FLASH_DATA_SR;
 340     uint32 reserved7;
 341     uint32 GRF_USBPHY_CON[12];
 342     uint32 GRF_DFI_STAT[4];
 343     uint32 reserved8[(0x300-0x260)/4];
 344     uint32 GRF_SECURE_BOOT_STATUS;
 345 } REG_FILE_RK319X, *pREG_FILE_RK319X;
 346
 347 /*
 348  * PCTL
 349  */
 350 //SCTL
 351 #define INIT_STATE                     (0)
 352 #define CFG_STATE                      (1)
 353 #define GO_STATE                       (2)
 354 #define SLEEP_STATE                    (3)
 355 #define WAKEUP_STATE                   (4)
 356
 357 //STAT
 358 #define Init_mem                       (0)
 359 #define Config                         (1)
 360 #define Config_req                     (2)
 361 #define Access                         (3)
 362 #define Access_req                     (4)
 363 #define Low_power                      (5)
 364 #define Low_power_entry_req            (6)
 365 #define Low_power_exit_req             (7)
 366
 367 //MCFG
 368 #define mddr_lpddr2_clk_stop_idle(n)   ((n)<<24)
 369 #define pd_idle(n)                     ((n)<<8)
 370 #define mddr_en                        (2<<22)
 371 #define lpddr2_en                      (3<<22)
 372 #define ddr2_en                        (0<<5)
 373 #define ddr3_en                        (1<<5)
 374 #define lpddr2_s2                      (0<<6)
 375 #define lpddr2_s4                      (1<<6)
 376 #define mddr_lpddr2_bl_2               (0<<20)
 377 #define mddr_lpddr2_bl_4               (1<<20)
 378 #define mddr_lpddr2_bl_8               (2<<20)
 379 #define mddr_lpddr2_bl_16              (3<<20)
 380 #define ddr2_ddr3_bl_4                 (0)
 381 #define ddr2_ddr3_bl_8                 (1)
 382 #define tfaw_cfg(n)                    (((n)-4)<<18)
 383 #define pd_exit_slow                   (0<<17)
 384 #define pd_exit_fast                   (1<<17)
 385 #define pd_type(n)                     ((n)<<16)
 386 #define two_t_en(n)                    ((n)<<3)
 387 #define bl8int_en(n)                   ((n)<<2)
 388 #define cke_or_en(n)                   ((n)<<1)
 389
 390 //POWCTL
 391 #define power_up_start                 (1<<0)
 392
 393 //POWSTAT
 394 #define power_up_done                  (1<<0)
 395
 396 //DFISTSTAT0
 397 #define dfi_init_complete              (1<<0)
 398
 399 //CMDTSTAT
 400 #define cmd_tstat                      (1<<0)
 401
 402 //CMDTSTATEN
 403 #define cmd_tstat_en                   (1<<1)
 404
 405 //MCMD
 406 #define Deselect_cmd                   (0)
 407 #define PREA_cmd                       (1)
 408 #define REF_cmd                        (2)
 409 #define MRS_cmd                        (3)
 410 #define ZQCS_cmd                       (4)
 411 #define ZQCL_cmd                       (5)
 412 #define RSTL_cmd                       (6)
 413 #define MRR_cmd                        (8)
 414 #define DPDE_cmd                       (9)
 415
 416 #define lpddr2_op(n)                   ((n)<<12)
 417 #define lpddr2_ma(n)                   ((n)<<4)
 418
 419 #define bank_addr(n)                   ((n)<<17)
 420 #define cmd_addr(n)                    ((n)<<4)
 421
 422 #define start_cmd                      (1u<<31)
 423
 424 typedef union STAT_Tag
 425 {
 426     uint32 d32;
 427     struct
 428     {
 429         unsigned ctl_stat : 3;
 430         unsigned reserved3 : 1;
 431         unsigned lp_trig : 3;
 432         unsigned reserved7_31 : 25;
 433     }b;
 434 }STAT_T;
 435
 436 typedef union SCFG_Tag
 437 {
 438     uint32 d32;
 439     struct
 440     {
 441         unsigned hw_low_power_en : 1;
 442         unsigned reserved1_5 : 5;
 443         unsigned nfifo_nif1_dis : 1;
 444         unsigned reserved7 : 1;
 445         unsigned bbflags_timing : 4;
 446         unsigned reserved12_31 : 20;
 447     } b;
 448 }SCFG_T;
 449
 450 /* DDR Controller register struct */
 451 typedef volatile struct DDR_REG_Tag
 452 {
 453     //Operational State, Control, and Status Registers
 454     SCFG_T SCFG;                   //State Configuration Register
 455     volatile uint32 SCTL;                   //State Control Register
 456     STAT_T STAT;                   //State Status Register
 457     volatile uint32 INTRSTAT;               //Interrupt Status Register
 458     uint32 reserved0[(0x40-0x10)/4];
 459     //Initailization Control and Status Registers
 460     volatile uint32 MCMD;                   //Memory Command Register
 461     volatile uint32 POWCTL;                 //Power Up Control Registers
 462     volatile uint32 POWSTAT;                //Power Up Status Register
 463     volatile uint32 CMDTSTAT;               //Command Timing Status Register
 464     volatile uint32 CMDTSTATEN;             //Command Timing Status Enable Register
 465     uint32 reserved1[(0x60-0x54)/4];
 466     volatile uint32 MRRCFG0;                //MRR Configuration 0 Register
 467     volatile uint32 MRRSTAT0;               //MRR Status 0 Register
 468     volatile uint32 MRRSTAT1;               //MRR Status 1 Register
 469     uint32 reserved2[(0x7c-0x6c)/4];
 470     //Memory Control and Status Registers
 471     volatile uint32 MCFG1;                  //Memory Configuration 1 Register
 472     volatile uint32 MCFG;                   //Memory Configuration Register
 473     volatile uint32 PPCFG;                  //Partially Populated Memories Configuration Register
 474     volatile uint32 MSTAT;                  //Memory Status Register
 475     volatile uint32 LPDDR2ZQCFG;            //LPDDR2 ZQ Configuration Register
 476     uint32 reserved3;
 477     //DTU Control and Status Registers
 478     volatile uint32 DTUPDES;                //DTU Status Register
 479     volatile uint32 DTUNA;                  //DTU Number of Random Addresses Created Register
 480     volatile uint32 DTUNE;                  //DTU Number of Errors Register
 481     volatile uint32 DTUPRD0;                //DTU Parallel Read 0
 482     volatile uint32 DTUPRD1;                //DTU Parallel Read 1
 483     volatile uint32 DTUPRD2;                //DTU Parallel Read 2
 484     volatile uint32 DTUPRD3;                //DTU Parallel Read 3
 485     volatile uint32 DTUAWDT;                //DTU Address Width
 486     uint32 reserved4[(0xc0-0xb4)/4];
 487     //Memory Timing Registers
 488     volatile uint32 TOGCNT1U;               //Toggle Counter 1U Register
 489     volatile uint32 TINIT;                  //t_init Timing Register
 490     volatile uint32 TRSTH;                  //Reset High Time Register
 491     volatile uint32 TOGCNT100N;             //Toggle Counter 100N Register
 492     volatile uint32 TREFI;                  //t_refi Timing Register
 493     volatile uint32 TMRD;                   //t_mrd Timing Register
 494     volatile uint32 TRFC;                   //t_rfc Timing Register
 495     volatile uint32 TRP;                    //t_rp Timing Register
 496     volatile uint32 TRTW;                   //t_rtw Timing Register
 497     volatile uint32 TAL;                    //AL Latency Register
 498     volatile uint32 TCL;                    //CL Timing Register
 499     volatile uint32 TCWL;                   //CWL Register
 500     volatile uint32 TRAS;                   //t_ras Timing Register
 501     volatile uint32 TRC;                    //t_rc Timing Register
 502     volatile uint32 TRCD;                   //t_rcd Timing Register
 503     volatile uint32 TRRD;                   //t_rrd Timing Register
 504     volatile uint32 TRTP;                   //t_rtp Timing Register
 505     volatile uint32 TWR;                    //t_wr Timing Register
 506     volatile uint32 TWTR;                   //t_wtr Timing Register
 507     volatile uint32 TEXSR;                  //t_exsr Timing Register
 508     volatile uint32 TXP;                    //t_xp Timing Register
 509     volatile uint32 TXPDLL;                 //t_xpdll Timing Register
 510     volatile uint32 TZQCS;                  //t_zqcs Timing Register
 511     volatile uint32 TZQCSI;                 //t_zqcsi Timing Register
 512     volatile uint32 TDQS;                   //t_dqs Timing Register
 513     volatile uint32 TCKSRE;                 //t_cksre Timing Register
 514     volatile uint32 TCKSRX;                 //t_cksrx Timing Register
 515     volatile uint32 TCKE;                   //t_cke Timing Register
 516     volatile uint32 TMOD;                   //t_mod Timing Register
 517     volatile uint32 TRSTL;                  //Reset Low Timing Register
 518     volatile uint32 TZQCL;                  //t_zqcl Timing Register
 519     volatile uint32 TMRR;                   //t_mrr Timing Register
 520     volatile uint32 TCKESR;                 //t_ckesr Timing Register
 521     volatile uint32 TDPD;                   //t_dpd Timing Register
 522     uint32 reserved5[(0x180-0x148)/4];
 523     //ECC Configuration, Control, and Status Registers
 524     volatile uint32 ECCCFG;                   //ECC Configuration Register
 525     volatile uint32 ECCTST;                   //ECC Test Register
 526     volatile uint32 ECCCLR;                   //ECC Clear Register
 527     volatile uint32 ECCLOG;                   //ECC Log Register
 528     uint32 reserved6[(0x200-0x190)/4];
 529     //DTU Control and Status Registers
 530     volatile uint32 DTUWACTL;                 //DTU Write Address Control Register
 531     volatile uint32 DTURACTL;                 //DTU Read Address Control Register
 532     volatile uint32 DTUCFG;                   //DTU Configuration Control Register
 533     volatile uint32 DTUECTL;                  //DTU Execute Control Register
 534     volatile uint32 DTUWD0;                   //DTU Write Data 0
 535     volatile uint32 DTUWD1;                   //DTU Write Data 1
 536     volatile uint32 DTUWD2;                   //DTU Write Data 2
 537     volatile uint32 DTUWD3;                   //DTU Write Data 3
 538     volatile uint32 DTUWDM;                   //DTU Write Data Mask
 539     volatile uint32 DTURD0;                   //DTU Read Data 0
 540     volatile uint32 DTURD1;                   //DTU Read Data 1
 541     volatile uint32 DTURD2;                   //DTU Read Data 2
 542     volatile uint32 DTURD3;                   //DTU Read Data 3
 543     volatile uint32 DTULFSRWD;                //DTU LFSR Seed for Write Data Generation
 544     volatile uint32 DTULFSRRD;                //DTU LFSR Seed for Read Data Generation
 545     volatile uint32 DTUEAF;                   //DTU Error Address FIFO
 546     //DFI Control Registers
 547     volatile uint32 DFITCTRLDELAY;            //DFI tctrl_delay Register
 548     volatile uint32 DFIODTCFG;                //DFI ODT Configuration Register
 549     volatile uint32 DFIODTCFG1;               //DFI ODT Configuration 1 Register
 550     volatile uint32 DFIODTRANKMAP;            //DFI ODT Rank Mapping Register
 551     //DFI Write Data Registers
 552     volatile uint32 DFITPHYWRDATA;            //DFI tphy_wrdata Register
 553     volatile uint32 DFITPHYWRLAT;             //DFI tphy_wrlat Register
 554     uint32 reserved7[(0x260-0x258)/4];
 555     volatile uint32 DFITRDDATAEN;             //DFI trddata_en Register
 556     volatile uint32 DFITPHYRDLAT;             //DFI tphy_rddata Register
 557     uint32 reserved8[(0x270-0x268)/4];
 558     //DFI Update Registers
 559     volatile uint32 DFITPHYUPDTYPE0;          //DFI tphyupd_type0 Register
 560     volatile uint32 DFITPHYUPDTYPE1;          //DFI tphyupd_type1 Register
 561     volatile uint32 DFITPHYUPDTYPE2;          //DFI tphyupd_type2 Register
 562     volatile uint32 DFITPHYUPDTYPE3;          //DFI tphyupd_type3 Register
 563     volatile uint32 DFITCTRLUPDMIN;           //DFI tctrlupd_min Register
 564     volatile uint32 DFITCTRLUPDMAX;           //DFI tctrlupd_max Register
 565     volatile uint32 DFITCTRLUPDDLY;           //DFI tctrlupd_dly Register
 566     uint32 reserved9;
 567     volatile uint32 DFIUPDCFG;                //DFI Update Configuration Register
 568     volatile uint32 DFITREFMSKI;              //DFI Masked Refresh Interval Register
 569     volatile uint32 DFITCTRLUPDI;             //DFI tctrlupd_interval Register
 570     uint32 reserved10[(0x2ac-0x29c)/4];
 571     volatile uint32 DFITRCFG0;                //DFI Training Configuration 0 Register
 572     volatile uint32 DFITRSTAT0;               //DFI Training Status 0 Register
 573     volatile uint32 DFITRWRLVLEN;             //DFI Training dfi_wrlvl_en Register
 574     volatile uint32 DFITRRDLVLEN;             //DFI Training dfi_rdlvl_en Register
 575     volatile uint32 DFITRRDLVLGATEEN;         //DFI Training dfi_rdlvl_gate_en Register
 576     //DFI Status Registers
 577     volatile uint32 DFISTSTAT0;               //DFI Status Status 0 Register
 578     volatile uint32 DFISTCFG0;                //DFI Status Configuration 0 Register
 579     volatile uint32 DFISTCFG1;                //DFI Status configuration 1 Register
 580     uint32 reserved11;
 581     volatile uint32 DFITDRAMCLKEN;            //DFI tdram_clk_enalbe Register
 582     volatile uint32 DFITDRAMCLKDIS;           //DFI tdram_clk_disalbe Register
 583     volatile uint32 DFISTCFG2;                //DFI Status configuration 2 Register
 584     volatile uint32 DFISTPARCLR;              //DFI Status Parity Clear Register
 585     volatile uint32 DFISTPARLOG;              //DFI Status Parity Log Register
 586     uint32 reserved12[(0x2f0-0x2e4)/4];
 587     //DFI Low Power Registers
 588     volatile uint32 DFILPCFG0;                //DFI Low Power Configuration 0 Register
 589     uint32 reserved13[(0x300-0x2f4)/4];
 590     //DFI Training 2 Registers
 591     volatile uint32 DFITRWRLVLRESP0;          //DFI Training dif_wrlvl_resp Status 0 Register
 592     volatile uint32 DFITRWRLVLRESP1;          //DFI Training dif_wrlvl_resp Status 1 Register
 593     volatile uint32 DFITRWRLVLRESP2;          //DFI Training dif_wrlvl_resp Status 2 Register
 594     volatile uint32 DFITRRDLVLRESP0;          //DFI Training dif_rdlvl_resp Status 0 Register
 595     volatile uint32 DFITRRDLVLRESP1;          //DFI Training dif_rdlvl_resp Status 1 Register
 596     volatile uint32 DFITRRDLVLRESP2;          //DFI Training dif_rdlvl_resp Status 2 Register
 597     volatile uint32 DFITRWRLVLDELAY0;         //DFI Training dif_wrlvl_delay Configuration 0 Register
 598     volatile uint32 DFITRWRLVLDELAY1;         //DFI Training dif_wrlvl_delay Configuration 1 Register
 599     volatile uint32 DFITRWRLVLDELAY2;         //DFI Training dif_wrlvl_delay Configuration 2 Register
 600     volatile uint32 DFITRRDLVLDELAY0;         //DFI Training dif_rdlvl_delay Configuration 0 Register
 601     volatile uint32 DFITRRDLVLDELAY1;         //DFI Training dif_rdlvl_delay Configuration 1 Register
 602     volatile uint32 DFITRRDLVLDELAY2;         //DFI Training dif_rdlvl_delay Configuration 2 Register
 603     volatile uint32 DFITRRDLVLGATEDELAY0;     //DFI Training dif_rdlvl_gate_delay Configuration 0 Register
 604     volatile uint32 DFITRRDLVLGATEDELAY1;     //DFI Training dif_rdlvl_gate_delay Configuration 1 Register
 605     volatile uint32 DFITRRDLVLGATEDELAY2;     //DFI Training dif_rdlvl_gate_delay Configuration 2 Register
 606     volatile uint32 DFITRCMD;                 //DFI Training Command Register
 607     uint32 reserved14[(0x3f8-0x340)/4];
 608     //IP Status Registers
 609     volatile uint32 IPVR;                     //IP Version Register
 610     volatile uint32 IPTR;                     //IP Type Register
 611 }DDR_REG_T, *pDDR_REG_T;
 612
 613 #define pDDR_Reg ((pDDR_REG_T)SDRAMC_BASE_ADDR)
 614
 615 /*
 616  * PUBL
 617  */
 618 //PIR
 619 #define INIT                 (1<<0)
 620 #define DLLSRST              (1<<1)
 621 #define DLLLOCK              (1<<2)
 622 #define ZCAL                 (1<<3)
 623 #define ITMSRST              (1<<4)
 624 #define DRAMRST              (1<<5)
 625 #define DRAMINIT             (1<<6)
 626 #define QSTRN                (1<<7)
 627 #define EYETRN               (1<<8)
 628 #define ICPC                 (1<<16)
 629 #define DLLBYP               (1<<17)
 630 #define CTLDINIT             (1<<18)
 631 #define CLRSR                (1<<28)
 632 #define LOCKBYP              (1<<29)
 633 #define ZCALBYP              (1<<30)
 634 #define INITBYP              (1u<<31)
 635
 636 //PGCR
 637 #define DFTLMT(n)            ((n)<<3)
 638 #define DFTCMP(n)            ((n)<<2)
 639 #define DQSCFG(n)            ((n)<<1)
 640 #define ITMDMD(n)            ((n)<<0)
 641 #define RANKEN(n)            ((n)<<18)
 642
 643 //PGSR
 644 #define IDONE                (1<<0)
 645 #define DLDONE               (1<<1)
 646 #define ZCDONE               (1<<2)
 647 #define DIDONE               (1<<3)
 648 #define DTDONE               (1<<4)
 649 #define DTERR                (1<<5)
 650 #define DTIERR               (1<<6)
 651 #define DFTERR               (1<<7)
 652 #define TQ                   (1u<<31)
 653
 654 //PTR0
 655 #define tITMSRST(n)          ((n)<<18)
 656 #define tDLLLOCK(n)          ((n)<<6)
 657 #define tDLLSRST(n)          ((n)<<0)
 658
 659 //PTR1
 660 #define tDINIT1(n)           ((n)<<19)
 661 #define tDINIT0(n)           ((n)<<0)
 662
 663 //PTR2
 664 #define tDINIT3(n)           ((n)<<17)
 665 #define tDINIT2(n)           ((n)<<0)
 666
 667 //DSGCR
 668 #define DQSGE(n)             ((n)<<8)
 669 #define DQSGX(n)             ((n)<<5)
 670
 671 typedef union DCR_Tag
 672 {
 673     uint32 d32;
 674     struct
 675     {
 676         unsigned DDRMD : 3;
 677         unsigned DDR8BNK : 1;
 678         unsigned PDQ : 3;
 679         unsigned MPRDQ : 1;
 680         unsigned DDRTYPE : 2;
 681         unsigned reserved10_26 : 17;
 682         unsigned NOSRA : 1;
 683         unsigned DDR2T : 1;
 684         unsigned UDIMM : 1;
 685         unsigned RDIMM : 1;
 686         unsigned TPD : 1;
 687     } b;
 688 }DCR_T;
 689
 690 typedef volatile struct DATX8_REG_Tag
 691 {
 692     volatile uint32 DXGCR;                 //DATX8 General Configuration Register
 693     volatile uint32 DXGSR[2];              //DATX8 General Status Register
 694     volatile uint32 DXDLLCR;               //DATX8 DLL Control Register
 695     volatile uint32 DXDQTR;                //DATX8 DQ Timing Register
 696     volatile uint32 DXDQSTR;               //DATX8 DQS Timing Register
 697     uint32 reserved[0x80-0x76];
 698 }DATX8_REG_T;
 699
 700 /* DDR PHY register struct */
 701 typedef volatile struct DDRPHY_REG_Tag
 702 {
 703     volatile uint32 RIDR;                   //Revision Identification Register
 704     volatile uint32 PIR;                    //PHY Initialization Register
 705     volatile uint32 PGCR;                   //PHY General Configuration Register
 706     volatile uint32 PGSR;                   //PHY General Status Register
 707     volatile uint32 DLLGCR;                 //DLL General Control Register
 708     volatile uint32 ACDLLCR;                //AC DLL Control Register
 709     volatile uint32 PTR[3];                 //PHY Timing Registers 0-2
 710     volatile uint32 ACIOCR;                 //AC I/O Configuration Register
 711     volatile uint32 DXCCR;                  //DATX8 Common Configuration Register
 712     volatile uint32 DSGCR;                  //DDR System General Configuration Register
 713     DCR_T DCR;                    //DRAM Configuration Register
 714     volatile uint32 DTPR[3];                //DRAM Timing Parameters Register 0-2
 715     volatile uint32 MR[4];                    //Mode Register 0-3
 716     volatile uint32 ODTCR;                  //ODT Configuration Register
 717     volatile uint32 DTAR;                   //Data Training Address Register
 718     volatile uint32 DTDR[2];                //Data Training Data Register 0-1
 719
 720     uint32 reserved1[0x30-0x18];
 721     uint32 DCU[0x38-0x30];
 722     uint32 reserved2[0x40-0x38];
 723     uint32 BIST[0x51-0x40];
 724     uint32 reserved3[0x60-0x51];
 725
 726     volatile uint32 ZQ0CR[2];               //ZQ 0 Impedance Control Register 0-1
 727     volatile uint32 ZQ0SR[2];               //ZQ 0 Impedance Status Register 0-1
 728     volatile uint32 ZQ1CR[2];               //ZQ 1 Impedance Control Register 0-1
 729     volatile uint32 ZQ1SR[2];               //ZQ 1 Impedance Status Register 0-1
 730     volatile uint32 ZQ2CR[2];               //ZQ 2 Impedance Control Register 0-1
 731     volatile uint32 ZQ2SR[2];               //ZQ 2 Impedance Status Register 0-1
 732     volatile uint32 ZQ3CR[2];               //ZQ 3 Impedance Control Register 0-1
 733     volatile uint32 ZQ3SR[2];               //ZQ 3 Impedance Status Register 0-1
 734
 735     DATX8_REG_T     DATX8[9];               //DATX8 Register
 736 }DDRPHY_REG_T, *pDDRPHY_REG_T;
 737
 738 #define pPHY_Reg ((pDDRPHY_REG_T)DDR_PUBL_BASE)
 739
 740 #if defined(CONFIG_ARCH_RK30) && (!defined(CONFIG_ARCH_RK3066B))
 741 #define pPMU_Reg               ((pPMU_FILE)PMU_BASE_ADDR)
 742 #define pCRU_Reg               ((pCRU_REG)CRU_BASE_ADDR)
 743 #define pGRF_Reg               ((pREG_FILE)REG_FILE_BASE_ADDR)
 744 #define GET_DDR3_DS_ODT()      ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0xb<<5) | 0xb)
 745 #define GET_LPDDR2_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x8<<5) | 0x8)
 746 #define GET_3188_PLUS_STATUS() (false)
 747 #define GET_DPLL_STATUS()      (true)
 748 #define DDR_GET_RANK_2_ROW15() (pGRF_Reg->GRF_SOC_CON[2] &  (1<<1))
 749 #define DDR_GET_BANK_2_RANK()  (pGRF_Reg->GRF_SOC_CON[2] &  (1<<2))
 750 #define DDR_HW_WAKEUP(en)      do{pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | en);}while(0)
 751 #define READ_GRF_REG()         (pGRF_Reg->GRF_SOC_CON[2])
 752 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS0 & (1<<4))
 753 #define SET_DDR_PLL_SRC(src, div)   do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<8))<<16)|(src<<8)| div;}while(0)
 754 #define GET_DDR_PLL_SRC()      (DPLL)
 755 #define SET_DDRPHY_CLKGATE(dis)  do{pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (dis<<2);}while(0)
 756 #elif defined(CONFIG_ARCH_RK30) && defined(CONFIG_ARCH_RK3066B)
 757 #define pPMU_Reg               ((pPMU_FILE)PMU_BASE_ADDR)
 758 #define pCRU_Reg               ((pCRU_REG)CRU_BASE_ADDR)
 759 #define pGRF_Reg               ((pREG_FILE_RK3066B)REG_FILE_BASE_ADDR)
 760 #define GET_DDR3_DS_ODT()      ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 761 #define GET_LPDDR2_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 762 #define GET_3188_PLUS_STATUS() (false)
 763 #define GET_DPLL_STATUS()      (true)
 764 #define DDR_GET_RANK_2_ROW15() (pGRF_Reg->GRF_SOC_CON[2] &  (1<<1))
 765 #define DDR_GET_BANK_2_RANK()  (pGRF_Reg->GRF_SOC_CON[2] &  (1<<2))
 766 #define DDR_HW_WAKEUP(en)      do{pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | en);}while(0)
 767 #define READ_GRF_REG()         (pGRF_Reg->GRF_SOC_CON[2])
 768 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS0 & (1<<5))
 769 #define SET_DDR_PLL_SRC(src, div)   do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<8))<<16)|(src<<8)| div;}while(0)
 770 #define GET_DDR_PLL_SRC()      (DPLL)
 771 #define DDR_GPLL_CLK_GATE(en)  do{pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000 | (en<<7);}while(0)
 772 #define SET_DDRPHY_CLKGATE(dis)  do{pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (dis<<2);}while(0)
 773 #elif defined(CONFIG_ARCH_RK3188)
 774 #define pPMU_Reg               ((pPMU_FILE)PMU_BASE_ADDR)
 775 #define pCRU_Reg               ((pCRU_REG)CRU_BASE_ADDR)
 776 #define pGRF_Reg               ((pREG_FILE_RK3066B)REG_FILE_BASE_ADDR)
 777 #define GET_DDR3_DS_ODT()      ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 778 #define GET_LPDDR2_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 779 #define GET_3188_PLUS_STATUS() (soc_is_rk3188plus())
 780 #define GET_DPLL_STATUS()      ((rk_pll_flag() & 0x3) ? false : true)
 781 #define DDR_GET_RANK_2_ROW15() (pGRF_Reg->GRF_SOC_CON[2] &  (1<<1))
 782 #define DDR_GET_BANK_2_RANK()  (pGRF_Reg->GRF_SOC_CON[2] &  (1<<2))
 783 #define DDR_HW_WAKEUP(en)      do{pGRF_Reg->GRF_SOC_CON[2] = (1<<16 | en);}while(0)
 784 #define READ_GRF_REG()         (pGRF_Reg->GRF_SOC_CON[2])
 785 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS0 & (1<<5))
 786 #define SET_DDR_PLL_SRC(src, div)   do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<8))<<16)|(src<<8)| div;}while(0)
 787 #define GET_DDR_PLL_SRC()      ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<8)) ? GPLL : DPLL)
 788 #define DDR_GPLL_CLK_GATE(en)  do{pCRU_Reg->CRU_CLKGATE_CON[1] = 0x00800000 | (en<<7);}while(0)
 789 #define SET_DDRPHY_CLKGATE(dis)  do{pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1<<2)<<16) | (dis<<2);}while(0)
 790 #elif defined(CONFIG_ARCH_RK319X)
 791 #define pPMU_Reg               ((pPMU_FILE_RK319X)PMU_BASE_ADDR)
 792 #define pCRU_Reg               ((pCRU_REG_RK319X)CRU_BASE_ADDR)
 793 #define pGRF_Reg               ((pREG_FILE_RK319X)REG_FILE_BASE_ADDR)
 794 #define GET_DDR3_DS_ODT()      ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 795 #define GET_LPDDR2_DS_ODT()    ((0x1<<28) | (0x2<<15) | (0x2<<10) | (0x19<<5) | 0x19)
 796 #define GET_3188_PLUS_STATUS() (true)
 797 #define GET_DPLL_STATUS()      (true)
 798 #define DDR_GET_RANK_2_ROW15() (pGRF_Reg->GRF_SOC_CON[0] &  (1<<9))
 799 #define DDR_GET_BANK_2_RANK()  (pGRF_Reg->GRF_SOC_CON[0] &  (1<<10))
 800 #define DDR_HW_WAKEUP(en)      do{pGRF_Reg->GRF_SOC_CON[0] = (1<<(16+8)) | (en<<8);}while(0)
 801 #define READ_GRF_REG()         (pGRF_Reg->GRF_SOC_CON[0])
 802 #define GET_DPLL_LOCK_STATUS() (pGRF_Reg->GRF_SOC_STATUS0 & (1<<5))
 803 #define SET_DDR_PLL_SRC(src, div)   do{pCRU_Reg->CRU_CLKSEL_CON[26] = ((0x3|(0x1<<2))<<16)|(src<<2)| div;}while(0)
 804 #define GET_DDR_PLL_SRC()      ((pCRU_Reg->CRU_CLKSEL_CON[26]&(1<<2)) ? GPLL : DPLL)
 805 #define DDR_GPLL_CLK_GATE(en)  do{pCRU_Reg->CRU_CLKGATE_CON[0] = 0x02000000 | (en<<9);}while(0)
 806 #define SET_DDRPHY_CLKGATE(dis)  do{pCRU_Reg->CRU_CLKGATE_CON[10] = ((0x1<<12)<<16) | (dis<<12);}while(0)
 807 #else
 808 #arch defined error!!
 809 #endif
 810 #define SET_PLL_MODE(pll, mode) do{pCRU_Reg->CRU_MODE_CON = ((mode<<((pll)*4))|(0x3<<(16+(pll)*4)));}while(0)
 811 #define SET_PLL_PD(pll, pd)     do{pCRU_Reg->CRU_PLL_CON[pll][3] = ((0x1<<1)<<16) | (pd<<1);}while(0)
 812
 813 #define DDR_SYS_REG()    (pPMU_Reg->PMU_PMU_SYS_REG[2])
 814 #define READ_CS_INFO()   ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>11)&0x1)+1)
 815 #define READ_BW_INFO()   (2>>(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>2)&0x3))
 816 #define READ_COL_INFO()  (9+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>9)&0x3))
 817 #define READ_BK_INFO()   (3-(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>8)&0x1))
 818 #define READ_CS0_ROW_INFO()  (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>6)&0x3))
 819 #define READ_CS1_ROW_INFO()  (13+(((pPMU_Reg->PMU_PMU_SYS_REG[2])>>4)&0x3))
 820 #define READ_DIE_BW_INFO()   (2>>(pPMU_Reg->PMU_PMU_SYS_REG[2]&0x3))
 821
 822 static const uint8_t  ddr_cfg_2_rbc[] =
 823 {
 824     /****************************/
 825     // [7:6]  bank(n:n bit bank)
 826     // [5:4]  row(13+n)
 827     // [3:2]  bank(n:n bit bank)
 828     // [1:0]  col(9+n)
 829     /****************************/
 830     //bank, row,    bank,  col
 831     ((3<<6)|(2<<4)|(0<<2)|2),  // 0 bank ahead
 832     ((0<<6)|(2<<4)|(3<<2)|1),  // 1
 833     ((0<<6)|(1<<4)|(3<<2)|1),  // 2
 834     ((0<<6)|(0<<4)|(3<<2)|1),  // 3
 835     ((0<<6)|(2<<4)|(3<<2)|2),  // 4
 836     ((0<<6)|(1<<4)|(3<<2)|2),  // 5
 837     ((0<<6)|(0<<4)|(3<<2)|2),  // 6
 838     ((0<<6)|(1<<4)|(3<<2)|0),  // 7
 839     ((0<<6)|(0<<4)|(3<<2)|0),  // 8
 840     ((1<<6)|(2<<4)|(2<<2)|2),  // 9
 841     ((1<<6)|(1<<4)|(2<<2)|2),  // 10
 842     ((1<<6)|(2<<4)|(2<<2)|1),  // 11
 843     ((1<<6)|(1<<4)|(2<<2)|1),  // 12
 844     ((1<<6)|(2<<4)|(2<<2)|0),  // 13
 845     ((1<<6)|(1<<4)|(2<<2)|0),  // 14
 846     ((3<<6)|(2<<4)|(0<<2)|1),  // 15 bank ahead
 847 };
 848
 849 /***********************************
 850  * LPDDR2 define
 851  ***********************************/
 852 //MR0 (Device Information)
 853 #define  LPDDR2_DAI    (0x1)        // 0:DAI complete, 1:DAI still in progress
 854 #define  LPDDR2_DI     (0x1<<1)     // 0:S2 or S4 SDRAM, 1:NVM
 855 #define  LPDDR2_DNVI   (0x1<<2)     // 0:DNV not supported, 1:DNV supported
 856 #define  LPDDR2_RZQI   (0x3<<3)     // 00:RZQ self test not supported, 01:ZQ-pin may connect to VDDCA or float
 857                                     // 10:ZQ-pin may short to GND.     11:ZQ-pin self test completed, no error condition detected.
 858
 859 //MR1 (Device Feature)
 860 #define LPDDR2_BL4     (0x2)
 861 #define LPDDR2_BL8     (0x3)
 862 #define LPDDR2_BL16    (0x4)
 863 #define LPDDR2_nWR(n)  (((n)-2)<<5)
 864
 865 //MR2 (Device Feature 2)
 866 #define LPDDR2_RL3_WL1  (0x1)
 867 #define LPDDR2_RL4_WL2  (0x2)
 868 #define LPDDR2_RL5_WL2  (0x3)
 869 #define LPDDR2_RL6_WL3  (0x4)
 870 #define LPDDR2_RL7_WL4  (0x5)
 871 #define LPDDR2_RL8_WL4  (0x6)
 872
 873 //MR3 (IO Configuration 1)
 874 #define LPDDR2_DS_34    (0x1)
 875 #define LPDDR2_DS_40    (0x2)
 876 #define LPDDR2_DS_48    (0x3)
 877 #define LPDDR2_DS_60    (0x4)
 878 #define LPDDR2_DS_80    (0x6)
 879 #define LPDDR2_DS_120   (0x7)   //optional
 880
 881 //MR4 (Device Temperature)
 882 #define LPDDR2_tREF_MASK (0x7)
 883 #define LPDDR2_4_tREF    (0x1)
 884 #define LPDDR2_2_tREF    (0x2)
 885 #define LPDDR2_1_tREF    (0x3)
 886 #define LPDDR2_025_tREF  (0x5)
 887 #define LPDDR2_025_tREF_DERATE    (0x6)
 888
 889 #define LPDDR2_TUF       (0x1<<7)
 890
 891 //MR8 (Basic configuration 4)
 892 #define LPDDR2_S4        (0x0)
 893 #define LPDDR2_S2        (0x1)
 894 #define LPDDR2_N         (0x2)
 895 #define LPDDR2_Density(mr8)  (8<<(((mr8)>>2)&0xf))   // Unit:MB
 896 #define LPDDR2_IO_Width(mr8) (32>>(((mr8)>>6)&0x3))
 897
 898 //MR10 (Calibration)
 899 #define LPDDR2_ZQINIT   (0xFF)
 900 #define LPDDR2_ZQCL     (0xAB)
 901 #define LPDDR2_ZQCS     (0x56)
 902 #define LPDDR2_ZQRESET  (0xC3)
 903
 904 //MR16 (PASR Bank Mask)
 905 // S2 SDRAM Only
 906 #define LPDDR2_PASR_Full (0x0)
 907 #define LPDDR2_PASR_1_2  (0x1)
 908 #define LPDDR2_PASR_1_4  (0x2)
 909 #define LPDDR2_PASR_1_8  (0x3)
 910
 911 //MR17 (PASR Segment Mask) 1Gb-8Gb S4 SDRAM only
 912
 913 //MR32 (DQ Calibration Pattern A)
 914
 915 //MR40 (DQ Calibration Pattern B)
 916
 917 /***********************************
 918  * DDR3 define
 919  ***********************************/
 920 //mr0 for ddr3
 921 #define DDR3_BL8          (0)
 922 #define DDR3_BC4_8        (1)
 923 #define DDR3_BC4          (2)
 924 #define DDR3_CL(n)        (((((n)-4)&0x7)<<4)|((((n)-4)&0x8)>>1))
 925 #define DDR3_WR(n)        (((n)&0x7)<<9)
 926 #define DDR3_DLL_RESET    (1<<8)
 927 #define DDR3_DLL_DeRESET  (0<<8)
 928
 929 //mr1 for ddr3
 930 #define DDR3_DLL_ENABLE    (0)
 931 #define DDR3_DLL_DISABLE   (1)
 932 #define DDR3_MR1_AL(n)  (((n)&0x3)<<3)
 933
 934 #define DDR3_DS_40            (0)
 935 #define DDR3_DS_34            (1<<1)
 936 #define DDR3_Rtt_Nom_DIS      (0)
 937 #define DDR3_Rtt_Nom_60       (1<<2)
 938 #define DDR3_Rtt_Nom_120      (1<<6)
 939 #define DDR3_Rtt_Nom_40       ((1<<2)|(1<<6))
 940
 941     //mr2 for ddr3
 942 #define DDR3_MR2_CWL(n) ((((n)-5)&0x7)<<3)
 943 #define DDR3_Rtt_WR_DIS       (0)
 944 #define DDR3_Rtt_WR_60        (1<<9)
 945 #define DDR3_Rtt_WR_120       (2<<9)
 946
 947 /***********************************
 948  * DDR2 define
 949  ***********************************/
 950 //MR;                     //Mode Register
 951 #define DDR2_BL4           (2)
 952 #define DDR2_BL8           (3)
 953 #define DDR2_CL(n)         (((n)&0x7)<<4)
 954 #define DDR2_WR(n)        ((((n)-1)&0x7)<<9)
 955 #define DDR2_DLL_RESET    (1<<8)
 956 #define DDR2_DLL_DeRESET  (0<<8)
 957
 958 //EMR;                    //Extended Mode Register
 959 #define DDR2_DLL_ENABLE    (0)
 960 #define DDR2_DLL_DISABLE   (1)
 961
 962 #define DDR2_STR_FULL     (0)
 963 #define DDR2_STR_REDUCE   (1<<1)
 964 #define DDR2_AL(n)        (((n)&0x7)<<3)
 965 #define DDR2_Rtt_Nom_DIS      (0)
 966 #define DDR2_Rtt_Nom_150      (0x40)
 967 #define DDR2_Rtt_Nom_75       (0x4)
 968 #define DDR2_Rtt_Nom_50       (0x44)
 969
 970 /***********************************
 971  * LPDDR define
 972  ***********************************/
 973 #define mDDR_BL2           (1)
 974 #define mDDR_BL4           (2)
 975 #define mDDR_BL8           (3)
 976 #define mDDR_CL(n)         (((n)&0x7)<<4)
 977
 978 #define mDDR_DS_Full       (0)
 979 #define mDDR_DS_1_2        (1<<5)
 980 #define mDDR_DS_1_4        (2<<5)
 981 #define mDDR_DS_1_8        (3<<5)
 982 #define mDDR_DS_3_4        (4<<5)
 983
 984 static const uint8_t ddr3_cl_cwl[22][7]={
 985 /*speed   0~330         331~400       401~533        534~666       667~800        801~933      934~1066
 986  * tCK    >3            2.5~3         1.875~2.5      1.5~1.875     1.25~1.5       1.07~1.25    0.938~1.07
 987  *        cl<<4, cwl    cl<<4, cwl    cl<<4, cwl              */
 988          {((5<<4)|5),   ((5<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800D (5-5-5)
 989          {((5<<4)|5),   ((6<<4)|5),   0         ,    0,            0,             0,            0}, //DDR3_800E (6-6-6)
 990
 991          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    0,            0,             0,            0}, //DDR3_1066E (6-6-6)
 992          {((5<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    0,            0,             0,            0}, //DDR3_1066F (7-7-7)
 993          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    0,            0,             0,            0}, //DDR3_1066G (8-8-8)
 994
 995          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   0,             0,            0}, //DDR3_1333F (7-7-7)
 996          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   0,             0,            0}, //DDR3_1333G (8-8-8)
 997          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((9<<4)|7),   0,             0,            0}, //DDR3_1333H (9-9-9)
 998          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  0,             0,            0}, //DDR3_1333J (10-10-10)
 999
1000          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((8<<4)|8),    0,            0}, //DDR3_1600G (8-8-8)
1001          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    0,            0}, //DDR3_1600H (9-9-9)
1002          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   0,            0}, //DDR3_1600J (10-10-10)
1003          {((5<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   0,            0}, //DDR3_1600K (11-11-11)
1004
1005          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  0}, //DDR3_1866J (10-10-10)
1006          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((8<<4)|7),   ((10<<4)|8),   ((11<<4)|9),  0}, //DDR3_1866K (11-11-11)
1007          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((12<<4)|9),  0}, //DDR3_1866L (12-12-12)
1008          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  0}, //DDR3_1866M (13-13-13)
1009
1010          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((7<<4)|7),   ((9<<4)|8),    ((10<<4)|9),  ((11<<4)|10)}, //DDR3_2133K (11-11-11)
1011          {((5<<4)|5),   ((5<<4)|5),   ((6<<4)|6),    ((8<<4)|7),   ((9<<4)|8),    ((11<<4)|9),  ((12<<4)|10)}, //DDR3_2133L (12-12-12)
1012          {((5<<4)|5),   ((5<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((10<<4)|8),   ((12<<4)|9),  ((13<<4)|10)}, //DDR3_2133M (13-13-13)
1013          {((6<<4)|5),   ((6<<4)|5),   ((7<<4)|6),    ((9<<4)|7),   ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)},  //DDR3_2133N (14-14-14)
1014
1015          {((6<<4)|5),   ((6<<4)|5),   ((8<<4)|6),    ((10<<4)|7),  ((11<<4)|8),   ((13<<4)|9),  ((14<<4)|10)} //DDR3_DEFAULT
1016 };
1017
1018 static const uint16_t ddr3_tRC_tFAW[22]={
1019 /**    tRC    tFAW   */
1020     ((50<<8)|50), //DDR3_800D (5-5-5)
1021     ((53<<8)|50), //DDR3_800E (6-6-6)
1022
1023     ((49<<8)|50), //DDR3_1066E (6-6-6)
1024     ((51<<8)|50), //DDR3_1066F (7-7-7)
1025     ((53<<8)|50), //DDR3_1066G (8-8-8)
1026
1027     ((47<<8)|45), //DDR3_1333F (7-7-7)
1028     ((48<<8)|45), //DDR3_1333G (8-8-8)
1029     ((50<<8)|45), //DDR3_1333H (9-9-9)
1030     ((51<<8)|45), //DDR3_1333J (10-10-10)
1031
1032     ((45<<8)|40), //DDR3_1600G (8-8-8)
1033     ((47<<8)|40), //DDR3_1600H (9-9-9)
1034     ((48<<8)|40), //DDR3_1600J (10-10-10)
1035     ((49<<8)|40), //DDR3_1600K (11-11-11)
1036
1037     ((45<<8)|35), //DDR3_1866J (10-10-10)
1038     ((46<<8)|35), //DDR3_1866K (11-11-11)
1039     ((47<<8)|35), //DDR3_1866L (12-12-12)
1040     ((48<<8)|35), //DDR3_1866M (13-13-13)
1041
1042     ((44<<8)|35), //DDR3_2133K (11-11-11)
1043     ((45<<8)|35), //DDR3_2133L (12-12-12)
1044     ((46<<8)|35), //DDR3_2133M (13-13-13)
1045     ((47<<8)|35), //DDR3_2133N (14-14-14)
1046
1047     ((53<<8)|50)  //DDR3_DEFAULT
1048 };
1049
1050 typedef enum DRAM_TYPE_Tag
1051 {
1052     LPDDR = 0,
1053     DDR,
1054     DDR2,
1055     DDR3,
1056     LPDDR2,
1057
1058     DRAM_MAX
1059 }DRAM_TYPE;
1060
1061 typedef struct PCTRL_TIMING_Tag
1062 {
1063     uint32 ddrFreq;
1064     //Memory Timing Registers
1065     uint32 togcnt1u;               //Toggle Counter 1U Register
1066     uint32 tinit;                  //t_init Timing Register
1067     uint32 trsth;                  //Reset High Time Register
1068     uint32 togcnt100n;             //Toggle Counter 100N Register
1069     uint32 trefi;                  //t_refi Timing Register
1070     uint32 tmrd;                   //t_mrd Timing Register
1071     uint32 trfc;                   //t_rfc Timing Register
1072     uint32 trp;                    //t_rp Timing Register
1073     uint32 trtw;                   //t_rtw Timing Register
1074     uint32 tal;                    //AL Latency Register
1075     uint32 tcl;                    //CL Timing Register
1076     uint32 tcwl;                   //CWL Register
1077     uint32 tras;                   //t_ras Timing Register
1078     uint32 trc;                    //t_rc Timing Register
1079     uint32 trcd;                   //t_rcd Timing Register
1080     uint32 trrd;                   //t_rrd Timing Register
1081     uint32 trtp;                   //t_rtp Timing Register
1082     uint32 twr;                    //t_wr Timing Register
1083     uint32 twtr;                   //t_wtr Timing Register
1084     uint32 texsr;                  //t_exsr Timing Register
1085     uint32 txp;                    //t_xp Timing Register
1086     uint32 txpdll;                 //t_xpdll Timing Register
1087     uint32 tzqcs;                  //t_zqcs Timing Register
1088     uint32 tzqcsi;                 //t_zqcsi Timing Register
1089     uint32 tdqs;                   //t_dqs Timing Register
1090     uint32 tcksre;                 //t_cksre Timing Register
1091     uint32 tcksrx;                 //t_cksrx Timing Register
1092     uint32 tcke;                   //t_cke Timing Register
1093     uint32 tmod;                   //t_mod Timing Register
1094     uint32 trstl;                  //Reset Low Timing Register
1095     uint32 tzqcl;                  //t_zqcl Timing Register
1096     uint32 tmrr;                   //t_mrr Timing Register
1097     uint32 tckesr;                 //t_ckesr Timing Register
1098     uint32 tdpd;                   //t_dpd Timing Register
1099 }PCTL_TIMING_T;
1100
1101 typedef union DTPR_0_Tag
1102 {
1103     uint32 d32;
1104     struct
1105     {
1106         unsigned tMRD : 2;
1107         unsigned tRTP : 3;
1108         unsigned tWTR : 3;
1109         unsigned tRP : 4;
1110         unsigned tRCD : 4;
1111         unsigned tRAS : 5;
1112         unsigned tRRD : 4;
1113         unsigned tRC : 6;
1114         unsigned tCCD : 1;
1115     } b;
1116 }DTPR_0_T;
1117
1118 typedef union DTPR_1_Tag
1119 {
1120     uint32 d32;
1121     struct
1122     {
1123         unsigned tAOND : 2;
1124         unsigned tRTW : 1;
1125         unsigned tFAW : 6;
1126         unsigned tMOD : 2;
1127         unsigned tRTODT : 1;
1128         unsigned reserved12_15 : 4;
1129         unsigned tRFC : 8;
1130         unsigned tDQSCK : 3;
1131         unsigned tDQSCKmax : 3;
1132         unsigned reserved30_31 : 2;
1133     } b;
1134 }DTPR_1_T;
1135
1136 typedef union DTPR_2_Tag
1137 {
1138     uint32 d32;
1139     struct
1140     {
1141         unsigned tXS : 10;
1142         unsigned tXP : 5;
1143         unsigned tCKE : 4;
1144         unsigned tDLLK : 10;
1145         unsigned reserved29_31 : 3;
1146     } b;
1147 }DTPR_2_T;
1148
1149 typedef struct PHY_TIMING_Tag
1150 {
1151     DTPR_0_T  dtpr0;
1152     DTPR_1_T  dtpr1;
1153     DTPR_2_T  dtpr2;
1154     uint32    mr[4];   //LPDDR2 no MR0, mr[2] is mDDR MR1
1155 }PHY_TIMING_T;
1156
1157 typedef union NOC_TIMING_Tag
1158 {
1159     uint32 d32;
1160     struct
1161     {
1162         unsigned ActToAct : 6;
1163         unsigned RdToMiss : 6;
1164         unsigned WrToMiss : 6;
1165         unsigned BurstLen : 3;
1166         unsigned RdToWr : 5;
1167         unsigned WrToRd : 5;
1168         unsigned BwRatio : 1;
1169     } b;
1170 }NOC_TIMING_T;
1171
1172 typedef struct PCTL_REG_Tag
1173 {
1174     uint32 SCFG;
1175     uint32 CMDTSTATEN;
1176     uint32 MCFG1;
1177     uint32 MCFG;
1178     PCTL_TIMING_T pctl_timing;
1179     //DFI Control Registers
1180     uint32 DFITCTRLDELAY;
1181     uint32 DFIODTCFG;
1182     uint32 DFIODTCFG1;
1183     uint32 DFIODTRANKMAP;
1184     //DFI Write Data Registers
1185     uint32 DFITPHYWRDATA;
1186     uint32 DFITPHYWRLAT;
1187     //DFI Read Data Registers
1188     uint32 DFITRDDATAEN;
1189     uint32 DFITPHYRDLAT;
1190     //DFI Update Registers
1191     uint32 DFITPHYUPDTYPE0;
1192     uint32 DFITPHYUPDTYPE1;
1193     uint32 DFITPHYUPDTYPE2;
1194     uint32 DFITPHYUPDTYPE3;
1195     uint32 DFITCTRLUPDMIN;
1196     uint32 DFITCTRLUPDMAX;
1197     uint32 DFITCTRLUPDDLY;
1198     uint32 DFIUPDCFG;
1199     uint32 DFITREFMSKI;
1200     uint32 DFITCTRLUPDI;
1201     //DFI Status Registers
1202     uint32 DFISTCFG0;
1203     uint32 DFISTCFG1;
1204     uint32 DFITDRAMCLKEN;
1205     uint32 DFITDRAMCLKDIS;
1206     uint32 DFISTCFG2;
1207     //DFI Low Power Register
1208     uint32 DFILPCFG0;
1209 }PCTL_REG_T;
1210
1211 typedef struct PUBL_REG_Tag
1212 {
1213     uint32 PIR;
1214     uint32 PGCR;
1215     uint32 DLLGCR;
1216     uint32 ACDLLCR;
1217     uint32 PTR[3];
1218     uint32 ACIOCR;
1219     uint32 DXCCR;
1220     uint32 DSGCR;
1221     uint32 DCR;
1222     PHY_TIMING_T phy_timing;
1223     uint32 ODTCR;
1224     uint32 DTAR;
1225     uint32 ZQ0CR0;
1226     uint32 ZQ1CR0;
1227
1228     uint32 DX0GCR;
1229     uint32 DX0DLLCR;
1230     uint32 DX0DQTR;
1231     uint32 DX0DQSTR;
1232
1233     uint32 DX1GCR;
1234     uint32 DX1DLLCR;
1235     uint32 DX1DQTR;
1236     uint32 DX1DQSTR;
1237
1238     uint32 DX2GCR;
1239     uint32 DX2DLLCR;
1240     uint32 DX2DQTR;
1241     uint32 DX2DQSTR;
1242
1243     uint32 DX3GCR;
1244     uint32 DX3DLLCR;
1245     uint32 DX3DQTR;
1246     uint32 DX3DQSTR;
1247 }PUBL_REG_T;
1248
1249 typedef struct BACKUP_REG_Tag
1250 {
1251     PCTL_REG_T pctl;
1252     PUBL_REG_T publ;
1253     uint32 DdrConf;
1254     NOC_TIMING_T noc_timing;
1255     uint32 DdrMode;
1256     uint32 ReadLatency;
1257 }BACKUP_REG_T;
1258
1259 BACKUP_REG_T DEFINE_PIE_DATA(ddr_reg);
1260 static BACKUP_REG_T *p_ddr_reg;
1261 static __attribute__((aligned(4096))) uint32_t ddr_data_training_buf[32];
1262 uint32_t DEFINE_PIE_DATA(mem_type);    // 0:LPDDR, 1:DDR, 2:DDR2, 3:DDR3, 4:LPDDR2
1263 static uint32_t *p_mem_type;
1264 static uint32_t ddr_speed_bin;    // used for ddr3 only
1265 static uint32_t ddr_capability_per_die;  // one chip cs capability
1266 uint32_t DEFINE_PIE_DATA(ddr_freq);
1267 static uint32_t ddr_freq;
1268 uint32_t DEFINE_PIE_DATA(ddr_sr_idle);
1269
1270 /***********************************
1271  * ARCH Relative Data and Function
1272  ***********************************/
1273 static __sramdata uint32_t clkr;
1274 static __sramdata uint32_t clkf;
1275 static __sramdata uint32_t clkod;
1276 static __sramdata uint32_t dpllvaluel=0,gpllvaluel=0;
1277 uint32_t DEFINE_PIE_DATA(ddr_select_gpll_div); // 0-Disable, 1-1:1, 2-2:1, 4-4:1
1278 static uint32_t *p_ddr_select_gpll_div;
1279 bool DEFINE_PIE_DATA(ddr_soc_is_rk3188_plus);
1280 static bool ddr_soc_is_rk3188_plus;
1281 bool DEFINE_PIE_DATA(ddr_rk3188_dpll_is_good);
1282 static bool ddr_rk3188_dpll_is_good;
1283
1284 static void __sramfunc ddr_delayus(uint32_t us);
1285
1286 static uint32_t __sramfunc ddr_get_pll_freq_sram(PLL_ID pll_id)   //APLL-1;CPLL-2;DPLL-3;GPLL-4
1287 {
1288     uint32_t ret = 0;
1289
1290      // freq = (Fin/NR)*NF/OD
1291     if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1)             // DPLL Normal mode
1292         ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0xffff)+1)    // NF = 2*(CLKF+1)
1293                 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1)           // NR = CLKR+1
1294                 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0x3F)+1));             // OD = 2^CLKOD
1295     else
1296         ret = 24;
1297
1298     return ret;
1299 }
1300
1301 static noinline uint32_t ddr_get_pll_freq(PLL_ID pll_id)   //APLL-1;CPLL-2;DPLL-3;GPLL-4
1302 {
1303     uint32_t ret = 0;
1304
1305      // freq = (Fin/NR)*NF/OD
1306     if(((pCRU_Reg->CRU_MODE_CON>>(pll_id*4))&3) == 1)             // DPLL Normal mode
1307         ret= 24 *((pCRU_Reg->CRU_PLL_CON[pll_id][1]&0xffff)+1)    // NF = 2*(CLKF+1)
1308                 /((((pCRU_Reg->CRU_PLL_CON[pll_id][0]>>8)&0x3f)+1)           // NR = CLKR+1
1309                 *((pCRU_Reg->CRU_PLL_CON[pll_id][0]&0x3F)+1));             // OD = 2^CLKOD
1310     else
1311         ret = 24;
1312
1313     return ret;
1314 }
1315
1316 #if defined(CONFIG_ARCH_RK30) && (!defined(CONFIG_ARCH_RK3066B))
1317 /*****************************************
1318 NR   NO     NF               Fout                       freq Step     finally use
1319 1    8      12.5 - 62.5      37.5MHz  - 187.5MHz        3MHz          50MHz   <= 150MHz
1320 1    6      12.5 - 62.5      50MHz    - 250MHz          4MHz          150MHz  <= 200MHz
1321 1    4      12.5 - 62.5      75MHz    - 375MHz          6MHz          200MHz  <= 300MHz
1322 1    2      12.5 - 62.5      150MHz   - 750MHz          12MHz         300MHz  <= 600MHz
1323 1    1      12.5 - 62.5      300MHz   - 1500MHz         24MHz         600MHz  <= 1200MHz
1324 ******************************************/
1325 static uint32_t __sramfunc ddr_set_pll_3066(uint32_t nMHz, uint32_t set)
1326 {
1327     uint32_t ret = 0;
1328     int delay = 1000;
1329     //NOÒ»¶¨ÒªÅ¼Êý,NR¾¡Á¿Ð¡£¬jitter¾Í»áÐ¡
1330
1331     if(nMHz == 24)
1332     {
1333         ret = 24;
1334         goto out;
1335     }
1336
1337     if(!set)
1338     {
1339         if(nMHz <= 150)
1340         {
1341             clkod = 8;
1342         }
1343         else if(nMHz <= 200)
1344         {
1345             clkod = 6;
1346         }
1347         else if(nMHz <= 300)
1348         {
1349             clkod = 4;
1350         }
1351         else if(nMHz <= 600)
1352         {
1353             clkod = 2;
1354         }
1355         else
1356         {
1357             clkod = 1;
1358         }
1359         clkr = 1;
1360         clkf=(nMHz*clkr*clkod)/24;
1361         ret = (24*clkf)/(clkr*clkod);
1362     }
1363     else
1364     {
1365         SET_PLL_MODE(DPLL,0);            //PLL slow-mode
1366         dsb();
1367         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
1368         pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
1369         pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
1370         pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
1371         ddr_delayus(1);
1372         pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
1373         dsb();
1374         while (delay > 0)
1375         {
1376             ddr_delayus(1);
1377             if (GET_DPLL_LOCK_STATUS())
1378             break;
1379             delay--;
1380         }
1381         SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL, clk_ddr_src:clk_ddrphy = 1:1
1382         SET_PLL_MODE(DPLL,1);            //PLL normal
1383         dsb();
1384     }
1385 out:
1386     return ret;
1387 }
1388 #endif
1389
1390 #if (defined(CONFIG_ARCH_RK30) && defined(CONFIG_ARCH_RK3066B)) || defined(CONFIG_ARCH_RK3188)
1391 /*****************************************
1392 RK3066B
1393 NR   NO     NF                      Fout                       freq Step     finally use
1394 1    14     46 - 91          78MHz  -   157MHz          1.7MHz        78MHz<= 150MHz
1395 1    8      46 - 91          137MHz  -  275MHz          3MHz          150MHz<= 200MHz
1396 1    6      46 - 91          183MHz   - 366MHz          4MHz          200MHz<= 300MHz
1397 1    4      46 - 91          275MHz   - 550MHz          6MHz          300MHz<= 550MHz
1398 1    2      46 - 91          550MHz   - 1100MHz         12MHz         550MHz<= 1100MHz
1399 1    1      46 - 91          1100MHz  - 2200MHz         24MHz         1100MHz<= 2200MHz
1400 ******************************************/
1401 static uint32_t __sramfunc ddr_set_pll_rk3066b(uint32_t nMHz, uint32_t set)
1402 {
1403     uint32_t ret = 0;
1404     int delay = 1000;
1405
1406     if(nMHz == 24)
1407     {
1408         ret = 24;
1409         goto out;
1410     }
1411
1412     if(!set)
1413     {
1414         dpllvaluel = ddr_get_pll_freq_sram(DPLL);
1415         gpllvaluel = ddr_get_pll_freq_sram(GPLL);
1416
1417         if(DATA(ddr_rk3188_dpll_is_good) == false)    //if rk3188 DPLL is bad,use GPLL
1418         {
1419             if( (gpllvaluel < 200) ||(gpllvaluel > 2000))
1420             {
1421                 ///ddr_print("DPLL is bad and GPLL freq = %dMHz,Not suitable for ddr_clock\n",gpllvaluel);
1422                 return 0;
1423             }
1424
1425             if(gpllvaluel > 1000)    //GPLL:1000MHz-2000MHz
1426             {
1427                 DATA(ddr_select_gpll_div)=4;    //DDR_CLCOK:250MHz-500MHz
1428             }
1429             else if(gpllvaluel > 800)    //GPLL:800MHz-1000MHz
1430             {
1431                 if(nMHz > 250)
1432                     DATA(ddr_select_gpll_div)=2;    //DDR_CLCOK:400MHz-500MHz
1433                 else
1434                     DATA(ddr_select_gpll_div)=4;    //DDR_CLCOK:200MHz-250MHz
1435             }
1436             else if(gpllvaluel > 500)    //GPLL:500MHz-800MHz
1437             {
1438                 DATA(ddr_select_gpll_div)=2;    //DDR_CLCOK:250MHz-400MHz
1439             }
1440             else     //GPLL:200MHz-500MHz
1441             {
1442                 DATA(ddr_select_gpll_div)=1;    //DDR_CLCOK:200MHz-500MHz
1443             }
1444         }
1445
1446         if(DATA(ddr_select_gpll_div) > 0)
1447         {
1448             ret=gpllvaluel/DATA(ddr_select_gpll_div);
1449         }
1450         else
1451         {
1452             if(nMHz <= 150)
1453             {
1454                 clkod = 14;
1455             }
1456             else if(nMHz <= 200)
1457             {
1458                 clkod = 8;
1459             }
1460             else if(nMHz <= 300)
1461             {
1462                 clkod = 6;
1463             }
1464             else if(nMHz <= 550)
1465             {
1466                 clkod = 4;
1467             }
1468             else if(nMHz <= 1100)
1469             {
1470                 clkod = 2;
1471             }
1472             else
1473             {
1474                 clkod = 1;
1475             }
1476             clkr = 1;
1477             clkf=(nMHz*clkr*clkod)/24;
1478             ret = (24*clkf)/(clkr*clkod);
1479         }
1480
1481     }
1482     else
1483     {
1484         if(DATA(ddr_select_gpll_div) > 0)
1485         {
1486             DDR_GPLL_CLK_GATE(0);
1487             SET_DDR_PLL_SRC(1, (DATA(ddr_select_gpll_div)>>1));  //clk_ddr_src = G PLL, clk_ddr_src:clk_ddrphy = 4:1/2:1/1:1
1488             dsb();
1489         }
1490         else if((nMHz==dpllvaluel) && (set == 1))
1491         {
1492             SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1493             dsb();
1494         }
1495         else
1496         {
1497             SET_PLL_MODE(DPLL,0);            //PLL slow-mode
1498             dsb();
1499
1500             pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET_RK3066B;
1501              ddr_delayus(1);
1502             pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR_RK3066B(clkr) | NO_RK3066B(clkod);
1503             pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF_RK3066B(clkf);
1504             //     pCRU_Reg->CRU_PLL_CON[pll_id][2] = NB(clkf>>1);
1505             ddr_delayus(1);
1506             pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET_RK3066B;
1507             dsb();
1508             while (delay > 0)
1509             {
1510                 ddr_delayus(1);
1511                 if (GET_DPLL_LOCK_STATUS())
1512                     break;
1513                 delay--;
1514             }
1515
1516             if(set == 1)
1517                 SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1518             SET_PLL_MODE(DPLL,1);            //PLL normal
1519             dsb();
1520         }
1521     }
1522     dsb();
1523 out:
1524     return ret;
1525 }
1526 #endif
1527
1528 #if defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X)
1529 /*****************************************
1530 NR   NO     NF               Fout                       freq Step     finally use
1531 1    8      12.5 - 62.5      37.5MHz  - 187.5MHz        3MHz          50MHz   <= 150MHz
1532 1    6      12.5 - 62.5      50MHz    - 250MHz          4MHz          150MHz  <= 200MHz
1533 1    4      12.5 - 62.5      75MHz    - 375MHz          6MHz          200MHz  <= 300MHz
1534 1    2      12.5 - 62.5      150MHz   - 750MHz          12MHz         300MHz  <= 600MHz
1535 1    1      12.5 - 62.5      300MHz   - 1500MHz         24MHz         600MHz  <= 1200MHz
1536 ******************************************/
1537 static uint32_t __sramfunc ddr_set_pll_rk3188_plus(uint32_t nMHz, uint32_t set)
1538 {
1539     uint32_t ret = 0;
1540     int delay = 1000;
1541
1542     if(nMHz == 24)
1543     {
1544         ret = 24;
1545         goto out;
1546     }
1547
1548     if(!set)
1549     {
1550         dpllvaluel = ddr_get_pll_freq_sram(DPLL);
1551         gpllvaluel = ddr_get_pll_freq_sram(GPLL);
1552
1553         if(DATA(ddr_select_gpll_div) > 0)
1554         {
1555             ret = gpllvaluel/DATA(ddr_select_gpll_div);
1556         }
1557         else
1558         {
1559             if(nMHz <= 150)
1560             {
1561                 clkod = 8;
1562             }
1563             else if(nMHz <= 200)
1564             {
1565                 clkod = 6;
1566             }
1567             else if(nMHz <= 300)
1568             {
1569                 clkod = 4;
1570             }
1571             else if(nMHz <= 600)
1572             {
1573                 clkod = 2;
1574             }
1575             else
1576             {
1577                 clkod = 1;
1578             }
1579             clkr = 1;
1580             clkf=(nMHz*clkr*clkod)/24;
1581             ret = (24*clkf)/(clkr*clkod);
1582         }
1583
1584     }
1585     else
1586     {
1587         if(DATA(ddr_select_gpll_div) > 0)
1588         {
1589             DDR_GPLL_CLK_GATE(0);
1590             SET_DDR_PLL_SRC(1, (DATA(ddr_select_gpll_div)>>1));  //clk_ddr_src = G PLL,clk_ddr_src:clk_ddrphy = 4:1/2:1/1:1
1591             dsb();
1592         }
1593         else if((nMHz==dpllvaluel) && (set == 1))
1594         {
1595             SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1596             dsb();
1597         }
1598         else
1599         {
1600             SET_PLL_MODE(DPLL,0);            //PLL slow-mode
1601             dsb();
1602
1603             pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_RESET;
1604              ddr_delayus(1);
1605             pCRU_Reg->CRU_PLL_CON[DPLL][0] = NR(clkr) | NO(clkod);
1606             pCRU_Reg->CRU_PLL_CON[DPLL][1] = NF(clkf);
1607             pCRU_Reg->CRU_PLL_CON[DPLL][2] = NB(clkf>>1);
1608             ddr_delayus(1);
1609             pCRU_Reg->CRU_PLL_CON[DPLL][3] = PLL_DE_RESET;
1610             dsb();
1611             while (delay > 0)
1612             {
1613                 ddr_delayus(1);
1614                 if (GET_DPLL_LOCK_STATUS())
1615                     break;
1616                 delay--;
1617             }
1618
1619             if(set == 1)
1620                 SET_DDR_PLL_SRC(0, 0);  //clk_ddr_src = DDR PLL,clk_ddr_src:clk_ddrphy = 1:1
1621             SET_PLL_MODE(DPLL,1);            //PLL normal
1622             dsb();
1623         }
1624     }
1625     dsb();
1626 out:
1627     return ret;
1628 }
1629 #endif
1630
1631 uint32_t PIE_FUNC(ddr_set_pll)(uint32_t nMHz, uint32_t set)
1632 {
1633 #if defined(CONFIG_ARCH_RK3188)
1634     if(DATA(ddr_soc_is_rk3188_plus) == true)
1635         return ddr_set_pll_rk3188_plus(nMHz,set);
1636     else
1637         return ddr_set_pll_rk3066b(nMHz,set);
1638 #elif defined(CONFIG_ARCH_RK30) && defined(CONFIG_ARCH_RK3066B)
1639     return ddr_set_pll_rk3066b(nMHz,set);
1640 #elif defined(CONFIG_ARCH_RK319X)
1641     return ddr_set_pll_rk3188_plus(nMHz,set);
1642 #else
1643     return ddr_set_pll_3066(nMHz,set);
1644 #endif
1645 }
1646 EXPORT_PIE_SYMBOL(FUNC(ddr_set_pll));
1647 static uint32_t (*p_ddr_set_pll)(uint32_t nMHz, uint32_t set);
1648
1649 #ifdef CONFIG_ARCH_RK319X
1650 static void __sramfunc idle_port(void)
1651 {
1652     int i;
1653     uint32 clk_gate[16];
1654
1655     //save clock gate status
1656     for(i=0;i<16;i++)
1657         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1658
1659     //enable all clock gate for request idle
1660     for(i=0;i<16;i++)
1661         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1662
1663     /*
1664     pPMU_Reg->PMU_NOC_REQ |= idle_req_bp2ap_rk319x;
1665     dsb();
1666     while(((pPMU_Reg->PMU_NOC_ST) & idle_req_bp2ap_rk319x) == 0);
1667     */
1668
1669     pPMU_Reg->PMU_NOC_REQ |= idle_req_dma_cfg_rk319x;
1670     dsb();
1671     while(((pPMU_Reg->PMU_NOC_ST) & idle_req_dma_cfg_rk319x) == 0);
1672
1673     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st_rk319x) == 0 )
1674     {
1675         pPMU_Reg->PMU_NOC_REQ |= idle_req_peri_cfg_rk319x;
1676         dsb();
1677         while( (pPMU_Reg->PMU_NOC_ST & idle_peri_rk319x) == 0 );
1678     }
1679
1680     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st_rk319x) == 0 )
1681     {
1682         pPMU_Reg->PMU_NOC_REQ |= idle_req_vio_cfg_rk319x;
1683         dsb();
1684         while( (pPMU_Reg->PMU_NOC_ST & idle_vio_rk319x) == 0 );
1685     }
1686
1687     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st_rk319x) == 0 )
1688     {
1689         pPMU_Reg->PMU_NOC_REQ |= idle_req_video_cfg_rk319x;
1690         dsb();
1691         while( (pPMU_Reg->PMU_NOC_ST & idle_video_rk319x) == 0 );
1692     }
1693
1694     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st_rk319x) == 0 )
1695     {
1696         pPMU_Reg->PMU_NOC_REQ |= idle_req_gpu_cfg_rk319x;
1697         dsb();
1698         while( (pPMU_Reg->PMU_NOC_ST & idle_gpu_rk319x) == 0 );
1699     }
1700
1701     //resume clock gate status
1702     for(i=0;i<16;i++)
1703         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1704 }
1705
1706 static void __sramfunc deidle_port(void)
1707 {
1708     int i;
1709     uint32 clk_gate[16];
1710
1711     //save clock gate status
1712     for(i=0;i<16;i++)
1713         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1714
1715     //enable all clock gate for request idle
1716     for(i=0;i<16;i++)
1717         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1718
1719     /*
1720     pPMU_Reg->PMU_NOC_REQ &= ~idle_req_bp2ap_rk319x;
1721     dsb();
1722     while( (pPMU_Reg->PMU_NOC_ST & idle_bp2ap_rk319x) != 0 );
1723     */
1724
1725     pPMU_Reg->PMU_NOC_REQ &= ~idle_req_dma_cfg_rk319x;
1726     dsb();
1727     while( (pPMU_Reg->PMU_NOC_ST & idle_dma_rk319x) != 0 );
1728
1729     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st_rk319x) == 0 )
1730     {
1731         pPMU_Reg->PMU_NOC_REQ &= ~idle_req_peri_cfg_rk319x;
1732         dsb();
1733         while( (pPMU_Reg->PMU_NOC_ST & idle_peri_rk319x) != 0 );
1734     }
1735
1736     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st_rk319x) == 0 )
1737     {
1738         pPMU_Reg->PMU_NOC_REQ &= ~idle_req_vio_cfg_rk319x;
1739         dsb();
1740         while( (pPMU_Reg->PMU_NOC_ST & idle_vio_rk319x) != 0 );
1741     }
1742
1743     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st_rk319x) == 0 )
1744     {
1745         pPMU_Reg->PMU_NOC_REQ &= ~idle_req_video_cfg_rk319x;
1746         dsb();
1747         while( (pPMU_Reg->PMU_NOC_ST & idle_video_rk319x) != 0 );
1748     }
1749
1750     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st_rk319x) == 0 )
1751     {
1752         pPMU_Reg->PMU_NOC_REQ &= ~idle_req_gpu_cfg_rk319x;
1753         dsb();
1754         while( (pPMU_Reg->PMU_NOC_ST & idle_gpu_rk319x) != 0 );
1755     }
1756
1757     //resume clock gate status
1758     for(i=0;i<16;i++)
1759         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1760
1761 }
1762 #else
1763 static void __sramfunc idle_port(void)
1764 {
1765     int i;
1766     uint32 clk_gate[10];
1767
1768     //save clock gate status
1769     for(i=0;i<10;i++)
1770         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1771
1772     //enable all clock gate for request idle
1773     for(i=0;i<10;i++)
1774         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1775
1776     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
1777     {
1778 #ifdef CONFIG_ARCH_RK3188
1779         pPMU_Reg->PMU_MISC_CON1 |= idle_req_dma_cfg;
1780         dsb();
1781         while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) == 0 );
1782 #else
1783         pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
1784         dsb();
1785         while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
1786 #endif
1787     }
1788
1789     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
1790     {
1791         pPMU_Reg->PMU_MISC_CON1 |= idle_req_peri_cfg;
1792         dsb();
1793         while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) == 0 );
1794     }
1795
1796     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
1797     {
1798         pPMU_Reg->PMU_MISC_CON1 |= idle_req_vio_cfg;
1799         dsb();
1800         while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) == 0 );
1801     }
1802
1803     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
1804     {
1805         pPMU_Reg->PMU_MISC_CON1 |= idle_req_video_cfg;
1806         dsb();
1807         while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) == 0 );
1808     }
1809
1810     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
1811     {
1812         pPMU_Reg->PMU_MISC_CON1 |= idle_req_gpu_cfg;
1813         dsb();
1814         while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) == 0 );
1815     }
1816
1817     //resume clock gate status
1818     for(i=0;i<10;i++)
1819         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1820 }
1821
1822 static void __sramfunc deidle_port(void)
1823 {
1824     int i;
1825     uint32 clk_gate[10];
1826
1827     //save clock gate status
1828     for(i=0;i<10;i++)
1829         clk_gate[i]=pCRU_Reg->CRU_CLKGATE_CON[i];
1830
1831     //enable all clock gate for request idle
1832     for(i=0;i<10;i++)
1833         pCRU_Reg->CRU_CLKGATE_CON[i]=0xffff0000;
1834
1835     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
1836     {
1837
1838 #ifdef CONFIG_ARCH_RK3188
1839         pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_dma_cfg;
1840         dsb();
1841         while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) != 0 );
1842 #else
1843         pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
1844         dsb();
1845         while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
1846 #endif
1847     }
1848     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
1849     {
1850         pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_peri_cfg;
1851         dsb();
1852         while( (pPMU_Reg->PMU_PWRDN_ST & idle_peri) != 0 );
1853     }
1854
1855     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_vio_pwr_st) == 0 )
1856     {
1857         pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_vio_cfg;
1858         dsb();
1859         while( (pPMU_Reg->PMU_PWRDN_ST & idle_vio) != 0 );
1860     }
1861
1862     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_video_pwr_st) == 0 )
1863     {
1864         pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_video_cfg;
1865         dsb();
1866         while( (pPMU_Reg->PMU_PWRDN_ST & idle_video) != 0 );
1867     }
1868
1869     if ( (pPMU_Reg->PMU_PWRDN_ST & pd_gpu_pwr_st) == 0 )
1870     {
1871         pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_gpu_cfg;
1872         dsb();
1873         while( (pPMU_Reg->PMU_PWRDN_ST & idle_gpu) != 0 );
1874     }
1875
1876     //resume clock gate status
1877     for(i=0;i<10;i++)
1878         pCRU_Reg->CRU_CLKGATE_CON[i]=  (clk_gate[i] | 0xffff0000);
1879
1880 }
1881 #endif
1882
1883 /***********************************
1884  * Only DDR Relative Function
1885  ***********************************/
1886
1887 /****************************************************************************
1888 Internal sram us delay function
1889 Cpu highest frequency is 1.6 GHz
1890 1 cycle = 1/1.6 ns
1891 1 us = 1000 ns = 1000 * 1.6 cycles = 1600 cycles
1892 *****************************************************************************/
1893 static __sramdata volatile uint32_t loops_per_us;
1894
1895 #define LPJ_100MHZ  999456UL
1896
1897 static void __sramfunc ddr_delayus(uint32_t us)
1898 {
1899     do
1900     {
1901         unsigned int i = (loops_per_us*us);
1902         if (i < 7) i = 7;
1903         barrier();
1904         asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
1905     } while (0);
1906 }
1907
1908 static __sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
1909 {
1910     uint32 i;
1911
1912     for(i=0; i<words; i++)
1913     {
1914         pDest[i] = pSrc[i];
1915     }
1916 }
1917
1918 static uint32 ddr_get_row(void)
1919 {
1920     uint32 i;
1921     uint32 row;
1922
1923     if(DDR_SYS_REG())
1924     {
1925         row=READ_CS0_ROW_INFO();
1926     }
1927     else
1928     {
1929         i = *(volatile uint32*)SysSrv_DdrConf;
1930         row = 13+((ddr_cfg_2_rbc[i]>>4)&0x3);
1931         if(DDR_GET_RANK_2_ROW15())
1932         {
1933             row += 1;
1934         }
1935     }
1936     return row;
1937 }
1938
1939 static uint32 ddr_get_bank(void)
1940 {
1941     uint32 i;
1942     uint32 bank;
1943
1944     if(DDR_SYS_REG())
1945     {
1946         bank = READ_BK_INFO();
1947     }
1948     else
1949     {
1950         i = *(volatile uint32*)SysSrv_DdrConf;
1951         bank = ((ddr_cfg_2_rbc[i]>>6)&0x3) + ((ddr_cfg_2_rbc[i]>>2)&0x3);
1952         if(DDR_GET_BANK_2_RANK())
1953         {
1954             bank -= 1;
1955         }
1956     }
1957     return bank;
1958 }
1959
1960 static uint32 ddr_get_col(void)
1961 {
1962     uint32 i;
1963     uint32 col;
1964
1965     if(DDR_SYS_REG())
1966     {
1967         col=READ_COL_INFO();
1968     }
1969     else
1970     {
1971         i = *(volatile uint32*)SysSrv_DdrConf;
1972         col = 9+(ddr_cfg_2_rbc[i]&0x3);
1973         if(pDDR_Reg->PPCFG & 1)
1974         {
1975             col +=1;
1976         }
1977     }
1978     return col;
1979 }
1980
1981 static uint32 ddr_get_bw(void)
1982 {
1983     uint32 bw;
1984
1985     if(pDDR_Reg->PPCFG & 1)
1986     {
1987         bw=1;
1988     }
1989     else
1990     {
1991         bw=2;
1992     }
1993     return bw;
1994 }
1995
1996 static uint32 ddr_get_cs(void)
1997 {
1998     uint32 cs;
1999
2000     switch((pPHY_Reg->PGCR>>18) & 0xF)
2001     {
2002         case 0xF:
2003             cs = 4;
2004         case 7:
2005             cs = 3;
2006             break;
2007         case 3:
2008             cs = 2;
2009             break;
2010         default:
2011             cs = 1;
2012             break;
2013     }
2014     return cs;
2015 }
2016
2017 static uint32_t ddr_get_datatraing_addr(void)
2018 {
2019     uint32_t          value=0;
2020     uint32_t          addr;
2021     uint32_t          col = 0;
2022     uint32_t          row = 0;
2023     uint32_t          bank = 0;
2024     uint32_t          bw = 0;
2025     uint32_t          i;
2026
2027     // caculate aglined physical address
2028     addr =  __pa((unsigned long)ddr_data_training_buf);
2029     if(addr&0x3F)
2030     {
2031         addr += (64-(addr&0x3F));
2032     }
2033     addr -= 0x60000000;
2034     // find out col£¬row£¬bank
2035     row = ddr_get_row();
2036     bank = ddr_get_bank();
2037     col = ddr_get_col();
2038     bw = ddr_get_bw();
2039     // according different address mapping, caculate DTAR register value
2040     i = (*(volatile uint32*)SysSrv_DdrConf);
2041     value |= (addr>>bw) & ((0x1<<col)-1);  // col
2042     if(row==16)
2043     {
2044         value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & 0x7FFF) << 12;  // row
2045         value |= (((addr>>(bw+col+bank+15))&0x1)<<15)<<12;
2046         row = 15;  //use for bank
2047     }
2048     else
2049     {
2050         value |= ((addr>>(bw+col+((ddr_cfg_2_rbc[i]>>2)&0x3))) & ((0x1<<row)-1)) << 12;  // row
2051     }
2052     if(((ddr_cfg_2_rbc[i]>>6)&0x3)==1)
2053     {
2054         value |= (((addr>>(bw+col)) & 0x3) << 28)
2055                  | (((addr>>(bw+col+2+row)) & (bank-2))  << 30);  // bank
2056     }
2057     else if(((ddr_cfg_2_rbc[i]>>6)&0x3)==3)
2058     {
2059         value |= (((addr>>(bw+col+row)) & ((0x1<<bank)-1))  << 28);  // bank
2060     }
2061     else
2062     {
2063         value |= (((addr>>(bw+col)) & 0x7) << 28);  // bank
2064     }
2065
2066     return value;
2067 }
2068
2069 static __sramfunc void ddr_reset_dll(void)
2070 {
2071     pPHY_Reg->ACDLLCR &= ~0x40000000;
2072     pPHY_Reg->DATX8[0].DXDLLCR &= ~0x40000000;
2073     pPHY_Reg->DATX8[1].DXDLLCR &= ~0x40000000;
2074     if(!(pDDR_Reg->PPCFG & 1))
2075     {
2076         pPHY_Reg->DATX8[2].DXDLLCR &= ~0x40000000;
2077         pPHY_Reg->DATX8[3].DXDLLCR &= ~0x40000000;
2078     }
2079     ddr_delayus(1);
2080     pPHY_Reg->ACDLLCR |= 0x40000000;
2081     pPHY_Reg->DATX8[0].DXDLLCR |= 0x40000000;
2082     pPHY_Reg->DATX8[1].DXDLLCR |= 0x40000000;
2083     if(!(pDDR_Reg->PPCFG & 1))
2084     {
2085         pPHY_Reg->DATX8[2].DXDLLCR |= 0x40000000;
2086         pPHY_Reg->DATX8[3].DXDLLCR |= 0x40000000;
2087     }
2088     ddr_delayus(1);
2089 }
2090
2091 static __sramfunc void ddr_move_to_Lowpower_state(void)
2092 {
2093     volatile uint32 value;
2094
2095     while(1)
2096     {
2097         value = pDDR_Reg->STAT.b.ctl_stat;
2098         if(value == Low_power)
2099         {
2100             break;
2101         }
2102         switch(value)
2103         {
2104             case Init_mem:
2105                 pDDR_Reg->SCTL = CFG_STATE;
2106                 dsb();
2107                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
2108             case Config:
2109                 pDDR_Reg->SCTL = GO_STATE;
2110                 dsb();
2111                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
2112             case Access:
2113                 pDDR_Reg->SCTL = SLEEP_STATE;
2114                 dsb();
2115                 while((pDDR_Reg->STAT.b.ctl_stat) != Low_power);
2116                 break;
2117             default:  //Transitional state
2118                 break;
2119         }
2120     }
2121 }
2122
2123 static __sramfunc void ddr_move_to_Access_state(void)
2124 {
2125     volatile uint32 value;
2126
2127     //set auto self-refresh idle
2128     pDDR_Reg->MCFG1=(pDDR_Reg->MCFG1&0xffffff00) | DATA(ddr_sr_idle) | (1<<31);
2129     dsb();
2130
2131     while(1)
2132     {
2133         value = pDDR_Reg->STAT.b.ctl_stat;
2134         if((value == Access)
2135            || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power)))
2136         {
2137             break;
2138         }
2139         switch(value)
2140         {
2141             case Low_power:
2142                 pDDR_Reg->SCTL = WAKEUP_STATE;
2143                 dsb();
2144                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
2145                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
2146                 break;
2147             case Init_mem:
2148                 pDDR_Reg->SCTL = CFG_STATE;
2149                 dsb();
2150                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
2151             case Config:
2152                 pDDR_Reg->SCTL = GO_STATE;
2153                 dsb();
2154                 while(!(((pDDR_Reg->STAT.b.ctl_stat) == Access)
2155                       || ((pDDR_Reg->STAT.b.lp_trig == 1) && ((pDDR_Reg->STAT.b.ctl_stat) == Low_power))));
2156                 break;
2157             default:  //Transitional state
2158                 break;
2159         }
2160     }
2161     /* de_hw_wakeup :enable auto sr if sr_idle != 0 */
2162     DDR_HW_WAKEUP(0);
2163 }
2164
2165 static __sramfunc void ddr_move_to_Config_state(void)
2166 {
2167     volatile uint32 value;
2168
2169     /* hw_wakeup :disable auto sr */
2170     DDR_HW_WAKEUP(1);
2171         dsb();
2172
2173     while(1)
2174     {
2175         value = pDDR_Reg->STAT.b.ctl_stat;
2176         if(value == Config)
2177         {
2178             break;
2179         }
2180         switch(value)
2181         {
2182             case Low_power:
2183                 pDDR_Reg->SCTL = WAKEUP_STATE;
2184                 dsb();
2185                 while((pDDR_Reg->STAT.b.ctl_stat) != Access);
2186                 while((pPHY_Reg->PGSR & DLDONE) != DLDONE);  //wait DLL lock
2187             case Access:
2188             case Init_mem:
2189                 pDDR_Reg->SCTL = CFG_STATE;
2190                 dsb();
2191                 while((pDDR_Reg->STAT.b.ctl_stat) != Config);
2192                 break;
2193             default:  //Transitional state
2194                 break;
2195         }
2196     }
2197 }
2198
2199 //arg°üÀ¨bank_addrºÍcmd_addr
2200 static void __sramfunc ddr_send_command(uint32 rank, uint32 cmd, uint32 arg)
2201 {
2202     pDDR_Reg->MCMD = (start_cmd | (rank<<20) | arg | cmd);
2203     dsb();
2204     while(pDDR_Reg->MCMD & start_cmd);
2205 }
2206
2207 //¶ÔtypeÀàÐÍµÄDDRµÄ¼¸¸öcs½øÐÐDTT
2208 //0  DTT³É¹¦
2209 //!0 DTTÊ§°Ü
2210 static uint32_t __sramfunc ddr_data_training(void)
2211 {
2212     uint32 value,cs,i,byte=2;
2213
2214     // disable auto refresh
2215     value = pDDR_Reg->TREFI;
2216     pDDR_Reg->TREFI = 0;
2217     dsb();
2218     if(DATA(mem_type) != LPDDR2)
2219     {
2220         // passive window
2221         pPHY_Reg->PGCR |= (1<<1);
2222     }
2223     // clear DTDONE status
2224     pPHY_Reg->PIR |= CLRSR;
2225     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
2226     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (1<<18);  //use cs0 dtt
2227     // trigger DTT
2228     pPHY_Reg->PIR |= INIT | QSTRN | LOCKBYP | ZCALBYP | CLRSR | ICPC;
2229     dsb();
2230     // wait echo byte DTDONE
2231     while((pPHY_Reg->DATX8[0].DXGSR[0] & 1) != 1);
2232     while((pPHY_Reg->DATX8[1].DXGSR[0] & 1) != 1);
2233     if(!(pDDR_Reg->PPCFG & 1))
2234     {
2235         while((pPHY_Reg->DATX8[2].DXGSR[0] & 1) != 1);
2236         while((pPHY_Reg->DATX8[3].DXGSR[0] & 1) != 1);
2237         byte=4;
2238     }
2239     pPHY_Reg->PGCR = (pPHY_Reg->PGCR & (~(0xF<<18))) | (cs<<18);  //restore cs
2240     for(i=0;i<byte;i++)
2241     {
2242         pPHY_Reg->DATX8[i].DXDQSTR = (pPHY_Reg->DATX8[i].DXDQSTR & (~((0x7<<3)|(0x3<<14))))
2243                                       | ((pPHY_Reg->DATX8[i].DXDQSTR & 0x7)<<3)
2244                                       | (((pPHY_Reg->DATX8[i].DXDQSTR>>12) & 0x3)<<14);
2245     }
2246     // send some auto refresh to complement the lost while DTT£¬//²âµ½1¸öCSµÄDTT×î³¤Ê±¼äÊÇ10.7us¡£×î¶à²¹2´ÎË¢ÐÂ
2247     if(cs > 1)
2248     {
2249         ddr_send_command(cs, REF_cmd, 0);
2250         ddr_send_command(cs, REF_cmd, 0);
2251         ddr_send_command(cs, REF_cmd, 0);
2252         ddr_send_command(cs, REF_cmd, 0);
2253     }
2254     else
2255     {
2256         ddr_send_command(cs, REF_cmd, 0);
2257         ddr_send_command(cs, REF_cmd, 0);
2258     }
2259     if(DATA(mem_type) != LPDDR2)
2260     {
2261         // active window
2262         pPHY_Reg->PGCR &= ~(1<<1);
2263     }
2264     // resume auto refresh
2265     pDDR_Reg->TREFI = value;
2266
2267     if(pPHY_Reg->PGSR & DTERR)
2268     {
2269         return (-1);
2270     }
2271     else
2272     {
2273         return 0;
2274     }
2275 }
2276
2277 static void __sramfunc ddr_set_dll_bypass(uint32 freq)
2278 {
2279     if(freq<=150)
2280     {
2281         pPHY_Reg->DLLGCR &= ~(1<<23);
2282         pPHY_Reg->ACDLLCR |= 0x80000000;
2283         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2284         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2285         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2286         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2287         pPHY_Reg->PIR |= DLLBYP;
2288     }
2289     else if(freq<=250)
2290     {
2291         pPHY_Reg->DLLGCR |= (1<<23);
2292         pPHY_Reg->ACDLLCR |= 0x80000000;
2293         pPHY_Reg->DATX8[0].DXDLLCR |= 0x80000000;
2294         pPHY_Reg->DATX8[1].DXDLLCR |= 0x80000000;
2295         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;
2296         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
2297         pPHY_Reg->PIR |= DLLBYP;
2298     }
2299     else
2300     {
2301         pPHY_Reg->DLLGCR &= ~(1<<23);
2302         pPHY_Reg->ACDLLCR &= ~0x80000000;
2303         pPHY_Reg->DATX8[0].DXDLLCR &= ~0x80000000;
2304         pPHY_Reg->DATX8[1].DXDLLCR &= ~0x80000000;
2305         if(!(pDDR_Reg->PPCFG & 1))
2306         {
2307             pPHY_Reg->DATX8[2].DXDLLCR &= ~0x80000000;
2308             pPHY_Reg->DATX8[3].DXDLLCR &= ~0x80000000;
2309         }
2310         pPHY_Reg->PIR &= ~DLLBYP;
2311     }
2312 }
2313
2314 static noinline uint32_t ddr_get_parameter(uint32_t nMHz)
2315 {
2316     uint32_t tmp;
2317     uint32_t ret = 0;
2318     uint32_t al;
2319     uint32_t bl,bl_tmp;
2320     uint32_t cl;
2321     uint32_t cwl;
2322     PCTL_TIMING_T *p_pctl_timing=&(p_ddr_reg->pctl.pctl_timing);
2323     PHY_TIMING_T  *p_publ_timing=&(p_ddr_reg->publ.phy_timing);
2324     NOC_TIMING_T  *p_noc_timing=&(p_ddr_reg->noc_timing);
2325
2326     p_pctl_timing->togcnt1u = nMHz;
2327     p_pctl_timing->togcnt100n = nMHz/10;
2328     p_pctl_timing->tinit = 200;
2329     p_pctl_timing->trsth = 500;
2330
2331     if(*p_mem_type == DDR3)
2332     {
2333         if(ddr_speed_bin > DDR3_DEFAULT){
2334             ret = -1;
2335             goto out;
2336         }
2337
2338         #define DDR3_tREFI_7_8_us    (78)  //unit 100ns
2339         #define DDR3_tMRD            (4)   //tCK
2340         #define DDR3_tRFC_512Mb      (90)  //ns
2341         #define DDR3_tRFC_1Gb        (110) //ns
2342         #define DDR3_tRFC_2Gb        (160) //ns
2343         #define DDR3_tRFC_4Gb        (300) //ns
2344         #define DDR3_tRFC_8Gb        (350) //ns
2345         #define DDR3_tRTW            (2)   //register min valid value
2346         #define DDR3_tRAS            (37)  //ns
2347         #define DDR3_tRRD            (10)  //ns
2348         #define DDR3_tRTP            (7)   //ns
2349         #define DDR3_tWR             (15)  //ns
2350         #define DDR3_tWTR            (7)   //ns
2351         #define DDR3_tXP             (7)   //ns
2352         #define DDR3_tXPDLL          (24)  //ns
2353         #define DDR3_tZQCS           (80)  //ns
2354         #define DDR3_tZQCSI          (0)   //ns
2355         #define DDR3_tDQS            (1)   //tCK
2356         #define DDR3_tCKSRE          (10)  //ns
2357         #define DDR3_tCKE_400MHz     (7)   //ns
2358         #define DDR3_tCKE_533MHz     (6)   //ns
2359         #define DDR3_tMOD            (15)  //ns
2360         #define DDR3_tRSTL           (100) //ns
2361         #define DDR3_tZQCL           (320) //ns
2362         #define DDR3_tDLLK           (512) //tCK
2363
2364         al = 0;
2365         bl = 8;
2366         if(nMHz <= 330)
2367         {
2368             tmp = 0;
2369         }
2370         else if(nMHz<=400)
2371         {
2372             tmp = 1;
2373         }
2374         else if(nMHz<=533)
2375         {
2376             tmp = 2;
2377         }
2378         else if(nMHz<=666)
2379         {
2380             tmp = 3;
2381         }
2382         else if(nMHz<=800)
2383         {
2384             tmp = 4;
2385         }
2386         else if(nMHz<=933)
2387         {
2388             tmp = 5;
2389         }
2390         else
2391         {
2392             tmp = 6;
2393         }
2394
2395         if(nMHz < DDR3_DDR2_DLL_DISABLE_FREQ)       //when dll bypss cl = cwl = 6;
2396         {
2397             cl = 6;
2398             cwl = 6;
2399         }
2400         else
2401         {
2402             cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4)&0xf;
2403             cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
2404         }
2405         if(cl == 0)
2406             ret = -4;
2407         if(nMHz <= DDR3_DDR2_ODT_DISABLE_FREQ)
2408         {
2409             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_DIS;
2410         }
2411         else
2412         {
2413             p_publ_timing->mr[1] = DDR3_DS_40 | DDR3_Rtt_Nom_120;
2414         }
2415         p_publ_timing->mr[2] = DDR3_MR2_CWL(cwl) /* | DDR3_Rtt_WR_60 */;
2416         p_publ_timing->mr[3] = 0;
2417         /**************************************************
2418          * PCTL Timing
2419          **************************************************/
2420         /*
2421          * tREFI, average periodic refresh interval, 7.8us
2422          */
2423         p_pctl_timing->trefi = DDR3_tREFI_7_8_us;
2424         /*
2425          * tMRD, 4 tCK
2426          */
2427         p_pctl_timing->tmrd = DDR3_tMRD & 0x7;
2428         p_publ_timing->dtpr0.b.tMRD = DDR3_tMRD-4;
2429         /*
2430          * tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb)
2431          */
2432         if(ddr_capability_per_die <= 0x4000000)         // 512Mb 90ns
2433         {
2434             tmp = DDR3_tRFC_512Mb;
2435         }
2436         else if(ddr_capability_per_die <= 0x8000000)    // 1Gb 110ns
2437         {
2438             tmp = DDR3_tRFC_1Gb;
2439         }
2440         else if(ddr_capability_per_die <= 0x10000000)   // 2Gb 160ns
2441         {
2442             tmp = DDR3_tRFC_2Gb;
2443         }
2444         else if(ddr_capability_per_die <= 0x20000000)   // 4Gb 300ns
2445         {
2446             tmp = DDR3_tRFC_4Gb;
2447         }
2448         else    // 8Gb  350ns
2449         {
2450             tmp = DDR3_tRFC_8Gb;
2451         }
2452         p_pctl_timing->trfc = (tmp*nMHz+999)/1000;
2453         p_publ_timing->dtpr1.b.tRFC = ((tmp*nMHz+999)/1000)&0xFF;
2454         /*
2455          * tXSR, =tDLLK=512 tCK
2456          */
2457         p_pctl_timing->texsr = DDR3_tDLLK;
2458         p_publ_timing->dtpr2.b.tXS = DDR3_tDLLK;
2459         /*
2460          * tRP=CL
2461          */
2462         p_pctl_timing->trp = cl;
2463         p_publ_timing->dtpr0.b.tRP = cl;
2464         /*
2465          * WrToMiss=WL*tCK + tWR + tRP + tRCD
2466          */
2467         p_noc_timing->b.WrToMiss = ((cwl+((DDR3_tWR*nMHz+999)/1000)+cl+cl)&0x3F);
2468         /*
2469          * tRC=tRAS+tRP
2470          */
2471         p_pctl_timing->trc = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2472         p_noc_timing->b.ActToAct = ((((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0x3F);
2473         p_publ_timing->dtpr0.b.tRC = (((ddr3_tRC_tFAW[ddr_speed_bin]>>8)*nMHz+999)/1000)&0xF;
2474
2475         p_pctl_timing->trtw = (cl+2-cwl);//DDR3_tRTW;
2476         p_publ_timing->dtpr1.b.tRTW = 0;
2477         p_noc_timing->b.RdToWr = ((cl+2-cwl)&0x1F);
2478         p_pctl_timing->tal = al;
2479         p_pctl_timing->tcl = cl;
2480         p_pctl_timing->tcwl = cwl;
2481         /*
2482          * tRAS, 37.5ns(400MHz)     37.5ns(533MHz)
2483          */
2484         p_pctl_timing->tras = (((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x3F);
2485         p_publ_timing->dtpr0.b.tRAS = ((DDR3_tRAS*nMHz+(nMHz>>1)+999)/1000)&0x1F;
2486         /*
2487          * tRCD=CL
2488          */
2489         p_pctl_timing->trcd = cl;
2490         p_publ_timing->dtpr0.b.tRCD = cl;
2491         /*
2492          * tRRD = max(4nCK, 7.5ns), DDR3-1066(1K), DDR3-1333(2K), DDR3-1600(2K)
2493          *        max(4nCK, 10ns), DDR3-800(1K,2K), DDR3-1066(2K)
2494          *        max(4nCK, 6ns), DDR3-1333(1K), DDR3-1600(1K)
2495          *
2496          */
2497         tmp = ((DDR3_tRRD*nMHz+999)/1000);
2498         if(tmp < 4)
2499         {
2500             tmp = 4;
2501         }
2502         p_pctl_timing->trrd = (tmp&0xF);
2503         p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
2504         /*
2505          * tRTP, max(4 tCK,7.5ns)
2506          */
2507         tmp = ((DDR3_tRTP*nMHz+(nMHz>>1)+999)/1000);
2508         if(tmp < 4)
2509         {
2510             tmp = 4;
2511         }
2512         p_pctl_timing->trtp = tmp&0xF;
2513         p_publ_timing->dtpr0.b.tRTP = tmp;
2514         /*
2515          * RdToMiss=tRTP+tRP + tRCD - (BL/2 * tCK)
2516          */
2517         p_noc_timing->b.RdToMiss = ((tmp+cl+cl-(bl>>1))&0x3F);
2518         /*
2519          * tWR, 15ns
2520          */
2521         tmp = ((DDR3_tWR*nMHz+999)/1000);
2522         p_pctl_timing->twr = tmp&0x1F;
2523         if(tmp<9)
2524             tmp = tmp - 4;
2525         else
2526             tmp = tmp>>1;
2527         bl_tmp = (bl == 8) ? DDR3_BL8 : DDR3_BC4;
2528         p_publ_timing->mr[0] = bl_tmp | DDR3_CL(cl) | DDR3_WR(tmp);
2529
2530         /*
2531          * tWTR, max(4 tCK,7.5ns)
2532          */
2533         tmp = ((DDR3_tWTR*nMHz+(nMHz>>1)+999)/1000);
2534         if(tmp < 4)
2535         {
2536             tmp = 4;
2537         }
2538         p_pctl_timing->twtr = tmp&0xF;
2539         p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2540         p_noc_timing->b.WrToRd = ((tmp+cwl)&0x1F);
2541         /*
2542          * tXP, max(3 tCK, 7.5ns)(<933MHz)
2543          */
2544         tmp = ((DDR3_tXP*nMHz+(nMHz>>1)+999)/1000);
2545         if(tmp < 3)
2546         {
2547             tmp = 3;
2548         }
2549         p_pctl_timing->txp = tmp&0x7;
2550         /*
2551          * tXPDLL, max(10 tCK,24ns)
2552          */
2553         tmp = ((DDR3_tXPDLL*nMHz+999)/1000);
2554         if(tmp < 10)
2555         {
2556             tmp = 10;
2557         }
2558         p_pctl_timing->txpdll = tmp & 0x3F;
2559         p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
2560         /*
2561          * tZQCS, max(64 tCK, 80ns)
2562          */
2563         tmp = ((DDR3_tZQCS*nMHz+999)/1000);
2564         if(tmp < 64)
2565         {
2566             tmp = 64;
2567         }
2568         p_pctl_timing->tzqcs = tmp&0x7F;
2569         /*
2570          * tZQCSI,
2571          */
2572         p_pctl_timing->tzqcsi = DDR3_tZQCSI;
2573         /*
2574          * tDQS,
2575          */
2576         p_pctl_timing->tdqs = DDR3_tDQS;
2577         /*
2578          * tCKSRE, max(5 tCK, 10ns)
2579          */
2580         tmp = ((DDR3_tCKSRE*nMHz+999)/1000);
2581         if(tmp < 5)
2582         {
2583             tmp = 5;
2584         }
2585         p_pctl_timing->tcksre = tmp & 0x1F;
2586         /*
2587          * tCKSRX, max(5 tCK, 10ns)
2588          */
2589         p_pctl_timing->tcksrx = tmp & 0x1F;
2590         /*
2591          * tCKE, max(3 tCK,7.5ns)(400MHz) max(3 tCK,5.625ns)(533MHz)
2592          */
2593         if(nMHz>=533)
2594         {
2595             tmp = ((DDR3_tCKE_533MHz*nMHz+999)/1000);
2596         }
2597         else
2598         {
2599             tmp = ((DDR3_tCKE_400MHz*nMHz+(nMHz>>1)+999)/1000);
2600         }
2601         if(tmp < 3)
2602         {
2603             tmp = 3;
2604         }
2605         p_pctl_timing->tcke = tmp & 0x7;
2606         p_publ_timing->dtpr2.b.tCKE = tmp;
2607         /*
2608          * tCKESR, =tCKE + 1tCK
2609          */
2610         p_pctl_timing->tckesr = (tmp+1)&0xF;
2611         /*
2612          * tMOD, max(12 tCK,15ns)
2613          */
2614         tmp = ((DDR3_tMOD*nMHz+999)/1000);
2615         if(tmp < 12)
2616         {
2617             tmp = 12;
2618         }
2619         p_pctl_timing->tmod = tmp&0x1F;
2620         p_publ_timing->dtpr1.b.tMOD = tmp;
2621         /*
2622          * tRSTL, 100ns
2623          */
2624         p_pctl_timing->trstl = ((DDR3_tRSTL*nMHz+999)/1000)&0x7F;
2625         /*
2626          * tZQCL, max(256 tCK, 320ns)
2627          */
2628         tmp = ((DDR3_tZQCL*nMHz+999)/1000);
2629         if(tmp < 256)
2630         {
2631             tmp = 256;
2632         }
2633         p_pctl_timing->tzqcl = tmp&0x3FF;
2634         /*
2635          * tMRR, 0 tCK
2636          */
2637         p_pctl_timing->tmrr = 0;
2638         /*
2639          * tDPD, 0
2640          */
2641         p_pctl_timing->tdpd = 0;
2642
2643         /**************************************************
2644          * PHY Timing
2645          **************************************************/
2646         /*
2647          * tCCD, BL/2 for DDR2 and 4 for DDR3
2648          */
2649         p_publ_timing->dtpr0.b.tCCD = 0;
2650         /*
2651          * tDQSCKmax,5.5ns
2652          */
2653         p_publ_timing->dtpr1.b.tDQSCKmax = 0;
2654         /*
2655          * tRTODT, 0:ODT may be turned on immediately after read post-amble
2656          *         1:ODT may not be turned on until one clock after the read post-amble
2657          */
2658         p_publ_timing->dtpr1.b.tRTODT = 1;
2659         /*
2660          * tFAW,40ns(400MHz 1KB page) 37.5ns(533MHz 1KB page) 50ns(400MHz 2KB page)   50ns(533MHz 2KB page)
2661          */
2662         p_publ_timing->dtpr1.b.tFAW = (((ddr3_tRC_tFAW[ddr_speed_bin]&0x0ff)*nMHz+999)/1000)&0x7F;
2663         /*
2664          * tAOND_tAOFD
2665          */
2666         p_publ_timing->dtpr1.b.tAOND = 0;
2667         /*
2668          * tDLLK,512 tCK
2669          */
2670         p_publ_timing->dtpr2.b.tDLLK = DDR3_tDLLK;
2671         /**************************************************
2672          * NOC Timing
2673          **************************************************/
2674         p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
2675     }
2676     else if(*p_mem_type == LPDDR2)
2677     {
2678         #define LPDDR2_tREFI_3_9_us    (38)  //unit 100ns
2679         #define LPDDR2_tREFI_7_8_us    (78)  //unit 100ns
2680         #define LPDDR2_tMRD            (5)   //tCK
2681         #define LPDDR2_tRFC_8Gb        (210)  //ns
2682         #define LPDDR2_tRFC_4Gb        (130)  //ns
2683         #define LPDDR2_tRP_4_BANK               (24)  //ns
2684         #define LPDDR2_tRPab_SUB_tRPpb_4_BANK   (0)
2685         #define LPDDR2_tRP_8_BANK               (27)  //ns
2686         #define LPDDR2_tRPab_SUB_tRPpb_8_BANK   (3)
2687         #define LPDDR2_tRTW          (1)   //tCK register min valid value
2688         #define LPDDR2_tRAS          (42)  //ns
2689         #define LPDDR2_tRCD          (24)  //ns
2690         #define LPDDR2_tRRD          (10)  //ns
2691         #define LPDDR2_tRTP          (7)   //ns
2692         #define LPDDR2_tWR           (15)  //ns
2693         #define LPDDR2_tWTR_GREAT_200MHz         (7)  //ns
2694         #define LPDDR2_tWTR_LITTLE_200MHz        (10) //ns
2695         #define LPDDR2_tXP           (7)  //ns
2696         #define LPDDR2_tXPDLL        (0)
2697         #define LPDDR2_tZQCS         (90) //ns
2698         #define LPDDR2_tZQCSI        (0)
2699         #define LPDDR2_tDQS          (1)
2700         #define LPDDR2_tCKSRE        (1)  //tCK
2701         #define LPDDR2_tCKSRX        (2)  //tCK
2702         #define LPDDR2_tCKE          (3)  //tCK
2703         #define LPDDR2_tMOD          (0)
2704         #define LPDDR2_tRSTL         (0)
2705         #define LPDDR2_tZQCL         (360)  //ns
2706         #define LPDDR2_tMRR          (2)    //tCK
2707         #define LPDDR2_tCKESR        (15)   //ns
2708         #define LPDDR2_tDPD_US       (500)
2709         #define LPDDR2_tFAW_GREAT_200MHz    (50)  //ns
2710         #define LPDDR2_tFAW_LITTLE_200MHz   (60)  //ns
2711         #define LPDDR2_tDLLK         (2)  //tCK
2712         #define LPDDR2_tDQSCK_MAX    (3)  //tCK
2713         #define LPDDR2_tDQSCK_MIN    (0)  //tCK
2714         #define LPDDR2_tDQSS         (1)  //tCK
2715
2716         uint32 trp_tmp;
2717         uint32 trcd_tmp;
2718         uint32 tras_tmp;
2719         uint32 trtp_tmp;
2720         uint32 twr_tmp;
2721
2722         al = 0;
2723         if(nMHz>=200)
2724         {
2725             bl = 4;  //you can change burst here
2726         }
2727         else
2728         {
2729             bl = 8;  // freq < 200MHz, BL fixed 8
2730         }
2731         /*     1066 933 800 667 533 400 333
2732          * RL,   8   7   6   5   4   3   3
2733          * WL,   4   4   3   2   2   1   1
2734          */
2735         if(nMHz<=200)
2736         {
2737             cl = 3;
2738             cwl = 1;
2739             p_publ_timing->mr[2] = LPDDR2_RL3_WL1;
2740         }
2741         else if(nMHz<=266)
2742         {
2743             cl = 4;
2744             cwl = 2;
2745             p_publ_timing->mr[2] = LPDDR2_RL4_WL2;
2746         }
2747         else if(nMHz<=333)
2748         {
2749             cl = 5;
2750             cwl = 2;
2751             p_publ_timing->mr[2] = LPDDR2_RL5_WL2;
2752         }
2753         else if(nMHz<=400)
2754         {
2755             cl = 6;
2756             cwl = 3;
2757             p_publ_timing->mr[2] = LPDDR2_RL6_WL3;
2758         }
2759         else if(nMHz<=466)
2760         {
2761             cl = 7;
2762             cwl = 4;
2763             p_publ_timing->mr[2] = LPDDR2_RL7_WL4;
2764         }
2765         else //(nMHz<=1066)
2766         {
2767             cl = 8;
2768             cwl = 4;
2769             p_publ_timing->mr[2] = LPDDR2_RL8_WL4;
2770         }
2771         p_publ_timing->mr[3] = LPDDR2_DS_34;
2772         p_publ_timing->mr[0] = 0;
2773         /**************************************************
2774          * PCTL Timing
2775          **************************************************/
2776         /*
2777          * tREFI, average periodic refresh interval, 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
2778          */
2779         if(ddr_capability_per_die >= 0x10000000)   // 2Gb
2780         {
2781             p_pctl_timing->trefi = LPDDR2_tREFI_3_9_us;
2782         }
2783         else
2784         {
2785             p_pctl_timing->trefi = LPDDR2_tREFI_7_8_us;
2786         }
2787
2788         /*
2789          * tMRD, (=tMRW), 5 tCK
2790          */
2791         p_pctl_timing->tmrd = LPDDR2_tMRD & 0x7;
2792         p_publ_timing->dtpr0.b.tMRD = 3;
2793         /*
2794          * tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb)
2795          */
2796         if(ddr_capability_per_die >= 0x40000000)   // 8Gb
2797         {
2798             p_pctl_timing->trfc = (LPDDR2_tRFC_8Gb*nMHz+999)/1000;
2799             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_8Gb*nMHz+999)/1000)&0xFF;
2800             /*
2801              * tXSR, max(2tCK,tRFC+10ns)
2802              */
2803             tmp=(((LPDDR2_tRFC_8Gb+10)*nMHz+999)/1000);
2804         }
2805         else
2806         {
2807             p_pctl_timing->trfc = (LPDDR2_tRFC_4Gb*nMHz+999)/1000;
2808             p_publ_timing->dtpr1.b.tRFC = ((LPDDR2_tRFC_4Gb*nMHz+999)/1000)&0xFF;
2809             tmp=(((LPDDR2_tRFC_4Gb+10)*nMHz+999)/1000);
2810         }
2811         if(tmp<2)
2812         {
2813             tmp=2;
2814         }
2815         p_pctl_timing->texsr = tmp&0x3FF;
2816         p_publ_timing->dtpr2.b.tXS = tmp&0x3FF;
2817
2818         /*
2819          * tRP, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
2820          */
2821         if(pPHY_Reg->DCR.b.DDR8BNK)
2822         {
2823             trp_tmp = ((LPDDR2_tRP_8_BANK*nMHz+999)/1000);
2824             if(trp_tmp<3)
2825             {
2826                 trp_tmp=3;
2827             }
2828             p_pctl_timing->trp = ((((LPDDR2_tRPab_SUB_tRPpb_8_BANK*nMHz+999)/1000) & 0x3)<<16) | (trp_tmp&0xF);
2829         }
2830         else
2831         {
2832             trp_tmp = ((LPDDR2_tRP_4_BANK*nMHz+999)/1000);
2833             if(trp_tmp<3)
2834             {
2835                 trp_tmp=3;
2836             }
2837             p_pctl_timing->trp = (LPDDR2_tRPab_SUB_tRPpb_4_BANK<<16) | (trp_tmp&0xF);
2838         }
2839         p_publ_timing->dtpr0.b.tRP = trp_tmp;
2840         /*
2841          * tRAS, max(3tCK,42ns)
2842          */
2843         tras_tmp=((LPDDR2_tRAS*nMHz+999)/1000);
2844         if(tras_tmp<3)
2845         {
2846             tras_tmp=3;
2847         }
2848         p_pctl_timing->tras = (tras_tmp&0x3F);
2849         p_publ_timing->dtpr0.b.tRAS = tras_tmp&0x1F;
2850
2851         /*
2852          * tRCD, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow))
2853          */
2854         trcd_tmp = ((LPDDR2_tRCD*nMHz+999)/1000);
2855         if(trcd_tmp<3)
2856         {
2857             trcd_tmp=3;
2858         }
2859         p_pctl_timing->trcd = (trcd_tmp&0xF);
2860         p_publ_timing->dtpr0.b.tRCD = trcd_tmp&0xF;
2861
2862         /*
2863          * tRTP, max(2tCK, 7.5ns)
2864          */
2865         trtp_tmp = ((LPDDR2_tRTP*nMHz+(nMHz>>1)+999)/1000);
2866         if(trtp_tmp<2)
2867         {
2868             trtp_tmp = 2;
2869         }
2870         p_pctl_timing->trtp = trtp_tmp&0xF;
2871         p_publ_timing->dtpr0.b.tRTP = trtp_tmp;
2872
2873         /*
2874          * tWR, max(3tCK,15ns)
2875          */
2876         twr_tmp=((LPDDR2_tWR*nMHz+999)/1000);
2877         if(twr_tmp<3)
2878         {
2879             twr_tmp=3;
2880         }
2881         p_pctl_timing->twr = twr_tmp&0x1F;
2882         bl_tmp = (bl == 16) ? LPDDR2_BL16 : ((bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
2883         p_publ_timing->mr[1] = bl_tmp | LPDDR2_nWR(twr_tmp);
2884
2885         /*
2886          * WrToMiss=WL*tCK + tDQSS + tWR + tRP + tRCD
2887          */
2888         p_noc_timing->b.WrToMiss = ((cwl+LPDDR2_tDQSS+twr_tmp+trp_tmp+trcd_tmp)&0x3F);
2889         /*
2890          * RdToMiss=tRTP + tRP + tRCD - (BL/2 * tCK)
2891          */
2892         p_noc_timing->b.RdToMiss = ((trtp_tmp+trp_tmp+trcd_tmp-(bl>>1))&0x3F);
2893         /*
2894          * tRC=tRAS+tRP
2895          */
2896         p_pctl_timing->trc = ((tras_tmp+trp_tmp)&0x3F);
2897         p_noc_timing->b.ActToAct = ((tras_tmp+trp_tmp)&0x3F);
2898         p_publ_timing->dtpr0.b.tRC = (tras_tmp+trp_tmp)&0xF;
2899
2900         /*
2901          * RdToWr=RL+tDQSCK-WL
2902          */
2903         p_pctl_timing->trtw = (cl+LPDDR2_tDQSCK_MAX+(bl/2)+1-cwl);//LPDDR2_tRTW;
2904         p_publ_timing->dtpr1.b.tRTW = 0;
2905         p_noc_timing->b.RdToWr = ((cl+LPDDR2_tDQSCK_MAX+1-cwl)&0x1F);
2906         p_pctl_timing->tal = al;
2907         p_pctl_timing->tcl = cl;
2908         p_pctl_timing->tcwl = cwl;
2909         /*
2910          * tRRD, max(2tCK,10ns)
2911          */
2912         tmp=((LPDDR2_tRRD*nMHz+999)/1000);
2913         if(tmp<2)
2914         {
2915             tmp=2;
2916         }
2917         p_pctl_timing->trrd = (tmp&0xF);
2918         p_publ_timing->dtpr0.b.tRRD = tmp&0xF;
2919         /*
2920          * tWTR, max(2tCK, 7.5ns(533-266MHz)  10ns(200-166MHz))
2921          */
2922         if(nMHz > 200)
2923         {
2924             tmp=((LPDDR2_tWTR_GREAT_200MHz*nMHz+(nMHz>>1)+999)/1000);
2925         }
2926         else
2927         {
2928             tmp=((LPDDR2_tWTR_LITTLE_200MHz*nMHz+999)/1000);
2929         }
2930         if(tmp<2)
2931         {
2932             tmp=2;
2933         }
2934         p_pctl_timing->twtr = tmp&0xF;
2935         p_publ_timing->dtpr0.b.tWTR = tmp&0x7;
2936         /*
2937          * WrToRd=WL+tDQSS+tWTR
2938          */
2939         p_noc_timing->b.WrToRd = ((cwl+LPDDR2_tDQSS+tmp)&0x1F);
2940         /*
2941          * tXP, max(2tCK,7.5ns)
2942          */
2943         tmp=((LPDDR2_tXP*nMHz+(nMHz>>1)+999)/1000);
2944         if(tmp<2)
2945         {
2946             tmp=2;
2947         }
2948         p_pctl_timing->txp = tmp&0x7;
2949         p_publ_timing->dtpr2.b.tXP = tmp&0x1F;
2950         /*
2951          * tXPDLL, 0ns
2952          */
2953         p_pctl_timing->txpdll = LPDDR2_tXPDLL;
2954         /*
2955          * tZQCS, 90ns
2956          */
2957         p_pctl_timing->tzqcs = ((LPDDR2_tZQCS*nMHz+999)/1000)&0x7F;
2958         /*
2959          * tZQCSI,
2960          */
2961         if(pDDR_Reg->MCFG &= lpddr2_s4)
2962         {
2963             p_pctl_timing->tzqcsi = LPDDR2_tZQCSI;
2964         }
2965         else
2966         {
2967             p_pctl_timing->tzqcsi = 0;
2968         }
2969         /*
2970          * tDQS,
2971          */
2972         p_pctl_timing->tdqs = LPDDR2_tDQS;
2973         /*
2974          * tCKSRE, 1 tCK
2975          */
2976         p_pctl_timing->tcksre = LPDDR2_tCKSRE;
2977         /*
2978          * tCKSRX, 2 tCK
2979          */
2980         p_pctl_timing->tcksrx = LPDDR2_tCKSRX;
2981         /*
2982          * tCKE, 3 tCK
2983          */
2984         p_pctl_timing->tcke = LPDDR2_tCKE;
2985         p_publ_timing->dtpr2.b.tCKE = LPDDR2_tCKE;
2986         /*
2987          * tMOD, 0 tCK
2988          */
2989         p_pctl_timing->tmod = LPDDR2_tMOD;
2990         p_publ_timing->dtpr1.b.tMOD = LPDDR2_tMOD;
2991         /*
2992          * tRSTL, 0 tCK
2993          */
2994         p_pctl_timing->trstl = LPDDR2_tRSTL;
2995         /*
2996          * tZQCL, 360ns
2997          */
2998         p_pctl_timing->tzqcl = ((LPDDR2_tZQCL*nMHz+999)/1000)&0x3FF;
2999         /*
3000          * tMRR, 2 tCK
3001          */
3002         p_pctl_timing->tmrr = LPDDR2_tMRR;
3003         /*
3004          * tCKESR, max(3tCK,15ns)
3005          */
3006         tmp = ((LPDDR2_tCKESR*nMHz+999)/1000);
3007         if(tmp < 3)
3008         {
3009             tmp = 3;
3010         }
3011         p_pctl_timing->tckesr = tmp&0xF;
3012         /*
3013          * tDPD, 500us
3014          */
3015         p_pctl_timing->tdpd = LPDDR2_tDPD_US;
3016
3017         /**************************************************
3018          * PHY Timing
3019          **************************************************/
3020         /*
3021          * tCCD, BL/2 for DDR2 and 4 for DDR3
3022          */
3023         p_publ_timing->dtpr0.b.tCCD = 0;
3024         /*
3025          * tDQSCKmax,5.5ns
3026          */
3027         p_publ_timing->dtpr1.b.tDQSCKmax = LPDDR2_tDQSCK_MAX;
3028         /*
3029          * tDQSCKmin,2.5ns
3030          */
3031         p_publ_timing->dtpr1.b.tDQSCK = LPDDR2_tDQSCK_MIN;
3032         /*
3033          * tRTODT, 0:ODT may be turned on immediately after read post-amble
3034          *         1:ODT may not be turned on until one clock after the read post-amble
3035          */
3036         p_publ_timing->dtpr1.b.tRTODT = 1;
3037         /*
3038          * tFAW,max(8tCK, 50ns(200-533MHz)  60ns(166MHz))
3039          */
3040         if(nMHz>=200)
3041         {
3042             tmp=((LPDDR2_tFAW_GREAT_200MHz*nMHz+999)/1000);
3043         }
3044         else
3045         {
3046             tmp=((LPDDR2_tFAW_LITTLE_200MHz*nMHz+999)/1000);
3047         }
3048         if(tmp<8)
3049         {
3050             tmp=8;
3051         }
3052         p_publ_timing->dtpr1.b.tFAW = tmp&0x7F;
3053         /*
3054          * tAOND_tAOFD
3055          */
3056         p_publ_timing->dtpr1.b.tAOND = 0;
3057         /*
3058          * tDLLK,0
3059          */
3060         p_publ_timing->dtpr2.b.tDLLK = LPDDR2_tDLLK;
3061         /**************************************************
3062          * NOC Timing
3063          **************************************************/
3064         p_noc_timing->b.BurstLen = ((bl>>1)&0x7);
3065     }
3066
3067 out:
3068     return ret;
3069 }
3070
3071 static uint32_t __sramfunc ddr_update_timing(void)
3072 {
3073     uint32_t i,bl_tmp=0;
3074     PCTL_TIMING_T *p_pctl_timing=&(DATA(ddr_reg).pctl.pctl_timing);
3075     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3076     NOC_TIMING_T  *p_noc_timing=&(DATA(ddr_reg).noc_timing);
3077
3078     ddr_copy((uint32_t *)&(pDDR_Reg->TOGCNT1U), (uint32_t*)&(p_pctl_timing->togcnt1u), 34);
3079     ddr_copy((uint32_t *)&(pPHY_Reg->DTPR[0]), (uint32_t*)&(p_publ_timing->dtpr0), 3);
3080     *(volatile uint32_t *)SysSrv_DdrTiming = p_noc_timing->d32;
3081     // Update PCTL BL
3082     if(DATA(mem_type) == DDR3)
3083     {
3084         bl_tmp = ((p_publ_timing->mr[0] & 0x3) == DDR3_BL8) ? ddr2_ddr3_bl_8 : ddr2_ddr3_bl_4;
3085         pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~(0x1|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_slow|pd_type(1);
3086         if((DATA(ddr_freq) <= DDR3_DDR2_DLL_DISABLE_FREQ) && (true == DATA(ddr_soc_is_rk3188_plus)))
3087         {
3088             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-3;
3089         }
3090         else
3091         {
3092             pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-2;
3093         }
3094         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL-1;
3095     }
3096     else if(DATA(mem_type) == LPDDR2)
3097     {
3098         if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL8)
3099         {
3100             bl_tmp = mddr_lpddr2_bl_8;
3101         }
3102         else if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL4)
3103         {
3104             bl_tmp = mddr_lpddr2_bl_4;
3105         }
3106         else //if(((p_publ_timing->mr[1]) & 0x7) == LPDDR2_BL16)
3107         {
3108             bl_tmp = mddr_lpddr2_bl_16;
3109         }
3110         if(DATA(ddr_freq)>=200)
3111         {
3112             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | bl_tmp | tfaw_cfg(5)|pd_exit_fast|pd_type(1);
3113         }
3114         else
3115         {
3116             pDDR_Reg->MCFG = (pDDR_Reg->MCFG & (~((0x3<<20)|(0x3<<18)|(0x1<<17)|(0x1<<16)))) | mddr_lpddr2_bl_8 | tfaw_cfg(6)|pd_exit_fast|pd_type(1);
3117         }
3118         i = ((pPHY_Reg->DTPR[1] >> 27) & 0x7) - ((pPHY_Reg->DTPR[1] >> 24) & 0x7);
3119         pPHY_Reg->DSGCR = (pPHY_Reg->DSGCR & (~(0x3F<<5))) | (i<<5) | (i<<8);  //tDQSCKmax-tDQSCK
3120         pDDR_Reg->DFITRDDATAEN   = pDDR_Reg->TCL-1;
3121         pDDR_Reg->DFITPHYWRLAT   = pDDR_Reg->TCWL;
3122     }
3123
3124     return 0;
3125 }
3126
3127 static uint32_t __sramfunc ddr_update_mr(void)
3128 {
3129     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3130     uint32_t cs,dll_off;
3131
3132     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3133     dll_off = (pPHY_Reg->MR[1] & DDR3_DLL_DISABLE) ? 1:0;
3134     ddr_copy((uint32_t *)&(pPHY_Reg->MR[0]), (uint32_t*)&(p_publ_timing->mr[0]), 4);
3135     if((DATA(mem_type) == DDR3) || (DATA(mem_type) == DDR2))
3136     {
3137         if(DATA(ddr_freq)>DDR3_DDR2_DLL_DISABLE_FREQ)
3138         {
3139             if(dll_off)  // off -> on
3140             {
3141                 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));  //DLL enable
3142                 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr(((p_publ_timing->mr[0]))| DDR3_DLL_RESET));  //DLL reset
3143                 ddr_delayus(2);  //at least 200 DDR cycle
3144                 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3145             }
3146             else // on -> on
3147             {
3148                 ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[1])));
3149                 ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3150             }
3151         }
3152         else
3153         {
3154             pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3155             ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));  //DLL disable
3156             ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3157         }
3158         ddr_send_command(cs, MRS_cmd, bank_addr(0x2) | cmd_addr((p_publ_timing->mr[2])));
3159     }
3160     else if(DATA(mem_type) == LPDDR2)
3161     {
3162         ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x1) | lpddr2_op((p_publ_timing->mr[1])));
3163         ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x2) | lpddr2_op((p_publ_timing->mr[2])));
3164         ddr_send_command(cs, MRS_cmd, lpddr2_ma(0x3) | lpddr2_op((p_publ_timing->mr[3])));
3165     }
3166     else //mDDR
3167     {
3168         ddr_send_command(cs, MRS_cmd, bank_addr(0x0) | cmd_addr((p_publ_timing->mr[0])));
3169         ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr((p_publ_timing->mr[2]))); //mr[2] is mDDR MR1
3170     }
3171     return 0;
3172 }
3173
3174 static void __sramfunc ddr_update_odt(void)
3175 {
3176     uint32_t cs,tmp;
3177
3178     //adjust DRV and ODT
3179     if((DATA(mem_type) == DDR3) || (DATA(mem_type) == DDR2))
3180     {
3181         if(DATA(ddr_freq) <= DDR3_DDR2_ODT_DISABLE_FREQ)
3182         {
3183             pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3184             pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3185             if(!(pDDR_Reg->PPCFG & 1))
3186             {
3187                 pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3188                 pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3189             }
3190         }
3191         else
3192         {
3193             pPHY_Reg->DATX8[0].DXGCR |= (0x3<<9);  //dynamic RTT enable
3194             pPHY_Reg->DATX8[1].DXGCR |= (0x3<<9);
3195             if(!(pDDR_Reg->PPCFG & 1))
3196             {
3197                 pPHY_Reg->DATX8[2].DXGCR |= (0x3<<9);
3198                 pPHY_Reg->DATX8[3].DXGCR |= (0x3<<9);
3199             }
3200         }
3201     }
3202     else
3203     {
3204         pPHY_Reg->DATX8[0].DXGCR &= ~(0x3<<9);  //dynamic RTT disable
3205         pPHY_Reg->DATX8[1].DXGCR &= ~(0x3<<9);
3206         if(!(pDDR_Reg->PPCFG & 1))
3207         {
3208             pPHY_Reg->DATX8[2].DXGCR &= ~(0x3<<9);
3209             pPHY_Reg->DATX8[3].DXGCR &= ~(0x3<<9);
3210         }
3211     }
3212     if(DATA(mem_type) == LPDDR2)
3213     {
3214         tmp = GET_LPDDR2_DS_ODT();  //DS=34ohm,ODT=171ohm
3215     }
3216     else
3217     {
3218         tmp = GET_DDR3_DS_ODT();  //DS=34ohm,ODT=171ohm
3219     }
3220     cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3221     if(cs > 1)
3222     {
3223         pPHY_Reg->ZQ1CR[0] = tmp;
3224         dsb();
3225     }
3226     pPHY_Reg->ZQ0CR[0] = tmp;
3227     dsb();
3228 }
3229
3230 void PIE_FUNC(ddr_adjust_config)(void *arg)
3231 {
3232     uint32 value = (uint32)arg;
3233
3234     //enter config state
3235     ddr_move_to_Config_state();
3236
3237     //set data training address
3238     pPHY_Reg->DTAR = value;
3239
3240     //set auto power down idle
3241     pDDR_Reg->MCFG=(pDDR_Reg->MCFG&0xffff00ff)|(PD_IDLE<<8);
3242
3243     //CKDV=00
3244     pPHY_Reg->PGCR &= ~(0x3<<12);
3245
3246     //enable the hardware low-power interface
3247     pDDR_Reg->SCFG.b.hw_low_power_en = 1;
3248
3249     if(pDDR_Reg->PPCFG & 1)
3250     {
3251         pPHY_Reg->DATX8[2].DXGCR &= ~(1);          //disable byte
3252         pPHY_Reg->DATX8[3].DXGCR &= ~(1);
3253         pPHY_Reg->DATX8[2].DXDLLCR |= 0x80000000;  //disable DLL
3254         pPHY_Reg->DATX8[3].DXDLLCR |= 0x80000000;
3255     }
3256
3257     ddr_update_odt();
3258
3259     //enter access state
3260     ddr_move_to_Access_state();
3261 }
3262 EXPORT_PIE_SYMBOL(FUNC(ddr_adjust_config));
3263
3264 static void ddr_adjust_config(uint32_t dram_type)
3265 {
3266     uint32 value;
3267     u32 i;
3268     volatile u32 n;
3269     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3270
3271     //get data training address before idle port
3272     value = ddr_get_datatraing_addr();
3273
3274     /** 1. Make sure there is no host access */
3275     flush_cache_all();
3276     outer_flush_all();
3277     flush_tlb_all();
3278     isb();
3279
3280     for(i=0;i<SRAM_SIZE/4096;i++)
3281     {
3282         n=temp[1024*i];
3283         barrier();
3284     }
3285     n= pDDR_Reg->SCFG.d32;
3286     n= pPHY_Reg->RIDR;
3287     n= pCRU_Reg->CRU_PLL_CON[0][0];
3288     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3289     n= *(volatile uint32_t *)SysSrv_DdrConf;
3290     n= READ_GRF_REG();
3291     dsb();
3292
3293     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_adjust_config)),
3294                     (void *)value,
3295                     rockchip_sram_stack);
3296 }
3297
3298 static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz)
3299 {
3300     PHY_TIMING_T  *p_publ_timing=&(DATA(ddr_reg).publ.phy_timing);
3301     uint32 cs;
3302
3303     ddr_move_to_Config_state();
3304     pDDR_Reg->TZQCSI = 0;
3305     if((nMHz<=DDR3_DDR2_DLL_DISABLE_FREQ) && ((DATA(mem_type) == DDR3) || (DATA(mem_type) == DDR2)))  // DLL disable
3306     {
3307         cs = ((pPHY_Reg->PGCR>>18) & 0xF);
3308         pPHY_Reg->MR[1] = (((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE);
3309         ddr_send_command(cs, MRS_cmd, bank_addr(0x1) | cmd_addr(((p_publ_timing->mr[1])) | DDR3_DLL_DISABLE));
3310     }
3311     ddr_move_to_Lowpower_state();
3312
3313     ddr_set_dll_bypass(0);  //dll bypass
3314     SET_DDRPHY_CLKGATE(1);  //disable DDR PHY clock
3315     ddr_delayus(1);
3316 }
3317
3318 static void __sramfunc ddr_selfrefresh_exit(void)
3319 {
3320     uint32 n;
3321
3322     SET_DDRPHY_CLKGATE(0);  //enable DDR PHY clock
3323     dsb();
3324     ddr_set_dll_bypass(DATA(ddr_freq));
3325     ddr_reset_dll();
3326     //ddr_delayus(10);   //wait DLL lock
3327
3328     ddr_move_to_Config_state();
3329     ddr_update_timing();
3330     ddr_update_mr();
3331     ddr_update_odt();
3332     n = ddr_data_training();
3333     ddr_move_to_Access_state();
3334     if(n!=0)
3335     {
3336         sram_printascii("DTT failed!\n");
3337     }
3338 }
3339
3340 #if defined(CONFIG_ARCH_RK3066B)
3341 static __sramdata uint32_t data8_dqstr[25][4];
3342 static __sramdata uint32_t min_ddr_freq,dqstr_flag=false;
3343
3344 int ddr_get_datatraing_value_3168(bool end_flag,uint32_t dqstr_value,uint32_t min_freq)
3345 {
3346     if(end_flag == true)
3347     {
3348         dqstr_flag = true;    //complete learn data training value flag
3349         min_ddr_freq = min_freq;
3350         return 0;
3351     }
3352
3353     data8_dqstr[dqstr_value][0]=pPHY_Reg->DATX8[0].DXDQSTR;
3354     data8_dqstr[dqstr_value][1]=pPHY_Reg->DATX8[0].DXDQSTR;
3355     data8_dqstr[dqstr_value][2]=pPHY_Reg->DATX8[0].DXDQSTR;
3356     data8_dqstr[dqstr_value][3]=pPHY_Reg->DATX8[0].DXDQSTR;
3357
3358     ddr_print("training %luMhz[%d]:0x%x-0x%x-0x%x-0x%x\n",
3359         clk_get_rate(clk_get(NULL, "ddr"))/1000000,dqstr_value,data8_dqstr[dqstr_value][0],data8_dqstr[dqstr_value][1],
3360         data8_dqstr[dqstr_value][2],data8_dqstr[dqstr_value][3]);
3361     return 0;
3362 }
3363
3364 static void __sramfunc ddr_set_pll_enter_3168(uint32_t freq_slew)
3365 {
3366     uint32_t value_1u,value_100n;
3367     ddr_move_to_Config_state();
3368
3369     if(freq_slew == 1)
3370     {
3371         value_100n = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3372         value_1u = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3373         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = pDDR_Reg->TOGCNT1U;
3374         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = pDDR_Reg->TOGCNT100N;
3375         ddr_update_timing();
3376         ddr_update_mr();
3377         DATA(ddr_reg).pctl.pctl_timing.togcnt100n = value_100n;
3378         DATA(ddr_reg).pctl.pctl_timing.togcnt1u = value_1u;
3379     }
3380     else
3381     {
3382         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3383         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3384     }
3385
3386     pDDR_Reg->TZQCSI = 0;
3387     ddr_move_to_Lowpower_state();
3388
3389     ddr_set_dll_bypass(0);  //dll bypass
3390     SET_DDRPHY_CLKGATE(1);  //disable DDR PHY clock
3391     dsb();
3392 }
3393
3394 void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32_t dqstr_value)
3395 {
3396     SET_DDRPHY_CLKGATE(0);  //enable DDR PHY clock
3397     dsb();
3398     ddr_set_dll_bypass(DATA(ddr_freq));
3399     ddr_reset_dll();
3400
3401     if(dqstr_flag==true)
3402     {
3403         pPHY_Reg->DATX8[0].DXDQSTR=data8_dqstr[dqstr_value][0];
3404         pPHY_Reg->DATX8[1].DXDQSTR=data8_dqstr[dqstr_value][1];
3405         pPHY_Reg->DATX8[2].DXDQSTR=data8_dqstr[dqstr_value][2];
3406         pPHY_Reg->DATX8[3].DXDQSTR=data8_dqstr[dqstr_value][3];
3407     }
3408
3409     ddr_update_odt();
3410     ddr_move_to_Config_state();
3411     if(freq_slew == 1)
3412     {
3413         pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl.pctl_timing.togcnt100n;
3414         pDDR_Reg->TOGCNT1U = DATA(ddr_reg).pctl.pctl_timing.togcnt1u;
3415         pDDR_Reg->TZQCSI = DATA(ddr_reg).pctl.pctl_timing.tzqcsi;
3416     }
3417     else
3418     {
3419         ddr_update_timing();
3420         ddr_update_mr();
3421     }
3422     ddr_data_training();
3423     ddr_move_to_Access_state();
3424 }
3425 #endif
3426
3427 /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3428 static void __sramfunc ddr_SRE_2_SRX(uint32 freq, uint32_t freq_slew,uint32_t dqstr_value)
3429 {
3430     /** 2. ddr enter self-refresh mode or precharge power-down mode */
3431     idle_port();
3432 #if defined(CONFIG_ARCH_RK3066B)
3433     ddr_set_pll_enter_3168(freq_slew);
3434 #else
3435     ddr_selfrefresh_enter(freq);
3436 #endif
3437
3438     /** 3. change frequence  */
3439     FUNC(ddr_set_pll)(freq,1);
3440     DATA(ddr_freq) = freq;
3441
3442     /** 5. Issues a Mode Exit command   */
3443 #if defined(CONFIG_ARCH_RK3066B)
3444     ddr_set_pll_exit_3168(freq_slew,dqstr_value);
3445 #else
3446     ddr_selfrefresh_exit();
3447 #endif
3448     deidle_port();
3449     dsb();
3450 }
3451
3452 struct ddr_change_freq_sram_param {
3453     uint32_t arm_freq;
3454     uint32_t freq;
3455     uint32_t freq_slew;
3456     uint32_t dqstr_value;
3457 };
3458
3459 void PIE_FUNC(ddr_change_freq_sram)(void *arg)
3460 {
3461     struct ddr_change_freq_sram_param *param = arg;
3462     loops_per_us = LPJ_100MHZ * param->arm_freq / 1000000;
3463     /* Make sure ddr_SRE_2_SRX paramter less than 4 */
3464     ddr_SRE_2_SRX(param->freq, param->freq_slew, param->dqstr_value);
3465 }
3466 EXPORT_PIE_SYMBOL(FUNC(ddr_change_freq_sram));
3467
3468 static noinline uint32_t ddr_change_freq_sram(uint32_t nMHz , struct ddr_freq_t ddr_freq_t)
3469 {
3470     register uint32_t freq;
3471     register uint32_t freq_slew=0;
3472     register uint32_t dqstr_value=0;
3473     unsigned long flags;
3474     struct ddr_change_freq_sram_param param;
3475     volatile u32 n;
3476     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3477     u32 i;
3478
3479 #if defined(CONFIG_ARCH_RK3066B)
3480     if(dqstr_flag==true)
3481     {
3482         dqstr_value=((nMHz-min_ddr_freq+1)/25 + 1) /2;
3483         freq_slew = (nMHz>ddr_freq)? 1 : 0;
3484     }
3485 #endif
3486
3487     freq=p_ddr_set_pll(nMHz,0);
3488
3489     ddr_get_parameter(freq);
3490
3491     /** 1. Make sure there is no host access */
3492     local_irq_save(flags);
3493     local_fiq_disable();
3494     flush_cache_all();
3495     outer_flush_all();
3496     flush_tlb_all();
3497     isb();
3498
3499 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3500     if(ddr_freq_t.screen_ft_us > 0)
3501     {
3502         ddr_freq_t.t1 = cpu_clock(0);
3503         ddr_freq_t.t2 = (u32)(ddr_freq_t.t1 - ddr_freq_t.t0);   //ns
3504
3505         //if test_count exceed maximum test times,ddr_freq_t.screen_ft_us == 0xfefefefe by ddr_freq.c
3506         if( (ddr_freq_t.t2 > ddr_freq_t.screen_ft_us*1000) && (ddr_freq_t.screen_ft_us != 0xfefefefe))
3507         {
3508             freq = 0;
3509             goto end;
3510         }
3511         else
3512         {
3513             rk_fb_poll_wait_frame_complete();
3514         }
3515     }
3516 #endif
3517     for(i=0;i<SRAM_SIZE/4096;i++)
3518     {
3519         n=temp[1024*i];
3520         barrier();
3521     }
3522
3523     n= pDDR_Reg->SCFG.d32;
3524     n= pPHY_Reg->RIDR;
3525     n= pCRU_Reg->CRU_PLL_CON[0][0];
3526     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3527     n= *(volatile uint32_t *)SysSrv_DdrConf;
3528     n= READ_GRF_REG();
3529     dsb();
3530
3531     param.arm_freq = ddr_get_pll_freq(APLL);
3532     param.freq = freq;
3533     param.freq_slew = freq_slew;
3534     param.dqstr_value = dqstr_value;
3535     call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_change_freq_sram)),
3536                     &param,
3537                     rockchip_sram_stack-(NR_CPUS-1)*PAUSE_CPU_STACK_SIZE);
3538
3539 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3540 end:
3541 #endif
3542     local_fiq_enable();
3543     local_irq_restore(flags);
3544     return freq;
3545 }
3546
3547 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH)
3548 static uint32_t ddr_change_freq_gpll_dpll(uint32_t nMHz)
3549 {
3550     uint32_t gpll_freq,gpll_div;
3551     struct ddr_freq_t ddr_freq_t;
3552     ddr_freq_t.screen_ft_us = 0;
3553
3554     if(true == ddr_rk3188_dpll_is_good)
3555     {
3556         gpllvaluel = ddr_get_pll_freq(GPLL);
3557
3558         if((200 < gpllvaluel) ||( gpllvaluel <1600))      //GPLL:200MHz~1600MHz
3559         {
3560             gpll_div = (gpllvaluel+nMHz-1)/nMHz;
3561             if( gpllvaluel > 800)     //800-1600MHz  /4:200MHz-400MHz
3562             {
3563                 gpll_freq = gpllvaluel/4;
3564                 gpll_div = 4;
3565             }
3566             else if( gpllvaluel > 400)    //400-800MHz  /2:200MHz-400MHz
3567             {
3568                 gpll_freq = gpllvaluel/2;
3569                 gpll_div = 2;
3570             }
3571             else        //200-400MHz  /1:200MHz-400MHz
3572             {
3573                 gpll_freq = gpllvaluel;
3574                 gpll_div = 1;
3575             }
3576
3577             *p_ddr_select_gpll_div=gpll_div;    //select GPLL
3578             ddr_change_freq_sram(gpll_freq,ddr_freq_t);
3579             *p_ddr_select_gpll_div=0;
3580
3581             p_ddr_set_pll(nMHz,0); //count DPLL
3582             p_ddr_set_pll(nMHz,2); //lock DPLL only,but not select DPLL
3583         }
3584         else
3585         {
3586             ddr_print("GPLL frequency = %dMHz,Not suitable for ddr_clock \n",gpllvaluel);
3587         }
3588     }
3589
3590     return ddr_change_freq_sram(nMHz,ddr_freq_t);
3591
3592 }
3593 #endif
3594
3595 /*****************************************
3596 if rk3188 DPLL is bad,use GPLL
3597             GPLL                   DDR_CLCOK
3598 1000MHz-2000MHz       4:250MHz-500MHz
3599 800MHz-1000MHz        4:200MHz-250MHz    2:400MHz-500MHz
3600 500MHz-800MHz          2:250MHz-400MHz
3601 200MHz-500MHz          1:200MHz-500MHz
3602 ******************************************/
3603 #if 0
3604 static noinline uint32_t ddr_change_freq(uint32_t nMHz)
3605 {
3606     struct ddr_freq_t ddr_freq_t;
3607     ddr_freq_t.screen_ft_us = 0;
3608
3609 #if defined(ENABLE_DDR_CLCOK_GPLL_PATH) && (defined(CONFIG_ARCH_RK3188) || defined(CONFIG_ARCH_RK319X))
3610     return ddr_change_freq_gpll_dpll(nMHz);
3611 #else
3612     return ddr_change_freq_sram(nMHz,ddr_freq_t);
3613 #endif
3614 }
3615 #endif
3616
3617 bool DEFINE_PIE_DATA(cpu_pause[NR_CPUS]);
3618 volatile bool *p_cpu_pause;
3619 static inline bool is_cpu0_paused(unsigned int cpu) { smp_rmb(); return DATA(cpu_pause)[0]; }
3620 static inline void set_cpuX_paused(unsigned int cpu, bool pause) { DATA(cpu_pause)[cpu] = pause; smp_wmb(); }
3621 static inline bool is_cpuX_paused(unsigned int cpu) { smp_rmb(); return p_cpu_pause[cpu]; }
3622 static inline void set_cpu0_paused(bool pause) { p_cpu_pause[0] = pause; smp_wmb();}
3623
3624 #define MAX_TIMEOUT (16000000UL << 6) //>0.64s
3625
3626 /* Do not use stack, safe on SMP */
3627 void PIE_FUNC(_pause_cpu)(void *arg)
3628 {
3629         unsigned int cpu = (unsigned int)arg;
3630
3631         set_cpuX_paused(cpu, true);
3632         while (is_cpu0_paused(cpu));
3633         set_cpuX_paused(cpu, false);
3634 }
3635
3636 static void pause_cpu(void *info)
3637 {
3638         unsigned int cpu = raw_smp_processor_id();
3639
3640         call_with_stack(fn_to_pie(rockchip_pie_chunk, &FUNC(_pause_cpu)),
3641                         (void *)cpu,
3642                         rockchip_sram_stack-(cpu-1)*PAUSE_CPU_STACK_SIZE);
3643 }
3644
3645 static void wait_cpu(void *info)
3646 {
3647 }
3648
3649 static int __ddr_change_freq(uint32_t nMHz, struct ddr_freq_t ddr_freq_t)
3650 {
3651         u32 timeout = MAX_TIMEOUT;
3652         unsigned int cpu;
3653         unsigned int this_cpu = smp_processor_id();
3654         int ret = 0;
3655
3656         cpu_maps_update_begin();
3657         local_bh_disable();
3658         set_cpu0_paused(true);
3659         smp_call_function((smp_call_func_t)pause_cpu, NULL, 0);
3660
3661         for_each_online_cpu(cpu) {
3662                 if (cpu == this_cpu)
3663                         continue;
3664                 while (!is_cpuX_paused(cpu) && --timeout);
3665                 if (timeout == 0) {
3666                         pr_err("pause cpu %d timeout\n", cpu);
3667                         goto out;
3668                 }
3669         }
3670
3671         ret = ddr_change_freq_sram(nMHz, ddr_freq_t);
3672
3673 out:
3674         set_cpu0_paused(false);
3675         local_bh_enable();
3676         smp_call_function(wait_cpu, NULL, true);
3677         cpu_maps_update_done();
3678
3679         return ret;
3680 }
3681
3682 static int _ddr_change_freq(uint32_t nMHz)
3683 {
3684         struct ddr_freq_t ddr_freq_t;
3685         //int test_count=0;
3686
3687         ddr_freq_t.screen_ft_us = 0;
3688         ddr_freq_t.t0 = 0;
3689         ddr_freq_t.t1 = 0;
3690 #if defined (DDR_CHANGE_FREQ_IN_LCDC_VSYNC)
3691         do
3692         {
3693                 if(rk_fb_poll_wait_frame_complete() == true)
3694                 {
3695                         ddr_freq_t.t0 = cpu_clock(0);
3696                         ddr_freq_t.screen_ft_us = rk_fb_get_prmry_screen_ft();
3697
3698                         test_count++;
3699                         if(test_count > 10) //test 10 times
3700                         {
3701                                 ddr_freq_t.screen_ft_us = 0xfefefefe;
3702                                 dprintk(DEBUG_DDR,"%s:test_count exceed maximum!\n",__func__);
3703                         }
3704                         dprintk(DEBUG_VERBOSE,"%s:test_count=%d\n",__func__,test_count);
3705                         usleep_range(ddr_freq_t.screen_ft_us-test_count*1000,ddr_freq_t.screen_ft_us-test_count*1000);
3706
3707                         flush_cache_all();
3708                         outer_flush_all();
3709                         flush_tlb_all();
3710                 }
3711         }while(__ddr_change_freq(nMHz, ddr_freq_t)==0);
3712 #else
3713         return __ddr_change_freq(nMHz, ddr_freq_t);
3714 #endif
3715 }
3716
3717 static long _ddr_round_rate(uint32_t nMHz)
3718 {
3719         return p_ddr_set_pll(nMHz, 0);
3720 }
3721
3722 static void _ddr_set_auto_self_refresh(bool en)
3723 {
3724     //set auto self-refresh idle
3725     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0;
3726 }
3727
3728 #define PERI_ACLK_DIV_MASK 0x1f
3729 #define PERI_ACLK_DIV_OFF 0
3730
3731 #define PERI_HCLK_DIV_MASK 0x3
3732 #define PERI_HCLK_DIV_OFF 8
3733
3734 #define PERI_PCLK_DIV_MASK 0x3
3735 #define PERI_PCLK_DIV_OFF 12
3736 #if 0
3737 static __sramdata u32 cru_sel32_sram;
3738 static void __sramfunc ddr_suspend(void)
3739 {
3740     u32 i;
3741     volatile u32 n;
3742     volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
3743     int pll_id;
3744
3745         pll_id=GET_DDR_PLL_SRC();
3746     /** 1. Make sure there is no host access */
3747     flush_cache_all();
3748     outer_flush_all();
3749     //flush_tlb_all();
3750
3751     for(i=0;i<SRAM_SIZE/4096;i++)
3752     {
3753         n=temp[1024*i];
3754         barrier();
3755     }
3756
3757     n= pDDR_Reg->SCFG.d32;
3758     n= pPHY_Reg->RIDR;
3759     n= pCRU_Reg->CRU_PLL_CON[0][0];
3760     n= pPMU_Reg->PMU_WAKEUP_CFG[0];
3761     n= *(volatile uint32_t *)SysSrv_DdrConf;
3762     n= READ_GRF_REG();
3763     dsb();
3764
3765     ddr_selfrefresh_enter(0);
3766
3767     SET_PLL_MODE(pll_id, 0);   //PLL slow-mode
3768     dsb();
3769     ddr_delayus(1);
3770     SET_PLL_PD(pll_id, 1);         //PLL power-down
3771     dsb();
3772     ddr_delayus(1);
3773     if(pll_id==GPLL)
3774     {
3775         cru_sel32_sram=   pCRU_Reg->CRU_CLKSEL_CON[10];
3776
3777         pCRU_Reg->CRU_CLKSEL_CON[10]=CRU_W_MSK_SETBITS(0, PERI_ACLK_DIV_OFF, PERI_ACLK_DIV_MASK)
3778                                    | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
3779                                    |CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK);
3780     }
3781     pPHY_Reg->DSGCR = pPHY_Reg->DSGCR&(~((0x1<<28)|(0x1<<29)));  //CKOE
3782 }
3783
3784 static void __sramfunc ddr_resume(void)
3785 {
3786     int delay=1000;
3787     int pll_id;
3788
3789     pll_id=GET_DDR_PLL_SRC();
3790         pPHY_Reg->DSGCR = pPHY_Reg->DSGCR|((0x1<<28)|(0x1<<29));  //CKOE
3791         dsb();
3792
3793         if(pll_id==GPLL)
3794         pCRU_Reg->CRU_CLKSEL_CON[10]=0xffff0000|cru_sel32_sram;
3795
3796     SET_PLL_PD(pll_id, 0);         //PLL no power-down
3797     dsb();
3798     while (delay > 0)
3799     {
3800             ddr_delayus(1);
3801         if (GET_DPLL_LOCK_STATUS())
3802             break;
3803         delay--;
3804     }
3805
3806     SET_PLL_MODE(pll_id, 1);   //PLL normal
3807     dsb();
3808
3809     ddr_selfrefresh_exit();
3810 }
3811 #endif
3812
3813 //»ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
3814 static uint32 ddr_get_cap(void)
3815 {
3816     uint32 cap;
3817
3818     if(DDR_SYS_REG())
3819     {
3820         cap = (1 << (READ_CS0_ROW_INFO()+READ_COL_INFO()+READ_BK_INFO()+READ_BW_INFO()));
3821         if(READ_CS_INFO()>1)
3822         {
3823             cap +=(1 << (READ_CS1_ROW_INFO()+READ_COL_INFO()+READ_BK_INFO()+READ_BW_INFO()));
3824         }
3825     }
3826     else
3827     {
3828         cap = (1 << (ddr_get_row()+ddr_get_col()+ddr_get_bank()+ddr_get_bw()))*ddr_get_cs();
3829     }
3830
3831     return cap;
3832 }
3833
3834 #if 0
3835 static void ddr_reg_save(void)
3836 {
3837     //PCTLR
3838     p_ddr_reg->pctl.SCFG = pDDR_Reg->SCFG.d32;
3839     p_ddr_reg->pctl.CMDTSTATEN = pDDR_Reg->CMDTSTATEN;
3840     p_ddr_reg->pctl.MCFG1 = pDDR_Reg->MCFG1;
3841     p_ddr_reg->pctl.MCFG = pDDR_Reg->MCFG;
3842     p_ddr_reg->pctl.pctl_timing.ddrFreq = ddr_freq;
3843     p_ddr_reg->pctl.DFITCTRLDELAY = pDDR_Reg->DFITCTRLDELAY;
3844     p_ddr_reg->pctl.DFIODTCFG = pDDR_Reg->DFIODTCFG;
3845     p_ddr_reg->pctl.DFIODTCFG1 = pDDR_Reg->DFIODTCFG1;
3846     p_ddr_reg->pctl.DFIODTRANKMAP = pDDR_Reg->DFIODTRANKMAP;
3847     p_ddr_reg->pctl.DFITPHYWRDATA = pDDR_Reg->DFITPHYWRDATA;
3848     p_ddr_reg->pctl.DFITPHYWRLAT = pDDR_Reg->DFITPHYWRLAT;
3849     p_ddr_reg->pctl.DFITRDDATAEN = pDDR_Reg->DFITRDDATAEN;
3850     p_ddr_reg->pctl.DFITPHYRDLAT = pDDR_Reg->DFITPHYRDLAT;
3851     p_ddr_reg->pctl.DFITPHYUPDTYPE0 = pDDR_Reg->DFITPHYUPDTYPE0;
3852     p_ddr_reg->pctl.DFITPHYUPDTYPE1 = pDDR_Reg->DFITPHYUPDTYPE1;
3853     p_ddr_reg->pctl.DFITPHYUPDTYPE2 = pDDR_Reg->DFITPHYUPDTYPE2;
3854     p_ddr_reg->pctl.DFITPHYUPDTYPE3 = pDDR_Reg->DFITPHYUPDTYPE3;
3855     p_ddr_reg->pctl.DFITCTRLUPDMIN = pDDR_Reg->DFITCTRLUPDMIN;
3856     p_ddr_reg->pctl.DFITCTRLUPDMAX = pDDR_Reg->DFITCTRLUPDMAX;
3857     p_ddr_reg->pctl.DFITCTRLUPDDLY = pDDR_Reg->DFITCTRLUPDDLY;
3858
3859     p_ddr_reg->pctl.DFIUPDCFG = pDDR_Reg->DFIUPDCFG;
3860     p_ddr_reg->pctl.DFITREFMSKI = pDDR_Reg->DFITREFMSKI;
3861     p_ddr_reg->pctl.DFITCTRLUPDI = pDDR_Reg->DFITCTRLUPDI;
3862     p_ddr_reg->pctl.DFISTCFG0 = pDDR_Reg->DFISTCFG0;
3863     p_ddr_reg->pctl.DFISTCFG1 = pDDR_Reg->DFISTCFG1;
3864     p_ddr_reg->pctl.DFITDRAMCLKEN = pDDR_Reg->DFITDRAMCLKEN;
3865     p_ddr_reg->pctl.DFITDRAMCLKDIS = pDDR_Reg->DFITDRAMCLKDIS;
3866     p_ddr_reg->pctl.DFISTCFG2 = pDDR_Reg->DFISTCFG2;
3867     p_ddr_reg->pctl.DFILPCFG0 = pDDR_Reg->DFILPCFG0;
3868
3869     //PUBL
3870     p_ddr_reg->publ.PIR = pPHY_Reg->PIR;
3871     p_ddr_reg->publ.PGCR = pPHY_Reg->PGCR;
3872     p_ddr_reg->publ.DLLGCR = pPHY_Reg->DLLGCR;
3873     p_ddr_reg->publ.ACDLLCR = pPHY_Reg->ACDLLCR;
3874     p_ddr_reg->publ.PTR[0] = pPHY_Reg->PTR[0];
3875     p_ddr_reg->publ.PTR[1] = pPHY_Reg->PTR[1];
3876     p_ddr_reg->publ.PTR[2] = pPHY_Reg->PTR[2];
3877     p_ddr_reg->publ.ACIOCR = pPHY_Reg->ACIOCR;
3878     p_ddr_reg->publ.DXCCR = pPHY_Reg->DXCCR;
3879     p_ddr_reg->publ.DSGCR = pPHY_Reg->DSGCR;
3880     p_ddr_reg->publ.DCR = pPHY_Reg->DCR.d32;
3881     p_ddr_reg->publ.ODTCR = pPHY_Reg->ODTCR;
3882     p_ddr_reg->publ.DTAR = pPHY_Reg->DTAR;
3883     p_ddr_reg->publ.ZQ0CR0 = (pPHY_Reg->ZQ0SR[0] & 0x0FFFFFFF) | (0x1<<28);
3884     p_ddr_reg->publ.ZQ1CR0 = (pPHY_Reg->ZQ1SR[0] & 0x0FFFFFFF) | (0x1<<28);
3885
3886     p_ddr_reg->publ.DX0GCR = pPHY_Reg->DATX8[0].DXGCR;
3887     p_ddr_reg->publ.DX0DLLCR = pPHY_Reg->DATX8[0].DXDLLCR;
3888     p_ddr_reg->publ.DX0DQTR = pPHY_Reg->DATX8[0].DXDQTR;
3889     p_ddr_reg->publ.DX0DQSTR = pPHY_Reg->DATX8[0].DXDQSTR;
3890
3891     p_ddr_reg->publ.DX1GCR = pPHY_Reg->DATX8[1].DXGCR;
3892     p_ddr_reg->publ.DX1DLLCR = pPHY_Reg->DATX8[1].DXDLLCR;
3893     p_ddr_reg->publ.DX1DQTR = pPHY_Reg->DATX8[1].DXDQTR;
3894     p_ddr_reg->publ.DX1DQSTR = pPHY_Reg->DATX8[1].DXDQSTR;
3895
3896     p_ddr_reg->publ.DX2GCR = pPHY_Reg->DATX8[2].DXGCR;
3897     p_ddr_reg->publ.DX2DLLCR = pPHY_Reg->DATX8[2].DXDLLCR;
3898     p_ddr_reg->publ.DX2DQTR = pPHY_Reg->DATX8[2].DXDQTR;
3899     p_ddr_reg->publ.DX2DQSTR = pPHY_Reg->DATX8[2].DXDQSTR;
3900
3901     p_ddr_reg->publ.DX3GCR = pPHY_Reg->DATX8[3].DXGCR;
3902     p_ddr_reg->publ.DX3DLLCR = pPHY_Reg->DATX8[3].DXDLLCR;
3903     p_ddr_reg->publ.DX3DQTR = pPHY_Reg->DATX8[3].DXDQTR;
3904     p_ddr_reg->publ.DX3DQSTR = pPHY_Reg->DATX8[3].DXDQSTR;
3905
3906     //NOC
3907     p_ddr_reg->DdrConf = *(volatile uint32_t *)SysSrv_DdrConf;
3908     p_ddr_reg->DdrMode = *(volatile uint32_t *)SysSrv_DdrMode;
3909     p_ddr_reg->ReadLatency = *(volatile uint32_t *)SysSrv_ReadLatency;
3910 }
3911
3912 static __attribute__((aligned(4))) __sramdata uint32 ddr_reg_resume[] =
3913 {
3914 #include "ddr_reg_resume.inc"
3915 };
3916 #endif
3917
3918 static int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
3919 {
3920     volatile uint32_t value = 0;
3921     uint32_t die=1;
3922     uint32_t gsr,dqstr;
3923     struct clk *clk;
3924
3925     ddr_print("version 1.00 20140228 \n");
3926
3927     p_ddr_reg = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_reg));
3928     p_ddr_select_gpll_div = kern_to_pie(rockchip_pie_chunk, &DATA(ddr_select_gpll_div));
3929     p_mem_type = kern_to_pie(rockchip_pie_chunk, &DATA(mem_type));
3930     p_ddr_set_pll = fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_set_pll));
3931     p_cpu_pause = kern_to_pie(rockchip_pie_chunk, &DATA(cpu_pause[0]));
3932
3933     *p_mem_type = pPHY_Reg->DCR.b.DDRMD;
3934     ddr_speed_bin = dram_speed_bin;
3935
3936     if(freq != 0)
3937         ddr_freq = freq;
3938     else
3939         ddr_freq = clk_get_rate(clk_get(NULL, "ddr"))/1000000;
3940     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_freq)) = ddr_freq;
3941
3942     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = 0;
3943     ddr_soc_is_rk3188_plus = GET_3188_PLUS_STATUS();
3944     if(true == ddr_soc_is_rk3188_plus)
3945     {
3946         ddr_print("A\n");
3947     }
3948     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_soc_is_rk3188_plus)) = ddr_soc_is_rk3188_plus;
3949     ddr_rk3188_dpll_is_good = GET_DPLL_STATUS();
3950     if(false == ddr_rk3188_dpll_is_good)
3951     {
3952         ddr_print("T\n");
3953     }
3954     *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_rk3188_dpll_is_good)) = ddr_rk3188_dpll_is_good;
3955     switch(*p_mem_type)
3956     {
3957         case DDR3:
3958             if(DDR_SYS_REG())
3959             {
3960                 die = (8<<READ_BW_INFO())/(8<<READ_DIE_BW_INFO());
3961             }
3962             else
3963             {
3964                 if(pDDR_Reg->PPCFG & 1)
3965                 {
3966                         die=1;
3967                 }
3968                 else
3969                 {
3970                         die = 2;
3971                 }
3972             }
3973             ddr_print("DDR3 Device\n");
3974             break;
3975         case LPDDR2:
3976             ddr_print("LPDDR2 Device\n");
3977             break;
3978         case DDR2:
3979             ddr_print("DDR2 Device\n");
3980             break;
3981         case DDR:
3982             ddr_print("DDR Device\n");
3983             break;
3984         default:
3985             ddr_print("LPDDR Device\n");
3986             break;
3987     }
3988     //get capability per chip, not total size, used for calculate tRFC
3989     ddr_capability_per_die = ddr_get_cap()/(ddr_get_cs()*die);
3990     ddr_print("Bus Width=%d Col=%d Bank=%d Row=%d CS=%d Total Capability=%dMB\n",
3991                                                                     ddr_get_bw()*16,\
3992                                                                     ddr_get_col(), \
3993                                                                     (0x1<<(ddr_get_bank())), \
3994                                                                     ddr_get_row(), \
3995                                                                     ddr_get_cs(), \
3996                                                                     (ddr_get_cap()>>20));
3997     ddr_adjust_config(*p_mem_type);
3998
3999     clk = clk_get(NULL, "clk_ddr");
4000     if (IS_ERR(clk)) {
4001         ddr_print("failed to get ddr clk\n");
4002         clk = NULL;
4003     }
4004     if(ddr_rk3188_dpll_is_good == true)
4005     {
4006         if(freq != 0)
4007             value = clk_set_rate(clk, 1000*1000*freq);
4008         else
4009             value = clk_set_rate(clk, clk_get_rate(clk));
4010     }
4011     ddr_print("init success!!! freq=%luMHz\n", clk ? clk_get_rate(clk)/1000000 : freq);
4012
4013     for(value=0;value<4;value++)
4014     {
4015         gsr = pPHY_Reg->DATX8[value].DXGSR[0];
4016         dqstr = pPHY_Reg->DATX8[value].DXDQSTR;
4017         ddr_print("DTONE=0x%x, DTERR=0x%x, DTIERR=0x%x, DTPASS=0x%x, DGSL=%d extra clock, DGPS=%d\n", \
4018                    (gsr&0xF), ((gsr>>4)&0xF), ((gsr>>8)&0xF), ((gsr>>13)&0xFFF), (dqstr&0x7), ((((dqstr>>12)&0x3)+1)*90));
4019     }
4020     ddr_print("ZERR=%x, ZDONE=%x, ZPD=0x%x, ZPU=0x%x, OPD=0x%x, OPU=0x%x\n", \
4021                                                 (pPHY_Reg->ZQ0SR[0]>>30)&0x1, \
4022                                                 (pPHY_Reg->ZQ0SR[0]>>31)&0x1, \
4023                                                 pPHY_Reg->ZQ0SR[1]&0x3,\
4024                                                 (pPHY_Reg->ZQ0SR[1]>>2)&0x3,\
4025                                                 (pPHY_Reg->ZQ0SR[1]>>4)&0x3,\
4026                                                 (pPHY_Reg->ZQ0SR[1]>>6)&0x3);
4027     ddr_print("DRV Pull-Up=0x%x, DRV Pull-Dwn=0x%x\n", pPHY_Reg->ZQ0SR[0]&0x1F, (pPHY_Reg->ZQ0SR[0]>>5)&0x1F);
4028     ddr_print("ODT Pull-Up=0x%x, ODT Pull-Dwn=0x%x\n", (pPHY_Reg->ZQ0SR[0]>>10)&0x1F, (pPHY_Reg->ZQ0SR[0]>>15)&0x1F);
4029
4030     return 0;
4031 }
4032