arch/arm/mach-rockchip/rk3036.c

   1 /*
   2  * Device Tree support for Rockchip RK3036
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/wakeup_reason.h>
  27 #include <linux/rockchip/common.h>
  28 #include <linux/rockchip/cpu.h>
  29 #include <linux/rockchip/cpu_axi.h>
  30 #include <linux/rockchip/cru.h>
  31 #include <linux/rockchip/dvfs.h>
  32 #include <linux/rockchip/grf.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/pmu.h>
  35 #include <asm/cpuidle.h>
  36 #include <asm/cputype.h>
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/map.h>
  39 #include "loader.h"
  40 #define CPU 3036
  41 #include "sram.h"
  42 #include "pm.h"
  43
  44 #define RK3036_DEVICE(name) \
  45         { \
  46                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  47                 .pfn            = __phys_to_pfn(RK3036_##name##_PHYS), \
  48                 .length         = RK3036_##name##_SIZE, \
  49                 .type           = MT_DEVICE, \
  50         }
  51
  52 #define RK3036_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  53 #define RK3036_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  54
  55 static struct map_desc rk3036_io_desc[] __initdata = {
  56         RK3036_DEVICE(CRU),
  57         RK3036_DEVICE(GRF),
  58         RK3036_DEVICE(ROM),
  59         RK3036_DEVICE(EFUSE),
  60         RK3036_DEVICE(CPU_AXI_BUS),
  61         RK_DEVICE(RK_DDR_VIRT, RK3036_DDR_PCTL_PHYS, RK3036_DDR_PCTL_SIZE),
  62         RK_DEVICE(RK_DDR_VIRT + RK3036_DDR_PCTL_SIZE, RK3036_DDR_PHY_PHYS,
  63                   RK3036_DDR_PHY_SIZE),
  64         RK_DEVICE(RK_GPIO_VIRT(0), RK3036_GPIO0_PHYS, RK3036_GPIO_SIZE),
  65         RK_DEVICE(RK_GPIO_VIRT(1), RK3036_GPIO1_PHYS, RK3036_GPIO_SIZE),
  66         RK_DEVICE(RK_GPIO_VIRT(2), RK3036_GPIO2_PHYS, RK3036_GPIO_SIZE),
  67         RK_DEVICE(RK_DEBUG_UART_VIRT, RK3036_UART2_PHYS, RK3036_UART_SIZE),
  68         RK_DEVICE(RK_GIC_VIRT, RK3036_GIC_DIST_PHYS, RK3036_GIC_DIST_SIZE),
  69         RK_DEVICE(RK_GIC_VIRT + RK3036_GIC_DIST_SIZE, RK3036_GIC_CPU_PHYS,
  70                   RK3036_GIC_CPU_SIZE),
  71         RK_DEVICE(RK3036_IMEM_VIRT, RK3036_IMEM_PHYS, SZ_4K),
  72         RK_DEVICE(RK_TIMER_VIRT, RK3036_TIMER_PHYS, RK3036_TIMER_SIZE),
  73         RK_DEVICE(RK_PWM_VIRT, RK3036_PWM_PHYS, RK3036_PWM_SIZE),
  74 };
  75
  76 static void __init rk3036_boot_mode_init(void)
  77 {
  78         u32 flag = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG4);
  79         u32 mode = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG5);
  80         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3036_CRU_RST_ST);
  81
  82         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
  83                 mode = BOOT_MODE_RECOVERY;
  84         if (rst_st & ((1 << 2) | (1 << 3)))
  85                 mode = BOOT_MODE_WATCHDOG;
  86         rockchip_boot_mode_init(flag, mode);
  87 }
  88
  89 static void usb_uart_init(void)
  90 {
  91 #ifdef CONFIG_RK_USB_UART
  92         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_STATUS0);
  93 #endif
  94         writel_relaxed(0x34000000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
  95 #ifdef CONFIG_RK_USB_UART
  96         if (!(soc_status0 & (1 << 14)) && (soc_status0 & (1 << 17))) {
  97                 /* software control usb phy enable */
  98                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK3036_GRF_UOC0_CON5);
  99                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK3036_GRF_UOC1_CON4);
 100         }
 101 #endif
 102
 103         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
 104         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 105         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 106         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 107         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 108         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 109 }
 110
 111 static void __init rk3036_dt_map_io(void)
 112 {
 113         rockchip_soc_id = ROCKCHIP_SOC_RK3036;
 114
 115         iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
 116         debug_ll_io_init();
 117         usb_uart_init();
 118
 119         /* enable timer5 for core */
 120         writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
 121         dsb();
 122         writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x00);
 123         writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x04);
 124         dsb();
 125         writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10);
 126         dsb();
 127
 128         rk3036_boot_mode_init();
 129 }
 130
 131 extern void secondary_startup(void);
 132 static int rk3036_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 133 {
 134         if (on) {
 135 #ifdef CONFIG_SMP
 136                 if (PD_CPU_1 == pd) {
 137                         writel_relaxed(0x20000
 138                                 , RK_CRU_VIRT + RK3036_CRU_SOFTRST0_CON);
 139                         dsb();
 140                         udelay(10);
 141                         writel_relaxed(virt_to_phys(secondary_startup),
 142                                            RK3036_IMEM_VIRT + 8);
 143                         writel_relaxed(0xDEADBEAF, RK3036_IMEM_VIRT + 4);
 144                         dsb_sev();
 145                 }
 146 #endif
 147         } else {
 148 #ifdef CONFIG_SMP
 149                 if (PD_CPU_1 == pd) {
 150                         writel_relaxed(0x20002
 151                                 , RK_CRU_VIRT + RK3036_CRU_SOFTRST0_CON);
 152                         dsb();
 153                 }
 154 #endif
 155         }
 156
 157         return 0;
 158 }
 159
 160 static bool rk3036_pmu_power_domain_is_on(enum pmu_power_domain pd)
 161 {
 162         return 1;
 163 }
 164
 165 static int rk3036_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 166 {
 167         return 0;
 168 }
 169
 170 static void __init rk3036_dt_init_timer(void)
 171 {
 172         rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain;
 173         rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on;
 174         rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request;
 175         of_clk_init(NULL);
 176         clocksource_of_init();
 177 }
 178
 179 #ifdef CONFIG_PM
 180 static inline void rk3036_uart_printch(char byte)
 181 {
 182 write_uart:
 183         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
 184         dsb();
 185
 186         /* loop check LSR[6], Transmitter Empty bit */
 187         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
 188                 barrier();
 189
 190         if (byte == '\n') {
 191                 byte = '\r';
 192                 goto write_uart;
 193         }
 194 }
 195
 196 static void rk3036_ddr_printch(char byte)
 197 {
 198         rk3036_uart_printch(byte);
 199
 200         rk_last_log_text(&byte, 1);
 201
 202         if (byte == '\n') {
 203                 byte = '\r';
 204                 rk_last_log_text(&byte, 1);
 205         }
 206 }
 207
 208 enum rk_plls_id {
 209         APLL_ID = 0,
 210         DPLL_ID,
 211         GPLL_ID,
 212         RK3036_END_PLL_ID,
 213 };
 214
 215 #define GPIO_INTEN 0x30
 216 #define GPIO_INT_STATUS 0x40
 217 #define GIC_DIST_PENDING_SET 0x200
 218 static void rk3036_pm_dump_irq(void)
 219 {
 220         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT
 221                 + GIC_DIST_PENDING_SET + 8) >> 4) & 7;
 222         u32 irq[4];
 223         int i;
 224
 225         for (i = 0; i < ARRAY_SIZE(irq); i++) {
 226                 irq[i] = readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET +
 227                                            (1 + i) * 4);
 228                 if (irq[i])
 229                         log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
 230         }
 231         pr_info("wakeup irq: %08x %08x %08x %08x\n",
 232                 irq[0], irq[1], irq[2], irq[3]);
 233         for (i = 0; i <= 2; i++) {
 234                 if (irq_gpio & (1 << i))
 235                         pr_info("wakeup gpio%d: %08x\n", i,
 236                                 readl_relaxed(RK_GPIO_VIRT(i) +
 237                                                   GPIO_INT_STATUS));
 238         }
 239 }
 240
 241 #define DUMP_GPIO_INTEN(ID) \
 242         do { \
 243                 u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
 244                 if (en) { \
 245                         pr_info("GPIO%d_INTEN: %08x\n", ID, en); \
 246                 } \
 247         } while (0)
 248
 249 static void rk3036_pm_dump_inten(void)
 250 {
 251         DUMP_GPIO_INTEN(0);
 252         DUMP_GPIO_INTEN(1);
 253         DUMP_GPIO_INTEN(2);
 254 }
 255
 256 static void rkpm_prepare(void)
 257 {
 258         rk3036_pm_dump_inten();
 259 }
 260 static void rkpm_finish(void)
 261 {
 262         rk3036_pm_dump_irq();
 263 }
 264
 265 static u32 clk_ungt_msk[RK3036_CRU_CLKGATES_CON_CNT];
 266 /*first clk gating setting*/
 267
 268 static u32 clk_ungt_msk_1[RK3036_CRU_CLKGATES_CON_CNT];
 269 /* first clk gating setting*/
 270
 271 static u32 clk_ungt_save[RK3036_CRU_CLKGATES_CON_CNT];
 272 /*first clk gating value saveing*/
 273
 274 static u32 *p_rkpm_clkgt_last_set;
 275 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
 276 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
 277
 278 static void gtclks_suspend(void)
 279 {
 280         int i;
 281
 282         for (i = 0; i < RK3036_CRU_CLKGATES_CON_CNT; i++) {
 283                 clk_ungt_save[i] = cru_readl(RK3036_CRU_CLKGATES_CON(i));
 284                 if (i != 10)
 285                         CLK_MSK_UNGATING(clk_ungt_msk[i]
 286                         , RK3036_CRU_CLKGATES_CON(i));
 287                 else
 288                         cru_writel(clk_ungt_msk[i], RK3036_CRU_CLKGATES_CON(i));
 289         }
 290
 291         /*gpio0_a1 clk gate should be disable for volt adjust*/
 292         if (cru_readl(RK3036_CRU_CLKGATES_CON(8)) & 0x200)
 293                 cru_writel(0x02000000, RK3036_CRU_CLKGATES_CON(8));
 294 }
 295
 296 static void gtclks_resume(void)
 297 {
 298         int i;
 299
 300         for (i = 0; i < RK3036_CRU_CLKGATES_CON_CNT; i++) {
 301                 if (i != 10)
 302                         cru_writel(clk_ungt_save[i] | 0xffff0000
 303                                 , RK3036_CRU_CLKGATES_CON(i));
 304                 else
 305                         cru_writel(clk_ungt_save[i]
 306                                 , RK3036_CRU_CLKGATES_CON(i));
 307         }
 308 }
 309
 310 static void clks_gating_suspend_init(void)
 311 {
 312         p_rkpm_clkgt_last_set = &clk_ungt_msk_1[0];
 313         if (clk_suspend_clkgt_info_get(clk_ungt_msk, p_rkpm_clkgt_last_set
 314                 , RK3036_CRU_CLKGATES_CON_CNT) == RK3036_CRU_CLKGATES_CON(0))
 315                 rkpm_set_ops_gtclks(gtclks_suspend, gtclks_resume);
 316 }
 317
 318 #define RK3036_PLL_BYPASS CRU_W_MSK_SETBITS(1, 0xF, 0x01)
 319 #define RK3036_PLL_NOBYPASS CRU_W_MSK_SETBITS(0, 0xF, 0x01)
 320 #define RK3036_PLL_POWERDOWN CRU_W_MSK_SETBITS(1, 0xD, 0x01)
 321 #define RK3036_PLL_POWERON CRU_W_MSK_SETBITS(0, 0xD, 0x01)
 322
 323 #define grf_readl(offset) readl_relaxed(RK_GRF_VIRT + offset)
 324 #define grf_writel(v, offset) do { writel_relaxed(v, \
 325         RK_GRF_VIRT + offset); dsb(); } while (0)
 326
 327 #define gpio0_readl(offset) readl_relaxed(RK_GPIO_VIRT(0) + offset)
 328 #define gpio0_writel(v, offset) do { writel_relaxed(v, RK_GPIO_VIRT(0) \
 329         + offset); dsb(); } while (0)
 330
 331 static u32 plls_con0_save[RK3036_END_PLL_ID];
 332 static u32 plls_con1_save[RK3036_END_PLL_ID];
 333 static u32 plls_con2_save[RK3036_END_PLL_ID];
 334
 335 static u32 cru_mode_con;
 336 static u32 clk_sel0, clk_sel1, clk_sel10;
 337 static void pm_pll_wait_lock(u32 pll_idx)
 338 {
 339         u32 delay = 600000U;
 340
 341         dsb();
 342         dsb();
 343         dsb();
 344         dsb();
 345         dsb();
 346         dsb();
 347         while (delay > 0) {
 348                 if ((cru_readl(RK3036_PLL_CONS(pll_idx, 1)) & (0x1 << 10)))
 349                         break;
 350                 delay--;
 351         }
 352         if (delay == 0) {
 353                 rkpm_ddr_printascii("unlock-pll:");
 354                 rkpm_ddr_printhex(pll_idx);
 355                 rkpm_ddr_printch('\n');
 356         }
 357 }
 358
 359 static void pll_udelay(u32 udelay)
 360 {
 361         u32 mode;
 362
 363         mode = cru_readl(RK3036_CRU_MODE_CON);
 364         cru_writel(RK3036_PLL_MODE_SLOW(APLL_ID), RK3036_CRU_MODE_CON);
 365         rkpm_udelay(udelay * 5);
 366         cru_writel(mode|(RK3036_PLL_MODE_MSK(APLL_ID)
 367                 << 16), RK3036_CRU_MODE_CON);
 368 }
 369
 370 static inline void plls_suspend(u32 pll_id)
 371 {
 372         plls_con0_save[pll_id] = cru_readl(RK3036_PLL_CONS((pll_id), 0));
 373         plls_con1_save[pll_id] = cru_readl(RK3036_PLL_CONS((pll_id), 1));
 374         plls_con2_save[pll_id] = cru_readl(RK3036_PLL_CONS((pll_id), 2));
 375
 376         /*cru_writel(RK3036_PLL_BYPASS, RK3036_PLL_CONS((pll_id), 0));*/
 377         cru_writel(RK3036_PLL_POWERDOWN, RK3036_PLL_CONS((pll_id), 1));
 378 }
 379 static inline void plls_resume(u32 pll_id)
 380 {
 381         u32 pllcon0, pllcon1, pllcon2;
 382
 383         pllcon0 = plls_con0_save[pll_id];
 384         pllcon1 = plls_con1_save[pll_id];
 385         pllcon2 = plls_con2_save[pll_id];
 386 /*
 387         cru_writel(pllcon0 | 0xffff0000, RK3036_PLL_CONS(pll_id, 0));
 388         cru_writel(pllcon1 | 0xf5ff0000, RK3036_PLL_CONS(pll_id, 1));
 389         cru_writel(pllcon2, RK3036_PLL_CONS(pll_id, 2));
 390 */
 391         cru_writel(RK3036_PLL_POWERON, RK3036_PLL_CONS((pll_id), 1));
 392
 393         pll_udelay(5);
 394
 395         pll_udelay(168);
 396         pm_pll_wait_lock(pll_id);
 397 }
 398
 399 static void pm_plls_suspend(void)
 400 {
 401         cru_mode_con  = cru_readl(RK3036_CRU_MODE_CON);
 402
 403         clk_sel0 = cru_readl(RK3036_CRU_CLKSELS_CON(0));
 404         clk_sel1 = cru_readl(RK3036_CRU_CLKSELS_CON(1));
 405         clk_sel10 = cru_readl(RK3036_CRU_CLKSELS_CON(10));
 406
 407         cru_writel(RK3036_PLL_MODE_SLOW(GPLL_ID), RK3036_CRU_MODE_CON);
 408         cru_writel(0
 409                                                 |CRU_W_MSK_SETBITS(0, 0, 0x1f)
 410                                                 |CRU_W_MSK_SETBITS(0, 8, 0x3)
 411                                                 |CRU_W_MSK_SETBITS(0, 12, 0x3)
 412                                                 , RK3036_CRU_CLKSELS_CON(10));
 413         plls_suspend(GPLL_ID);
 414
 415
 416         cru_writel(RK3036_PLL_MODE_SLOW(APLL_ID), RK3036_CRU_MODE_CON);
 417
 418         cru_writel(0
 419                                                 |CRU_W_MSK_SETBITS(0, 0, 0x1f)
 420                                                 |CRU_W_MSK_SETBITS(0, 8, 0x1f)
 421                                           , RK3036_CRU_CLKSELS_CON(0));
 422
 423         cru_writel(0
 424                                                 |CRU_W_MSK_SETBITS(0, 0, 0xf)
 425                                                 |CRU_W_MSK_SETBITS(0, 4, 0x7)
 426                                                 |CRU_W_MSK_SETBITS(0, 8, 0x3)
 427                                                 |CRU_W_MSK_SETBITS(0, 12, 0x7)
 428                                          , RK3036_CRU_CLKSELS_CON(1));
 429
 430         plls_suspend(APLL_ID);
 431 }
 432
 433 static void pm_plls_resume(void)
 434 {
 435         plls_resume(APLL_ID);
 436         cru_writel(clk_sel0 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x1f))
 437                 , RK3036_CRU_CLKSELS_CON(0));
 438         cru_writel(clk_sel1 | (CRU_W_MSK(0, 0xf) | CRU_W_MSK(4, 0x7)
 439                 |CRU_W_MSK(8, 0x3) | CRU_W_MSK(12, 0x7))
 440                 , RK3036_CRU_CLKSELS_CON(1));
 441         cru_writel(cru_mode_con | (RK3036_PLL_MODE_MSK(APLL_ID) << 16)
 442                 , RK3036_CRU_MODE_CON);
 443
 444         plls_resume(GPLL_ID);
 445         cru_writel(clk_sel10 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
 446                 | CRU_W_MSK(12, 0x3)), RK3036_CRU_CLKSELS_CON(10));
 447         cru_writel(cru_mode_con | (RK3036_PLL_MODE_MSK(GPLL_ID)
 448                 << 16), RK3036_CRU_MODE_CON);
 449 }
 450
 451 #include "ddr_rk3036.c"
 452 #include "pm-pie.c"
 453
 454 char PIE_DATA(sram_stack)[1024];
 455 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 456
 457 static int __init rk3036_pie_init(void)
 458 {
 459         int err;
 460
 461         if (!cpu_is_rk3036())
 462                 return 0;
 463
 464         err = rockchip_pie_init();
 465         if (err)
 466                 return err;
 467
 468         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk3036);
 469         if (IS_ERR(rockchip_pie_chunk)) {
 470                 err = PTR_ERR(rockchip_pie_chunk);
 471                 pr_err("%s: failed to load section %d\n", __func__, err);
 472                 rockchip_pie_chunk = NULL;
 473                 return err;
 474         }
 475
 476         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk
 477                 , &__pie_common_start[0]);
 478         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk
 479                 , (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 480
 481         return 0;
 482 }
 483 arch_initcall(rk3036_pie_init);
 484
 485 static void reg_pread(void)
 486 {
 487         volatile u32 n;
 488         int i;
 489
 490         volatile u32 *temp = (volatile unsigned int *)rockchip_sram_virt;
 491
 492         flush_cache_all();
 493         outer_flush_all();
 494         local_flush_tlb_all();
 495
 496         for (i = 0; i < 2; i++) {
 497                 n = temp[1024 * i];
 498                 barrier();
 499         }
 500
 501         n = readl_relaxed(RK_GPIO_VIRT(0));
 502         n = readl_relaxed(RK_GPIO_VIRT(1));
 503         n = readl_relaxed(RK_GPIO_VIRT(2));
 504
 505         n = readl_relaxed(RK_DEBUG_UART_VIRT);
 506         n = readl_relaxed(RK_CPU_AXI_BUS_VIRT);
 507         n = readl_relaxed(RK_DDR_VIRT);
 508         n = readl_relaxed(RK_GRF_VIRT);
 509         n = readl_relaxed(RK_CRU_VIRT);
 510         n = readl_relaxed(RK_PWM_VIRT);
 511 }
 512
 513 #define RK3036_CRU_UNGATING_OPS(id) cru_writel(\
 514         CRU_W_MSK_SETBITS(0,  (id), 0x1), RK3036_CRU_UART_GATE)
 515 #define RK3036_CRU_GATING_OPS(id) cru_writel(\
 516         CRU_W_MSK_SETBITS(1, (id), 0x1), RK3036_CRU_UART_GATE)
 517
 518 static inline void  uart_printch(char bbyte)
 519 {
 520         u32 reg_save;
 521         u32 u_clk_id = (RK3036_CLKGATE_UART0_SRC + CONFIG_RK_DEBUG_UART * 2);
 522         u32 u_pclk_id = (RK3036_CLKGATE_UART0_PCLK + CONFIG_RK_DEBUG_UART * 2);
 523
 524         reg_save = cru_readl(RK3036_CRU_UART_GATE);
 525         RK3036_CRU_UNGATING_OPS(u_clk_id);
 526         RK3036_CRU_UNGATING_OPS(u_pclk_id);
 527         rkpm_udelay(1);
 528
 529
 530 write_uart:
 531         writel_relaxed(bbyte, RK_DEBUG_UART_VIRT);
 532         dsb();
 533
 534         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
 535                 barrier();
 536
 537         if (bbyte == '\n') {
 538                 bbyte = '\r';
 539                 goto write_uart;
 540         }
 541
 542         cru_writel(reg_save | CRU_W_MSK(u_clk_id
 543                 , 0x1), RK3036_CRU_UART_GATE);
 544         cru_writel(reg_save | CRU_W_MSK(u_pclk_id
 545                 , 0x1), RK3036_CRU_UART_GATE);
 546
 547
 548         if (0) {
 549 write_uart1:
 550                 writel_relaxed(bbyte, RK_DEBUG_UART_VIRT);
 551                 dsb();
 552
 553                 while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
 554                         barrier();
 555         if (bbyte == '\n') {
 556                 bbyte = '\r';
 557                 goto write_uart1;
 558                 }
 559         }
 560 }
 561
 562
 563 void PIE_FUNC(sram_printch)(char byte)
 564 {
 565         uart_printch(byte);
 566 }
 567
 568 static __sramdata u32 rkpm_pwm_duty0;
 569 static __sramdata u32 rkpm_pwm_duty1;
 570 static __sramdata u32 rkpm_pwm_duty2;
 571 #define PWM_VOLTAGE 0x600
 572
 573 void PIE_FUNC(pwm_regulator_suspend)(void)
 574 {
 575         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0)) {
 576                 rkpm_pwm_duty0 = readl_relaxed(RK_PWM_VIRT + 0x08);
 577                 writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x08);
 578         }
 579
 580         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1)) {
 581                 rkpm_pwm_duty1 = readl_relaxed(RK_PWM_VIRT + 0x18);
 582                 writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x18);
 583         }
 584
 585         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2)) {
 586                 rkpm_pwm_duty2 = readl_relaxed(RK_PWM_VIRT + 0x28);
 587                 writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x28);
 588         }
 589         //rkpm_udelay(30);
 590 }
 591
 592 void PIE_FUNC(pwm_regulator_resume)(void)
 593 {
 594         rkpm_udelay(30);
 595
 596
 597         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0))
 598                 writel_relaxed(rkpm_pwm_duty0, RK_PWM_VIRT + 0x08);
 599
 600         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1))
 601                 writel_relaxed(rkpm_pwm_duty1, RK_PWM_VIRT + 0x18);
 602
 603         if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2))
 604                 writel_relaxed(rkpm_pwm_duty2, RK_PWM_VIRT + 0x28);
 605         rkpm_udelay(30);
 606 }
 607
 608 static void __init rk3036_suspend_init(void)
 609 {
 610         struct device_node *parent;
 611         u32 pm_ctrbits;
 612
 613         PM_LOG("%s enter\n", __func__);
 614
 615         parent = of_find_node_by_name(NULL, "rockchip_suspend");
 616
 617         if (IS_ERR_OR_NULL(parent)) {
 618                 PM_ERR("%s dev node err\n", __func__);
 619                 return;
 620         }
 621
 622         if (of_property_read_u32_array(parent, "rockchip,ctrbits"
 623                 , &pm_ctrbits, 1)) {
 624                         PM_ERR("%s:get pm ctr error\n", __func__);
 625                         return;
 626         }
 627         PM_LOG("%s: pm_ctrbits =%x\n", __func__, pm_ctrbits);
 628         rkpm_set_ctrbits(pm_ctrbits);
 629
 630         clks_gating_suspend_init();
 631         rkpm_set_ops_prepare_finish(rkpm_prepare, rkpm_finish);
 632         rkpm_set_ops_plls(pm_plls_suspend, pm_plls_resume);
 633
 634         rkpm_set_ops_regs_pread(reg_pread);
 635         rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk
 636                 , &FUNC(ddr_suspend))
 637                 , fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_resume)));
 638
 639         rkpm_set_sram_ops_volt(fn_to_pie(rockchip_pie_chunk
 640                 , &FUNC(pwm_regulator_suspend))
 641                 , fn_to_pie(rockchip_pie_chunk, &FUNC(pwm_regulator_resume)));
 642
 643
 644         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk
 645                 , &FUNC(sram_printch)));
 646         rkpm_set_ops_printch(rk3036_ddr_printch);
 647 }
 648 #endif
 649
 650 static void __init rk3036_init_suspend(void)
 651 {
 652         pr_info("%s\n", __func__);
 653         rockchip_suspend_init();
 654         rkpm_pie_init();
 655         rk3036_suspend_init();
 656 }
 657
 658 static void __init rk3036_init_late(void)
 659 {
 660 #ifdef CONFIG_PM
 661         rk3036_init_suspend();
 662 #endif
 663 }
 664
 665 static void __init rk3036_reserve(void)
 666 {
 667         /* reserve memory for ION */
 668         rockchip_ion_reserve();
 669 }
 670
 671 static void rk3036_restart(char mode, const char *cmd)
 672 {
 673         u32 boot_flag, boot_mode;
 674
 675         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 676         /* for loader */
 677         writel_relaxed(boot_flag, RK_GRF_VIRT + RK3036_GRF_OS_REG4);
 678         /* for linux */
 679         writel_relaxed(boot_mode, RK_GRF_VIRT + RK3036_GRF_OS_REG5);
 680         dsb();
 681
 682         /* pll enter slow mode */
 683         writel_relaxed(0x30110000, RK_CRU_VIRT + RK3036_CRU_MODE_CON);
 684         dsb();
 685         writel_relaxed(0xeca8, RK_CRU_VIRT + RK3036_CRU_GLB_SRST_SND_VALUE);
 686         dsb();
 687 }
 688
 689 static const char *const rk3036_dt_compat[] __initconst = {
 690         "rockchip,rk3036",
 691         NULL,
 692 };
 693
 694 DT_MACHINE_START(RK3036_DT, "Rockchip RK3036")
 695         .dt_compat      = rk3036_dt_compat,
 696         .smp            = smp_ops(rockchip_smp_ops),
 697         .reserve        = rk3036_reserve,
 698         .map_io         = rk3036_dt_map_io,
 699         .init_time      = rk3036_dt_init_timer,
 700         .init_late      = rk3036_init_late,
 701         .reserve        = rk3036_reserve,
 702         .restart        = rk3036_restart,
 703 MACHINE_END