arch/arm/mach-rockchip/common.c

   1 /*
   2  * Copyright (C) 2013-2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/genalloc.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/of_fdt.h>
  23 #include <asm/cputype.h>
  24 #ifdef CONFIG_CACHE_L2X0
  25 #include <asm/hardware/cache-l2x0.h>
  26 #endif
  27 #include <linux/rockchip/common.h>
  28 #include <linux/rockchip/cpu_axi.h>
  29 #include <linux/rockchip/pmu.h>
  30 #include <linux/memblock.h>
  31 #include "loader.h"
  32 #include "sram.h"
  33
  34 static int __init rockchip_cpu_axi_init(void)
  35 {
  36         struct device_node *np, *gp, *cp;
  37         void __iomem *base;
  38
  39         np = of_find_compatible_node(NULL, NULL, "rockchip,cpu_axi_bus");
  40         if (!np)
  41                 return -ENODEV;
  42
  43 #define MAP(base) if (!base) base = of_iomap(cp, 0); if (!base) continue;
  44
  45         gp = of_get_child_by_name(np, "qos");
  46         if (gp) {
  47                 for_each_child_of_node(gp, cp) {
  48                         u32 priority[2], mode, bandwidth, saturation, extcontrol;
  49                         base = NULL;
  50 #ifdef DEBUG
  51                         {
  52                                 struct resource r;
  53                                 of_address_to_resource(cp, 0, &r);
  54                                 pr_debug("qos: %s [%x ~ %x]\n", cp->name, r.start, r.end);
  55                         }
  56 #endif
  57                         if (!of_property_read_u32_array(cp, "rockchip,priority", priority, ARRAY_SIZE(priority))) {
  58                                 MAP(base);
  59                                 CPU_AXI_SET_QOS_PRIORITY(priority[0], priority[1], base);
  60                                 pr_debug("qos: %s priority %x %x\n", cp->name, priority[0], priority[1]);
  61                         }
  62                         if (!of_property_read_u32(cp, "rockchip,mode", &mode)) {
  63                                 MAP(base);
  64                                 CPU_AXI_SET_QOS_MODE(mode, base);
  65                                 pr_debug("qos: %s mode %x\n", cp->name, mode);
  66                         }
  67                         if (!of_property_read_u32(cp, "rockchip,bandwidth", &bandwidth)) {
  68                                 MAP(base);
  69                                 CPU_AXI_SET_QOS_BANDWIDTH(bandwidth, base);
  70                                 pr_debug("qos: %s bandwidth %x\n", cp->name, bandwidth);
  71                         }
  72                         if (!of_property_read_u32(cp, "rockchip,saturation", &saturation)) {
  73                                 MAP(base);
  74                                 CPU_AXI_SET_QOS_SATURATION(saturation, base);
  75                                 pr_debug("qos: %s saturation %x\n", cp->name, saturation);
  76                         }
  77                         if (!of_property_read_u32(cp, "rockchip,extcontrol", &extcontrol)) {
  78                                 MAP(base);
  79                                 CPU_AXI_SET_QOS_EXTCONTROL(extcontrol, base);
  80                                 pr_debug("qos: %s extcontrol %x\n", cp->name, extcontrol);
  81                         }
  82                         if (base)
  83                                 iounmap(base);
  84                 }
  85         };
  86
  87         gp = of_get_child_by_name(np, "msch");
  88         if (gp) {
  89                 for_each_child_of_node(gp, cp) {
  90                         u32 val;
  91                         base = NULL;
  92 #ifdef DEBUG
  93                         {
  94                                 struct resource r;
  95                                 of_address_to_resource(cp, 0, &r);
  96                                 pr_debug("msch: %s [%x ~ %x]\n", cp->name, r.start, r.end);
  97                         }
  98 #endif
  99                         if (!of_property_read_u32(cp, "rockchip,read-latency", &val)) {
 100                                 MAP(base);
 101                                 writel_relaxed(val, base + 0x0014);     // memory scheduler read latency
 102                                 pr_debug("msch: %s read latency %x\n", cp->name, val);
 103                         }
 104                         if (base)
 105                                 iounmap(base);
 106                 }
 107         }
 108         dsb(sy);
 109
 110 #undef MAP
 111
 112         return 0;
 113 }
 114 early_initcall(rockchip_cpu_axi_init);
 115
 116 #ifdef CONFIG_CACHE_L2X0
 117 static int __init rockchip_pl330_l2_cache_init(void)
 118 {
 119         struct device_node *np;
 120         void __iomem *base;
 121         u32 aux[2] = { 0, ~0 }, prefetch, power;
 122
 123         if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9)
 124                 return -ENODEV;
 125
 126         np = of_find_compatible_node(NULL, NULL, "rockchip,pl310-cache");
 127         if (!np)
 128                 return -ENODEV;
 129
 130         base = of_iomap(np, 0);
 131         if (!base)
 132                 return -EINVAL;
 133
 134         if (!of_property_read_u32(np, "rockchip,prefetch-ctrl", &prefetch)) {
 135                 /* L2X0 Prefetch Control */
 136                 writel_relaxed(prefetch, base + L2X0_PREFETCH_CTRL);
 137                 pr_debug("l2c: prefetch %x\n", prefetch);
 138         }
 139
 140         if (!of_property_read_u32(np, "rockchip,power-ctrl", &power)) {
 141                 /* L2X0 Power Control */
 142                 writel_relaxed(power, base + L2X0_POWER_CTRL);
 143                 pr_debug("l2c: power %x\n", power);
 144         }
 145
 146         iounmap(base);
 147
 148         of_property_read_u32_array(np, "rockchip,aux-ctrl", aux, ARRAY_SIZE(aux));
 149         pr_debug("l2c: aux %08x mask %08x\n", aux[0], aux[1]);
 150
 151         l2x0_of_init(aux[0], aux[1]);
 152
 153         return 0;
 154 }
 155 early_initcall(rockchip_pl330_l2_cache_init);
 156 #endif
 157
 158 struct gen_pool *rockchip_sram_pool = NULL;
 159 struct pie_chunk *rockchip_pie_chunk = NULL;
 160 void *rockchip_sram_virt = NULL;
 161 size_t rockchip_sram_size = 0;
 162 char *rockchip_sram_stack = NULL;
 163
 164 #ifdef CONFIG_PIE
 165 int __init rockchip_pie_init(void)
 166 {
 167         struct device_node *np;
 168
 169         np = of_find_node_by_path("/");
 170         if (!np)
 171                 return -ENODEV;
 172
 173         rockchip_sram_pool = of_get_named_gen_pool(np, "rockchip,sram", 0);
 174         if (!rockchip_sram_pool) {
 175                 pr_err("%s: failed to get sram pool\n", __func__);
 176                 return -ENODEV;
 177         }
 178         rockchip_sram_size = gen_pool_size(rockchip_sram_pool);
 179
 180         return 0;
 181 }
 182 #endif
 183
 184 static bool is_panic = false;
 185 extern void console_disable_suspend(void);
 186
 187 static int panic_event(struct notifier_block *this, unsigned long event, void *ptr)
 188 {
 189 #if CONFIG_RK_DEBUG_UART >= 0
 190         console_disable_suspend();
 191 #endif
 192         is_panic = true;
 193         return NOTIFY_DONE;
 194 }
 195
 196 static struct notifier_block panic_block = {
 197         .notifier_call  = panic_event,
 198 };
 199
 200 static int boot_mode;
 201
 202 int rockchip_boot_mode(void)
 203 {
 204         return boot_mode;
 205 }
 206 EXPORT_SYMBOL(rockchip_boot_mode);
 207
 208 static inline const char *boot_flag_name(u32 flag)
 209 {
 210         flag -= SYS_KERNRL_REBOOT_FLAG;
 211         switch (flag) {
 212         case BOOT_NORMAL: return "NORMAL";
 213         case BOOT_LOADER: return "LOADER";
 214         case BOOT_MASKROM: return "MASKROM";
 215         case BOOT_RECOVER: return "RECOVER";
 216         case BOOT_NORECOVER: return "NORECOVER";
 217         case BOOT_SECONDOS: return "SECONDOS";
 218         case BOOT_WIPEDATA: return "WIPEDATA";
 219         case BOOT_WIPEALL: return "WIPEALL";
 220         case BOOT_CHECKIMG: return "CHECKIMG";
 221         case BOOT_FASTBOOT: return "FASTBOOT";
 222         case BOOT_CHARGING: return "CHARGING";
 223         default: return "";
 224         }
 225 }
 226
 227 static inline const char *boot_mode_name(u32 mode)
 228 {
 229         switch (mode) {
 230         case BOOT_MODE_NORMAL: return "NORMAL";
 231         case BOOT_MODE_FACTORY2: return "FACTORY2";
 232         case BOOT_MODE_RECOVERY: return "RECOVERY";
 233         case BOOT_MODE_CHARGE: return "CHARGE";
 234         case BOOT_MODE_POWER_TEST: return "POWER_TEST";
 235         case BOOT_MODE_OFFMODE_CHARGING: return "OFFMODE_CHARGING";
 236         case BOOT_MODE_REBOOT: return "REBOOT";
 237         case BOOT_MODE_PANIC: return "PANIC";
 238         case BOOT_MODE_WATCHDOG: return "WATCHDOG";
 239         case BOOT_MODE_TSADC: return "TSADC";
 240         default: return "";
 241         }
 242 }
 243
 244 void __init rockchip_boot_mode_init(u32 flag, u32 mode)
 245 {
 246         boot_mode = mode;
 247         if (mode || ((flag & 0xff) && ((flag & 0xffffff00) == SYS_KERNRL_REBOOT_FLAG)))
 248                 printk("Boot mode: %s (%d) flag: %s (0x%08x)\n", boot_mode_name(mode), mode, boot_flag_name(flag), flag);
 249         atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
 250 }
 251
 252 void rockchip_restart_get_boot_mode(const char *cmd, u32 *flag, u32 *mode)
 253 {
 254         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_NORMAL;
 255         *mode = BOOT_MODE_REBOOT;
 256
 257         if (cmd) {
 258                 if (!strcmp(cmd, "loader") || !strcmp(cmd, "bootloader"))
 259                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_LOADER;
 260                 else if(!strcmp(cmd, "recovery"))
 261                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_RECOVER;
 262                 else if (!strcmp(cmd, "fastboot"))
 263                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_FASTBOOT;
 264                 else if (!strcmp(cmd, "charge")) {
 265                         *flag = SYS_LOADER_REBOOT_FLAG + BOOT_CHARGING;
 266                         *mode = BOOT_MODE_CHARGE;
 267                 }
 268         } else {
 269                 if (is_panic)
 270                         *mode = BOOT_MODE_PANIC;
 271         }
 272 }
 273
 274 struct rockchip_pmu_operations rockchip_pmu_ops;
 275 void (*ddr_bandwidth_get)(struct ddr_bw_info *ddr_bw_ch0,
 276                           struct ddr_bw_info *ddr_bw_ch1);
 277 int (*ddr_change_freq)(uint32_t nMHz) = NULL;
 278 long (*ddr_round_rate)(uint32_t nMHz) = NULL;
 279 void (*ddr_set_auto_self_refresh)(bool en) = NULL;
 280 int (*ddr_recalc_rate)(void) = NULL;
 281
 282 extern struct ion_platform_data ion_pdata;
 283 extern void __init ion_reserve(struct ion_platform_data *data);
 284 extern int __init rockchip_ion_find_heap(unsigned long node,
 285                                 const char *uname, int depth, void *data);
 286 void __init rockchip_ion_reserve(void)
 287 {
 288 #ifdef CONFIG_ION_ROCKCHIP
 289         printk("%s\n", __func__);
 290         of_scan_flat_dt(rockchip_ion_find_heap, (void*)&ion_pdata);
 291         ion_reserve(&ion_pdata);
 292 #endif
 293 }
 294
 295 bool rockchip_jtag_enabled = false;
 296 static int __init rockchip_jtag_enable(char *__unused)
 297 {
 298         rockchip_jtag_enabled = true;
 299         printk("rockchip jtag enabled\n");
 300         return 1;
 301 }
 302 __setup("rockchip_jtag", rockchip_jtag_enable);
 303
 304 phys_addr_t uboot_logo_base=0;
 305 phys_addr_t uboot_logo_size=0;
 306 phys_addr_t uboot_logo_offset=0;
 307
 308 void __init rockchip_uboot_mem_reserve(void)
 309 {
 310         if (uboot_logo_size==0)
 311                 return;
 312
 313         if (!memblock_is_region_reserved(uboot_logo_base, uboot_logo_size)
 314             && !memblock_reserve(uboot_logo_base, uboot_logo_size)){
 315                 pr_info("%s: reserve %pa@%pa for uboot logo\n", __func__,
 316                         &uboot_logo_size, &uboot_logo_base);
 317         } else {
 318                 pr_err("%s: reserve of %pa@%pa failed\n", __func__,
 319                        &uboot_logo_size, &uboot_logo_base);
 320         }
 321 }
 322
 323 static int __init rockchip_uboot_logo_setup(char *p)
 324 {
 325         char *endp;
 326
 327         uboot_logo_size = memparse(p, &endp);
 328         if (*endp == '@') {
 329                 uboot_logo_base = memparse(endp + 1, &endp);
 330                 if (*endp == ':') {
 331                         uboot_logo_offset = memparse(endp + 1, NULL);
 332                 }
 333         }
 334
 335         pr_info("%s: mem: %pa@%pa, offset:%pa\n", __func__,
 336                 &uboot_logo_size, &uboot_logo_base, &uboot_logo_offset);
 337
 338         return 0;
 339 }
 340 early_param("uboot_logo", rockchip_uboot_logo_setup);
 341
 342 static int __init rockchip_uboot_mem_late_init(void)
 343 {
 344         phys_addr_t addr = 0;
 345         phys_addr_t end = 0;
 346
 347         if (uboot_logo_size) {
 348                 addr = PAGE_ALIGN(uboot_logo_base);
 349                 end = (uboot_logo_base+uboot_logo_size)&PAGE_MASK;
 350
 351                 pr_info("%s: Freeing uboot logo memory: %pa@%pa\n", __func__,
 352                         &uboot_logo_size, &uboot_logo_base);
 353
 354                 memblock_free(uboot_logo_base, uboot_logo_size);
 355
 356                 for (; addr < end; addr += PAGE_SIZE)
 357                         free_reserved_page(pfn_to_page(addr >> PAGE_SHIFT));
 358         }
 359
 360         return 0;
 361 }
 362 late_initcall(rockchip_uboot_mem_late_init);