Programming Languages Research Group: Git

2012-10-08	Andrew Trick	misched: remove forceUnitLatencies. Defaults are handled...	commit \| commitdiff \| tree
2012-10-08	Andrew Trick	misched: avoid scheduling an instruction twice.	commit \| commitdiff \| tree
2012-10-04	Andrew Trick	Enable -schedmodel, but prefer itineraries until we...	commit \| commitdiff \| tree
2012-10-03	Andrew Trick	Added instregex support to TableGen subtarget emitter.	commit \| commitdiff \| tree
2012-10-03	Andrew Trick	TableGen subtarget emitter, nearly first class support...	commit \| commitdiff \| tree
2012-10-03	Andrew Trick	Cleanup TableGen subtarget emitter.	commit \| commitdiff \| tree
2012-09-22	Andrew Trick	Machine Model (-schedmodel only). Added SchedAliases.	commit \| commitdiff \| tree
2012-09-21	Andrew Trick	Cortex-A9 latency fixes (w/ -schedmodel only).	commit \| commitdiff \| tree
2012-09-20	Andrew Trick	Fix function names in coding style examples	commit \| commitdiff \| tree
2012-09-20	Andrew Trick	Fix static function names in CodingStandards examples.	commit \| commitdiff \| tree
2012-09-19	Andrew Trick	Silence -Wnon-virtual-dtor in llvm-stress.	commit \| commitdiff \| tree
2012-09-19	Andrew Trick	SchedMachineModel: compress the CPU's WriteLatencyTable.	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	comment typo	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	TargetSchedule: cleanup computeOperandLatency logic...	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	misched: Make ScheduleDAGInstrs use the TargetSchedule...	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	LSR critical edge splitting fix for PR13756.	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	Replaced ReInitMCSubtargetInfo with InitMCProcessor.	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	Let NULL slip through again.	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	TargetSchedModel API. Implement latency lookup, disabled.	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	comment typo	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	TableGen subtarget emitter. Use getSchedClassIdx.	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	TableGen subtarget emitter. Generate resolveSchedClass...	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	TableGen subtarget emitter. Remove unnecessary header...	commit \| commitdiff \| tree
2012-09-18	Andrew Trick	TableGen subtarget emitter. Initialize MCSubtargetInfo...	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	Backout the wrong subtarget emitter fix	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	Fix release build after reverting	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	Revert r164061-r164067. Most of the new subtarget emitter.	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	Don't use NULL as a fake keyword	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	InitMCProcessor	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	TargetSchedModel API. Implement latency lookup, disabled.	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	comment typo	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	TableGen subtarget emitter. Use getSchedClassIdx.	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	TableGen subtarget emitter. Generate resolveSchedClass...	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	TableGen subtarget emitter. Initialize MCSubtargetInfo...	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	TableGen subtarget emitter. Format and emit data tables...	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	TableGen subtarget emitter. Generate data tables for...	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	TableGen subtarget emitter. Emit processor resources...	commit \| commitdiff \| tree
2012-09-17	Andrew Trick	TableGen subtarget parser: Add getProcResourcesIdx().	commit \| commitdiff \| tree
2012-09-16	Andrew Trick	Guard fields by NDEBUG until they get used in the release...	commit \| commitdiff \| tree
2012-09-15	Andrew Trick	TableGen subtarget parser. Handle new machine model.	commit \| commitdiff \| tree
2012-09-15	Andrew Trick	TableGen subtarget parser. Handle new machine model.	commit \| commitdiff \| tree
2012-09-15	Andrew Trick	TableGen subtarget parser. Handle new machine model.	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	comment typo	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	TargetSchedModel interface. To be implemented...	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	Define MC data tables for the new scheduling machine...	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	Implement getNumLDMAddresses and expose through ARMBaseInstr...	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	Cortex-A9 instruction-level scheduling machine model.	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	misched: add a hook for custom DAG postprocessing.	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	misched: Generic tablegen classes for the new machine...	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	comment	commit \| commitdiff \| tree
2012-09-14	Andrew Trick	comment	commit \| commitdiff \| tree
2012-09-11	Andrew Trick	Reorganize MachineScheduler interfaces and publish...	commit \| commitdiff \| tree
2012-09-11	Andrew Trick	Remove unused declaration	commit \| commitdiff \| tree
2012-09-08	Andrew Trick	Remove an incorrect assert during branch weight propagation.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	Preserve branch profile metadata during switch formation.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	Cleanup sloppy code. Jakob's review.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	Fix a nondeterminism in the ARM assembler.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	Fix ARM vector copies of overlapping register tuples.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	cleanup	commit \| commitdiff \| tree
2012-08-23	Andrew Trick	Simplify the computeOperandLatency API.	commit \| commitdiff \| tree
2012-08-08	Andrew Trick	Added MispredictPenalty to SchedMachineModel.	commit \| commitdiff \| tree
2012-08-08	Andrew Trick	Minor cleanup of defaultDefLatency API	commit \| commitdiff \| tree
2012-08-08	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-08-07	Andrew Trick	Allow x86 subtargets to use the GenericModel defined...	commit \| commitdiff \| tree
2012-07-30	Andrew Trick	Use the latest MachineRegisterInfo APIs. No functionality.	commit \| commitdiff \| tree
2012-07-30	Andrew Trick	Added MachineRegisterInfo::hasOneDef()	commit \| commitdiff \| tree
2012-07-30	Andrew Trick	Inline MachineRegisterInfo::hasOneUse	commit \| commitdiff \| tree
2012-07-28	Andrew Trick	Reenable a basic SSA DAG builder optimization.	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	Fix ARMTargetLowering::isLegalAddImmediate to consider...	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	Added unit test for PR13361: LSR + SCEV "hangs" on...	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	SCEVTraversal: Add a visited set.	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	indvars: drive by heuristics fix.	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	indvars: Linear function test replace should avoid...	commit \| commitdiff \| tree
2012-07-17	Andrew Trick	Reapply r160340. LSR: Limit CollectSubexprs.	commit \| commitdiff \| tree
2012-07-17	Andrew Trick	Revert "LSR: try not to blow up solving combinatorial...	commit \| commitdiff \| tree
2012-07-17	Andrew Trick	LSR: try not to blow up solving combinatorial problems...	commit \| commitdiff \| tree
2012-07-13	Andrew Trick	LSR Fix: check SCEV expression safety before expansion.	commit \| commitdiff \| tree
2012-07-13	Andrew Trick	IVUsers should only generate SCEV's for values that...	commit \| commitdiff \| tree
2012-07-13	Andrew Trick	Factor SCEV traversal code so I can use it elsewhere...	commit \| commitdiff \| tree
2012-07-09	Andrew Trick	Machine model: allow itineraries to be shared by different...	commit \| commitdiff \| tree
2012-07-09	Andrew Trick	indentation	commit \| commitdiff \| tree
2012-07-07	Andrew Trick	I'm introducing a new machine model to simultaneously...	commit \| commitdiff \| tree
2012-07-07	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-07-07	Andrew Trick	Tweak spelling.	commit \| commitdiff \| tree
2012-07-02	Andrew Trick	misched: allow NULL InstrItineraries.	commit \| commitdiff \| tree
2012-07-02	Andrew Trick	Revert accidental checkin.	commit \| commitdiff \| tree
2012-07-02	Andrew Trick	Reapply "Make NumMicroOps a variable in the subtarget...	commit \| commitdiff \| tree
2012-06-29	Andrew Trick	Revert "Make NumMicroOps a variable in the subtarget...	commit \| commitdiff \| tree
2012-06-29	Andrew Trick	misched: avoid scheduling instructions that can't be...	commit \| commitdiff \| tree
2012-06-29	Andrew Trick	misched: count micro-ops toward the issue limit.	commit \| commitdiff \| tree
2012-06-29	Andrew Trick	Make NumMicroOps a variable in the subtarget's instruction...	commit \| commitdiff \| tree
2012-06-26	Andrew Trick	Enable the new LoopInfo algorithm by default.	commit \| commitdiff \| tree
2012-06-26	Andrew Trick	Remove unnecessary FIXME	commit \| commitdiff \| tree
2012-06-22	Andrew Trick	Use "NoItineraries" for processors with no itineraries.	commit \| commitdiff \| tree
2012-06-22	Andrew Trick	ARM scheduling fix: don't guess at implicit operand...	commit \| commitdiff \| tree
2012-06-22	Andrew Trick	ARM scheduling fix: compute predicated implicit use...	commit \| commitdiff \| tree
2012-06-20	Andrew Trick	Restructure PopulateLoopsDFS::insertIntoLoop.	commit \| commitdiff \| tree
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C/C++ LLVM-based compilers that forbids OOTA behaviors

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