const MachineInstr *MI = SU->getInstr();
unsigned Reg = MI->getOperand(OperIdx).getReg();
- // SSA defs do not have output/anti dependencies.
+ // Singly defined vregs do not have output/anti dependencies.
// The current operand is a def, so we have at least one.
- //
- // FIXME: This optimization is disabled pending PR13112.
- //if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
- // return;
+ // Check here if there are any others...
+ if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
+ return;
// Add output dependence to the next nearest def of this vreg.
//