TargetSchedModel interface. To be implemented...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163934 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/TargetSchedule.h b/include/llvm/CodeGen/TargetSchedule.h
new file mode 100644 (file)
index 0000000..4cf6f77
--- /dev/null
+++ b/include/llvm/CodeGen/TargetSchedule.h
@@ -0,0 +1,63 @@
+//===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines a wrapper around MCSchedModel that allows the interface to
+// benefit from information currently only available in TargetInstrInfo.
+// Ideally, the scheduling interface would be fully defined in the MC layter.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TARGET_TARGETSCHEDMODEL_H
+#define LLVM_TARGET_TARGETSCHEDMODEL_H
+
+#include "llvm/MC/MCSchedule.h"
+#include "llvm/MC/MCInstrItineraries.h"
+
+namespace llvm {
+
+class TargetRegisterInfo;
+class TargetSubtargetInfo;
+class TargetInstrInfo;
+class MachineInstr;
+
+/// Provide an instruction scheduling machine model to CodeGen passes.
+class TargetSchedModel {
+  // For efficiency, hold a copy of the statically defined MCSchedModel for this
+  // processor.
+  MCSchedModel SchedModel;
+  InstrItineraryData InstrItins;
+  const TargetSubtargetInfo *STI;
+  const TargetInstrInfo *TII;
+public:
+  TargetSchedModel(): STI(0), TII(0) {}
+
+  void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
+            const TargetInstrInfo *tii);
+
+  const TargetInstrInfo *getInstrInfo() const { return TII; }
+
+  /// Return true if this machine model includes an instruction-level scheduling
+  /// model. This is more detailed than the course grain IssueWidth and default
+  /// latency properties, but separate from the per-cycle itinerary data.
+  bool hasInstrSchedModel() const {
+    return SchedModel.hasInstrSchedModel();
+  }
+
+  /// Return true if this machine model includes cycle-to-cycle itinerary
+  /// data. This models scheduling at each stage in the processor pipeline.
+  bool hasInstrItineraries() const {
+    return SchedModel.hasInstrItineraries();
+  }
+
+  unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
+};
+
+} // namespace llvm
+
+#endif

diff --git a/include/llvm/MC/MCSchedule.h b/include/llvm/MC/MCSchedule.h
index dfab1305acfce4c069bdb4507831ccc1927b3b33..99afb10ebd36feca1b70dcb8da7e2adc4d3ef103 100644 (file)
--- a/include/llvm/MC/MCSchedule.h
+++ b/include/llvm/MC/MCSchedule.h
@@ -199,6 +199,8 @@ public:
     MispredictPenalty(mp), ProcID(0), ProcResourceTable(0),
     SchedClassTable(0), InstrItineraries(ii) {}
 
+  unsigned getProcessorID() const { return ProcID; }
+
   /// Does this machine model include instruction-level scheduling.
   bool hasInstrSchedModel() const {
     return SchedClassTable;

diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h
index 71581337a8b3e1a06bfc9f104a9728dc2663c852..d1d40476aaf54f6eaa695e86e7990b0483df1ae5 100644 (file)
--- a/include/llvm/MC/MCSubtargetInfo.h
+++ b/include/llvm/MC/MCSubtargetInfo.h
@@ -118,6 +118,9 @@ public:
   /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
   ///
   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
+
+  /// Initialize an InstrItineraryData instance.
+  void initInstrItins(InstrItineraryData &InstrItins) const;
 };
 
 } // End llvm namespace

diff --git a/lib/CodeGen/CMakeLists.txt b/lib/CodeGen/CMakeLists.txt
index 386509b702ed40a7b7fbb00fe48742e6160fc7e3..96c82c06692e3acd8ac361aef48e72a7fdb4e76d 100644 (file)
--- a/lib/CodeGen/CMakeLists.txt
+++ b/lib/CodeGen/CMakeLists.txt
@@ -102,6 +102,7 @@ add_llvm_library(LLVMCodeGen
   TargetInstrInfoImpl.cpp
   TargetLoweringObjectFileImpl.cpp
   TargetOptionsImpl.cpp
+  TargetSchedule.cpp
   TwoAddressInstructionPass.cpp
   UnreachableBlockElim.cpp
   VirtRegMap.cpp

diff --git a/lib/CodeGen/TargetSchedule.cpp b/lib/CodeGen/TargetSchedule.cpp
new file mode 100644 (file)
index 0000000..42effb4
--- /dev/null
+++ b/lib/CodeGen/TargetSchedule.cpp
@@ -0,0 +1,32 @@
+//===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a wrapper around MCSchedModel that allows the interface
+// to benefit from information currently only available in TargetInstrInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/TargetSchedule.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/Support/CommandLine.h"
+
+using namespace llvm;
+
+static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(false),
+  cl::desc("Use TargetSchedModel for latency lookup"));
+
+void TargetSchedModel::init(const MCSchedModel &sm,
+                            const TargetSubtargetInfo *sti,
+                            const TargetInstrInfo *tii) {
+  SchedModel = sm;
+  STI = sti;
+  TII = tii;
+  STI->initInstrItins(InstrItins);
+}

diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp
index 98206596952dcee8f2ab0cdcca967641fc2e6f5e..47735a492de647e93b834c7a24c12ef506fc0191 100644 (file)
--- a/lib/MC/MCSubtargetInfo.cpp
+++ b/lib/MC/MCSubtargetInfo.cpp
@@ -101,3 +101,9 @@ MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
   const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
   return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
 }
+
+/// Initialize an InstrItineraryData instance.
+void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
+  InstrItins =
+    InstrItineraryData(0, Stages, OperandCycles, ForwardingPaths);
+}