Use "NoItineraries" for processors with no itineraries.

This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td
index 31e8b17f25823b28c97165dd5ba514cf78ff0f39..e22e67cdac298f1c70e11a1393dd6b5a47b9ceff 100644 (file)
--- a/include/llvm/Target/TargetSchedule.td
+++ b/include/llvm/Target/TargetSchedule.td
@@ -133,7 +133,8 @@ class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp,
 }
 
 // NoItineraries - A marker that can be used by processors without schedule
-// info.
+// info. Subtargets using NoItineraries can bypass the scheduler's
+// expensive HazardRecognizer because no reservation table is needed.
 def NoItineraries : ProcessorItineraries<[], [], []>;
 
 // Processor itineraries with non-unit issue width. This allows issue

diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 9b0cb0c9e57504cce8188fee6f44c57202bb1b01..d332d20f80d79e18f179a0f9ad19c08c2a60666b 100644 (file)
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -141,7 +141,7 @@ def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
                                     FeatureAvoidPartialCPSR]>;
 
 class ProcNoItin<string Name, list<SubtargetFeature> Features>
- : Processor<Name, GenericItineraries, Features>;
+ : Processor<Name, NoItineraries, Features>;
 
 // V4 Processors.
 def : ProcNoItin<"generic",         []>;

diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index 45486fd0b6dd2a497c6b7447652fede7b51b6656..b9a07f1ee68ee8a08682f70114705f3e48c338fd 100644 (file)
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -258,8 +258,6 @@ def IIC_VTBX4      : InstrItinClass;
 //===----------------------------------------------------------------------===//
 // Processor instruction itineraries.
 
-def GenericItineraries : ProcessorItineraries<[], [], []>;
-
 include "ARMScheduleV6.td"
 include "ARMScheduleA8.td"
 include "ARMScheduleA9.td"

diff --git a/lib/Target/MBlaze/MBlaze.td b/lib/Target/MBlaze/MBlaze.td
index b4edff0709e6c4c2a3b2a98d3940f2a9241b2167..c2888553c5e38de893a212aa632bcf5dd5d4fb4a 100644 (file)
--- a/lib/Target/MBlaze/MBlaze.td
+++ b/lib/Target/MBlaze/MBlaze.td
@@ -50,7 +50,7 @@ def FeatureSqrt        : SubtargetFeature<"sqrt", "HasSqrt", "true",
 // MBlaze processors supported.
 //===----------------------------------------------------------------------===//
 
-def : Processor<"mblaze",  MBlazeGenericItineraries, []>;
+def : Processor<"mblaze",  NoItineraries, []>;
 def : Processor<"mblaze3", MBlazePipe3Itineraries, []>;
 def : Processor<"mblaze5", MBlazePipe5Itineraries, []>;
 

diff --git a/lib/Target/MBlaze/MBlazeSchedule.td b/lib/Target/MBlaze/MBlazeSchedule.td
index 4a3ae5fc14704af5365d01ce23dfbc764a1ce277..cd5691ce644fd8462d7f3f17f06739bf151ef1c0 100644 (file)
--- a/lib/Target/MBlaze/MBlazeSchedule.td
+++ b/lib/Target/MBlaze/MBlazeSchedule.td
@@ -39,11 +39,6 @@ def IIC_BRl    : InstrItinClass;
 def IIC_WDC    : InstrItinClass;
 def IIC_Pseudo : InstrItinClass;
 
-//===----------------------------------------------------------------------===//
-// MBlaze generic instruction itineraries.
-//===----------------------------------------------------------------------===//
-def MBlazeGenericItineraries : ProcessorItineraries<[], [], []>;
-
 //===----------------------------------------------------------------------===//
 // MBlaze instruction itineraries for three stage pipeline.
 //===----------------------------------------------------------------------===//

diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index 870b8ad0b8b5fef0f54dd9e024cacc7938735684..19b0550b994ffc7efaaeec26820e521fa61e796e 100644 (file)
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -422,15 +422,18 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
     // Get processor itinerary name
     const std::string &Name = Proc->getName();
 
-    // Skip default
-    if (Name == "NoItineraries") continue;
-
-    // Create and expand processor itinerary to cover all itinerary classes
-    std::vector<InstrItinerary> ItinList;
-    ItinList.resize(NItinClasses);
-
     // Get itinerary data list
     std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
+    std::vector<InstrItinerary> ItinList;
+
+    // Add an empty itinerary.
+    if (ItinDataList.empty()) {
+      ProcList.push_back(ItinList);
+      continue;
+    }
+
+    // Expand processor itinerary to cover all itinerary classes
+    ItinList.resize(NItinClasses);
 
     // For each itinerary data
     for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
@@ -559,8 +562,6 @@ EmitProcessorData(raw_ostream &OS,
     const std::string &Name = Itin->getName();
 
     // Skip default
-    if (Name == "NoItineraries") continue;
-
     // Begin processor itinerary properties
     OS << "\n";
     OS << "static const llvm::InstrItineraryProps " << Name << "Props(\n";
@@ -570,42 +571,45 @@ EmitProcessorData(raw_ostream &OS,
     EmitItineraryProp(OS, Itin, "HighLatency", ' ');
     OS << ");\n";
 
-    // Begin processor itinerary table
-    OS << "\n";
-    OS << "static const llvm::InstrItinerary " << Name << "Entries"
-       << "[] = {\n";
-
     // For each itinerary class
     std::vector<InstrItinerary> &ItinList = *ProcListIter++;
-    assert(ItinList.size() == ItinClassList.size() && "bad itinerary");
-    for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
-      InstrItinerary &Intinerary = ItinList[j];
-
-      // Emit in the form of
-      // { firstStage, lastStage, firstCycle, lastCycle } // index
-      if (Intinerary.FirstStage == 0) {
-        OS << "  { 1, 0, 0, 0, 0 }";
-      } else {
-        OS << "  { " <<
-          Intinerary.NumMicroOps << ", " <<
-          Intinerary.FirstStage << ", " <<
-          Intinerary.LastStage << ", " <<
-          Intinerary.FirstOperandCycle << ", " <<
-          Intinerary.LastOperandCycle << " }";
-      }
+    if (!ItinList.empty()) {
+      assert(ItinList.size() == ItinClassList.size() && "bad itinerary");
 
-      OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n";
+      // Begin processor itinerary table
+      OS << "\n";
+      OS << "static const llvm::InstrItinerary " << Name << "Entries"
+         << "[] = {\n";
+
+      for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
+        InstrItinerary &Intinerary = ItinList[j];
+
+        // Emit in the form of
+        // { firstStage, lastStage, firstCycle, lastCycle } // index
+        if (Intinerary.FirstStage == 0) {
+          OS << "  { 1, 0, 0, 0, 0 }";
+        } else {
+          OS << "  { " <<
+            Intinerary.NumMicroOps << ", " <<
+            Intinerary.FirstStage << ", " <<
+            Intinerary.LastStage << ", " <<
+            Intinerary.FirstOperandCycle << ", " <<
+            Intinerary.LastOperandCycle << " }";
+        }
+        OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n";
+      }
+      // End processor itinerary table
+      OS << "  { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n";
+      OS << "};\n";
     }
-
-    // End processor itinerary table
-    OS << "  { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n";
-    OS << "};\n";
-
     OS << '\n';
     OS << "static const llvm::InstrItinerarySubtargetValue "
        << Name << " = {\n";
     OS << "  &" << Name << "Props,\n";
-    OS << "  " << Name << "Entries\n";
+    if (ItinList.empty())
+      OS << "  0\n";
+    else
+      OS << "  " << Name << "Entries\n";
     OS << "};\n";
   }
 }