Programming Languages Research Group: Git

2012-09-11	Andrew Trick	Reorganize MachineScheduler interfaces and publish...	commit \| commitdiff \| tree
2012-09-11	Andrew Trick	Remove unused declaration	commit \| commitdiff \| tree
2012-09-08	Andrew Trick	Remove an incorrect assert during branch weight propagation.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	Preserve branch profile metadata during switch formation.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	Cleanup sloppy code. Jakob's review.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	Fix a nondeterminism in the ARM assembler.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	Fix ARM vector copies of overlapping register tuples.	commit \| commitdiff \| tree
2012-08-29	Andrew Trick	cleanup	commit \| commitdiff \| tree
2012-08-23	Andrew Trick	Simplify the computeOperandLatency API.	commit \| commitdiff \| tree
2012-08-08	Andrew Trick	Added MispredictPenalty to SchedMachineModel.	commit \| commitdiff \| tree
2012-08-08	Andrew Trick	Minor cleanup of defaultDefLatency API	commit \| commitdiff \| tree
2012-08-08	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-08-07	Andrew Trick	Allow x86 subtargets to use the GenericModel defined...	commit \| commitdiff \| tree
2012-07-30	Andrew Trick	Use the latest MachineRegisterInfo APIs. No functionality.	commit \| commitdiff \| tree
2012-07-30	Andrew Trick	Added MachineRegisterInfo::hasOneDef()	commit \| commitdiff \| tree
2012-07-30	Andrew Trick	Inline MachineRegisterInfo::hasOneUse	commit \| commitdiff \| tree
2012-07-28	Andrew Trick	Reenable a basic SSA DAG builder optimization.	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	Fix ARMTargetLowering::isLegalAddImmediate to consider...	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	Added unit test for PR13361: LSR + SCEV "hangs" on...	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	SCEVTraversal: Add a visited set.	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	indvars: drive by heuristics fix.	commit \| commitdiff \| tree
2012-07-18	Andrew Trick	indvars: Linear function test replace should avoid...	commit \| commitdiff \| tree
2012-07-17	Andrew Trick	Reapply r160340. LSR: Limit CollectSubexprs.	commit \| commitdiff \| tree
2012-07-17	Andrew Trick	Revert "LSR: try not to blow up solving combinatorial...	commit \| commitdiff \| tree
2012-07-17	Andrew Trick	LSR: try not to blow up solving combinatorial problems...	commit \| commitdiff \| tree
2012-07-13	Andrew Trick	LSR Fix: check SCEV expression safety before expansion.	commit \| commitdiff \| tree
2012-07-13	Andrew Trick	IVUsers should only generate SCEV's for values that...	commit \| commitdiff \| tree
2012-07-13	Andrew Trick	Factor SCEV traversal code so I can use it elsewhere...	commit \| commitdiff \| tree
2012-07-09	Andrew Trick	Machine model: allow itineraries to be shared by different...	commit \| commitdiff \| tree
2012-07-09	Andrew Trick	indentation	commit \| commitdiff \| tree
2012-07-07	Andrew Trick	I'm introducing a new machine model to simultaneously...	commit \| commitdiff \| tree
2012-07-07	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-07-07	Andrew Trick	Tweak spelling.	commit \| commitdiff \| tree
2012-07-02	Andrew Trick	misched: allow NULL InstrItineraries.	commit \| commitdiff \| tree
2012-07-02	Andrew Trick	Revert accidental checkin.	commit \| commitdiff \| tree
2012-07-02	Andrew Trick	Reapply "Make NumMicroOps a variable in the subtarget...	commit \| commitdiff \| tree
2012-06-29	Andrew Trick	Revert "Make NumMicroOps a variable in the subtarget...	commit \| commitdiff \| tree
2012-06-29	Andrew Trick	misched: avoid scheduling instructions that can't be...	commit \| commitdiff \| tree
2012-06-29	Andrew Trick	misched: count micro-ops toward the issue limit.	commit \| commitdiff \| tree
2012-06-29	Andrew Trick	Make NumMicroOps a variable in the subtarget's instruction...	commit \| commitdiff \| tree
2012-06-26	Andrew Trick	Enable the new LoopInfo algorithm by default.	commit \| commitdiff \| tree
2012-06-26	Andrew Trick	Remove unnecessary FIXME	commit \| commitdiff \| tree
2012-06-22	Andrew Trick	Use "NoItineraries" for processors with no itineraries.	commit \| commitdiff \| tree
2012-06-22	Andrew Trick	ARM scheduling fix: don't guess at implicit operand...	commit \| commitdiff \| tree
2012-06-22	Andrew Trick	ARM scheduling fix: compute predicated implicit use...	commit \| commitdiff \| tree
2012-06-20	Andrew Trick	Restructure PopulateLoopsDFS::insertIntoLoop.	commit \| commitdiff \| tree
2012-06-20	Andrew Trick	Add "extern template" declarations now that we use...	commit \| commitdiff \| tree
2012-06-20	Andrew Trick	A new algorithm for computing LoopInfo. Temporarily...	commit \| commitdiff \| tree
2012-06-20	Andrew Trick	Move the implementation of LoopInfo into LoopInfoImpl.h.	commit \| commitdiff \| tree
2012-06-15	Andrew Trick	Unit test for LSR kind=Special fix: r158536.	commit \| commitdiff \| tree
2012-06-15	Andrew Trick	LSR: fix expansion of scaled reg in non-address type...	commit \| commitdiff \| tree
2012-06-15	Andrew Trick	LSR fix: "Special" users are just like "Basic" users...	commit \| commitdiff \| tree
2012-06-14	Andrew Trick	misched: disable SSA check pending PR13112.	commit \| commitdiff \| tree
2012-06-13	Andrew Trick	sched: fix latency of memory dependence chain edges...	commit \| commitdiff \| tree
2012-06-13	Andrew Trick	sched: Avoid trivially redundant DAG edges. Take the...	commit \| commitdiff \| tree
2012-06-11	Andrew Trick	misched: When querying RegisterPressureTracker, always...	commit \| commitdiff \| tree
2012-06-11	Andrew Trick	misched: regpressure getMaxPressureDelta, revert accidental...	commit \| commitdiff \| tree
2012-06-09	Andrew Trick	Register pressure: added getPressureAfterInstr.	commit \| commitdiff \| tree
2012-06-08	Andrew Trick	Removing strange "using" declarations form TargetInstrInfo.	commit \| commitdiff \| tree
2012-06-08	Andrew Trick	TargetInstrInfo hooks implemented in codegen should...	commit \| commitdiff \| tree
2012-06-08	Andrew Trick	Sched itinerary fix: Avoid static initializers.	commit \| commitdiff \| tree
2012-06-08	Andrew Trick	Fix Target->Codegen dependence.	commit \| commitdiff \| tree
2012-06-07	Andrew Trick	Continue factoring computeOperandLatency. Use it for...	commit \| commitdiff \| tree
2012-06-07	Andrew Trick	ARM getOperandLatency rewrite.	commit \| commitdiff \| tree
2012-06-07	Andrew Trick	ARM getOperandLatency should return -1 for unknown...	commit \| commitdiff \| tree
2012-06-07	Andrew Trick	Fix ARM getInstrLatency logic to work with the current...	commit \| commitdiff \| tree
2012-06-06	Andrew Trick	Move RegisterClassInfo.h.	commit \| commitdiff \| tree
2012-06-06	Andrew Trick	Move RegisterPressure.h.	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	MachineInstr::eraseFromParent fix for removing bundled...	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	misched: API for minimum vs. expected latency.	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	LoopUnroll: always check for NULL LoopPassManager	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	X86 itinerary properties.	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	ARM itinerary properties.	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	misched: Added MultiIssueItineraries.	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	sdsched: Use the right heuristics when -mcpu is not...	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	misched: Allow disabling scoreboard hazard checking...	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	whitespace	commit \| commitdiff \| tree
2012-06-05	Andrew Trick	misched: comments from code review.	commit \| commitdiff \| tree
2012-05-30	Andrew Trick	SCEV: Handle a corner case reducing AddRecExpr * AddRecExpr	commit \| commitdiff \| tree
2012-05-30	Andrew Trick	Reformat the loop that does AddRecExpr * AddRecExpr...	commit \| commitdiff \| tree
2012-05-25	Andrew Trick	misched: trace formatting	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	misched: Use the same scheduling heuristics with -misched...	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	misched: Trace regpressure.	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	misched: Give each ReadyQ a unique ID	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	misched: Added ScoreboardHazardRecognizer.	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	misched: Release bottom roots in reverse order.	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	misched: rename ReadyQ class	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	misched: copy comments so compareRPDelta is readable...	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	regpressure: Added RegisterPressure::dump	commit \| commitdiff \| tree
2012-05-24	Andrew Trick	regpressure: physreg livein/out fix	commit \| commitdiff \| tree
2012-05-22	Andrew Trick	LSR fix: add a missing phi check during IV hoisting.	commit \| commitdiff \| tree
2012-05-19	Andrew Trick	SCEV: Add MarkPendingLoopPredicates to avoid recursive...	commit \| commitdiff \| tree
2012-05-17	Andrew Trick	comments	commit \| commitdiff \| tree
2012-05-17	Andrew Trick	misched: trace ReadyQ.	commit \| commitdiff \| tree
2012-05-17	Andrew Trick	misched: Added 3-level regpressure back-off.	commit \| commitdiff \| tree
2012-05-17	Andrew Trick	comment	commit \| commitdiff \| tree
2012-05-17	Andrew Trick	regpressure: Fix getMaxUpwardPressureDelta.	commit \| commitdiff \| tree
2012-05-17	Andrew Trick	misched: fix liveness iterators	commit \| commitdiff \| tree
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C/C++ LLVM-based compilers that forbids OOTA behaviors

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