misched: disable SSA check pending PR13112.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158461 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 24b9cd0b45f489d39e535929c5338a02dd4618ae..110f478f48ea78eb30954e9cda135bec2581916f 100644 (file)
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -413,8 +413,10 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
 
   // SSA defs do not have output/anti dependencies.
   // The current operand is a def, so we have at least one.
-  if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
-    return;
+  //
+  // FIXME: This optimization is disabled pending PR13112.
+  //if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
+  //  return;
 
   // Add output dependence to the next nearest def of this vreg.
   //